CoCalc -- cpu-features.h

GitHub Repository: awilliam/linux-vfio
Path: blob/master/arch/mips/include/asm/cpu-features.h
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/*
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 * This file is subject to the terms and conditions of the GNU General Public
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 * License.  See the file "COPYING" in the main directory of this archive
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 * for more details.
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 *
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 * Copyright (C) 2003, 2004 Ralf Baechle
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 * Copyright (C) 2004  Maciej W. Rozycki
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 */
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#ifndef __ASM_CPU_FEATURES_H
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#define __ASM_CPU_FEATURES_H
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#include <asm/cpu.h>
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#include <asm/cpu-info.h>
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#include <cpu-feature-overrides.h>
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#ifndef current_cpu_type
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#define current_cpu_type()      current_cpu_data.cputype
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#endif
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/*
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 * SMP assumption: Options of CPU 0 are a superset of all processors.
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 * This is true for all known MIPS systems.
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 */
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#ifndef cpu_has_tlb
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#define cpu_has_tlb		(cpu_data[0].options & MIPS_CPU_TLB)
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#endif
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#ifndef cpu_has_4kex
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#define cpu_has_4kex		(cpu_data[0].options & MIPS_CPU_4KEX)
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#endif
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#ifndef cpu_has_3k_cache
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#define cpu_has_3k_cache	(cpu_data[0].options & MIPS_CPU_3K_CACHE)
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#endif
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#define cpu_has_6k_cache	0
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#define cpu_has_8k_cache	0
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#ifndef cpu_has_4k_cache
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#define cpu_has_4k_cache	(cpu_data[0].options & MIPS_CPU_4K_CACHE)
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#endif
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#ifndef cpu_has_tx39_cache
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#define cpu_has_tx39_cache	(cpu_data[0].options & MIPS_CPU_TX39_CACHE)
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#endif
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#ifndef cpu_has_octeon_cache
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#define cpu_has_octeon_cache	0
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#endif
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#ifndef cpu_has_fpu
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#define cpu_has_fpu		(current_cpu_data.options & MIPS_CPU_FPU)
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#define raw_cpu_has_fpu		(raw_current_cpu_data.options & MIPS_CPU_FPU)
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#else
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#define raw_cpu_has_fpu		cpu_has_fpu
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#endif
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#ifndef cpu_has_32fpr
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#define cpu_has_32fpr		(cpu_data[0].options & MIPS_CPU_32FPR)
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#endif
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#ifndef cpu_has_counter
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#define cpu_has_counter		(cpu_data[0].options & MIPS_CPU_COUNTER)
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#endif
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#ifndef cpu_has_watch
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#define cpu_has_watch		(cpu_data[0].options & MIPS_CPU_WATCH)
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#endif
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#ifndef cpu_has_divec
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#define cpu_has_divec		(cpu_data[0].options & MIPS_CPU_DIVEC)
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#endif
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#ifndef cpu_has_vce
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#define cpu_has_vce		(cpu_data[0].options & MIPS_CPU_VCE)
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#endif
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#ifndef cpu_has_cache_cdex_p
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#define cpu_has_cache_cdex_p	(cpu_data[0].options & MIPS_CPU_CACHE_CDEX_P)
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#endif
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#ifndef cpu_has_cache_cdex_s
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#define cpu_has_cache_cdex_s	(cpu_data[0].options & MIPS_CPU_CACHE_CDEX_S)
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#endif
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#ifndef cpu_has_prefetch
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#define cpu_has_prefetch	(cpu_data[0].options & MIPS_CPU_PREFETCH)
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#endif
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#ifndef cpu_has_mcheck
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#define cpu_has_mcheck		(cpu_data[0].options & MIPS_CPU_MCHECK)
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#endif
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#ifndef cpu_has_ejtag
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#define cpu_has_ejtag		(cpu_data[0].options & MIPS_CPU_EJTAG)
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#endif
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#ifndef cpu_has_llsc
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#define cpu_has_llsc		(cpu_data[0].options & MIPS_CPU_LLSC)
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#endif
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#ifndef kernel_uses_llsc
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#define kernel_uses_llsc	cpu_has_llsc
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#endif
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#ifndef cpu_has_mips16
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#define cpu_has_mips16		(cpu_data[0].ases & MIPS_ASE_MIPS16)
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#endif
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#ifndef cpu_has_mdmx
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#define cpu_has_mdmx           (cpu_data[0].ases & MIPS_ASE_MDMX)
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#endif
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#ifndef cpu_has_mips3d
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#define cpu_has_mips3d         (cpu_data[0].ases & MIPS_ASE_MIPS3D)
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#endif
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#ifndef cpu_has_smartmips
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#define cpu_has_smartmips      (cpu_data[0].ases & MIPS_ASE_SMARTMIPS)
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#endif
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#ifndef kernel_uses_smartmips_rixi
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#define kernel_uses_smartmips_rixi 0
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#endif
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#ifndef cpu_has_vtag_icache
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#define cpu_has_vtag_icache	(cpu_data[0].icache.flags & MIPS_CACHE_VTAG)
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#endif
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#ifndef cpu_has_dc_aliases
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#define cpu_has_dc_aliases	(cpu_data[0].dcache.flags & MIPS_CACHE_ALIASES)
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#endif
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#ifndef cpu_has_ic_fills_f_dc
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#define cpu_has_ic_fills_f_dc	(cpu_data[0].icache.flags & MIPS_CACHE_IC_F_DC)
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#endif
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#ifndef cpu_has_pindexed_dcache
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#define cpu_has_pindexed_dcache	(cpu_data[0].dcache.flags & MIPS_CACHE_PINDEX)
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#endif
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/*
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 * I-Cache snoops remote store.  This only matters on SMP.  Some multiprocessors
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 * such as the R10000 have I-Caches that snoop local stores; the embedded ones
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 * don't.  For maintaining I-cache coherency this means we need to flush the
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 * D-cache all the way back to whever the I-cache does refills from, so the
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 * I-cache has a chance to see the new data at all.  Then we have to flush the
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 * I-cache also.
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 * Note we may have been rescheduled and may no longer be running on the CPU
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 * that did the store so we can't optimize this into only doing the flush on
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 * the local CPU.
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 */
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#ifndef cpu_icache_snoops_remote_store
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#ifdef CONFIG_SMP
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#define cpu_icache_snoops_remote_store	(cpu_data[0].icache.flags & MIPS_IC_SNOOPS_REMOTE)
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#else
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#define cpu_icache_snoops_remote_store	1
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#endif
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#endif
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# ifndef cpu_has_mips32r1
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# define cpu_has_mips32r1	(cpu_data[0].isa_level & MIPS_CPU_ISA_M32R1)
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# endif
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# ifndef cpu_has_mips32r2
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# define cpu_has_mips32r2	(cpu_data[0].isa_level & MIPS_CPU_ISA_M32R2)
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# endif
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# ifndef cpu_has_mips64r1
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# define cpu_has_mips64r1	(cpu_data[0].isa_level & MIPS_CPU_ISA_M64R1)
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# endif
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# ifndef cpu_has_mips64r2
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# define cpu_has_mips64r2	(cpu_data[0].isa_level & MIPS_CPU_ISA_M64R2)
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# endif
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/*
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 * Shortcuts ...
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 */
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#define cpu_has_mips32	(cpu_has_mips32r1 | cpu_has_mips32r2)
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#define cpu_has_mips64	(cpu_has_mips64r1 | cpu_has_mips64r2)
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#define cpu_has_mips_r1	(cpu_has_mips32r1 | cpu_has_mips64r1)
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#define cpu_has_mips_r2	(cpu_has_mips32r2 | cpu_has_mips64r2)
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#define cpu_has_mips_r	(cpu_has_mips32r1 | cpu_has_mips32r2 | \
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			 cpu_has_mips64r1 | cpu_has_mips64r2)
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#ifndef cpu_has_mips_r2_exec_hazard
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#define cpu_has_mips_r2_exec_hazard cpu_has_mips_r2
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#endif
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/*
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 * MIPS32, MIPS64, VR5500, IDT32332, IDT32334 and maybe a few other
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 * pre-MIPS32/MIPS53 processors have CLO, CLZ.  The IDT RC64574 is 64-bit and
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 * has CLO and CLZ but not DCLO nor DCLZ.  For 64-bit kernels
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 * cpu_has_clo_clz also indicates the availability of DCLO and DCLZ.
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 */
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# ifndef cpu_has_clo_clz
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# define cpu_has_clo_clz	cpu_has_mips_r
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# endif
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#ifndef cpu_has_dsp
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#define cpu_has_dsp		(cpu_data[0].ases & MIPS_ASE_DSP)
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#endif
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#ifndef cpu_has_mipsmt
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#define cpu_has_mipsmt		(cpu_data[0].ases & MIPS_ASE_MIPSMT)
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#endif
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#ifndef cpu_has_userlocal
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#define cpu_has_userlocal	(cpu_data[0].options & MIPS_CPU_ULRI)
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#endif
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#ifdef CONFIG_32BIT
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# ifndef cpu_has_nofpuex
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# define cpu_has_nofpuex	(cpu_data[0].options & MIPS_CPU_NOFPUEX)
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# endif
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# ifndef cpu_has_64bits
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# define cpu_has_64bits		(cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT)
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# endif
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# ifndef cpu_has_64bit_zero_reg
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# define cpu_has_64bit_zero_reg	(cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT)
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# endif
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# ifndef cpu_has_64bit_gp_regs
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# define cpu_has_64bit_gp_regs		0
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# endif
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# ifndef cpu_has_64bit_addresses
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# define cpu_has_64bit_addresses	0
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# endif
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# ifndef cpu_vmbits
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# define cpu_vmbits 31
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# endif
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#endif
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#ifdef CONFIG_64BIT
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# ifndef cpu_has_nofpuex
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# define cpu_has_nofpuex		0
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# endif
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# ifndef cpu_has_64bits
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# define cpu_has_64bits			1
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# endif
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# ifndef cpu_has_64bit_zero_reg
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# define cpu_has_64bit_zero_reg		1
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# endif
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# ifndef cpu_has_64bit_gp_regs
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# define cpu_has_64bit_gp_regs		1
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# endif
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# ifndef cpu_has_64bit_addresses
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# define cpu_has_64bit_addresses	1
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# endif
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# ifndef cpu_vmbits
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# define cpu_vmbits cpu_data[0].vmbits
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# define __NEED_VMBITS_PROBE
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# endif
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#endif
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#if defined(CONFIG_CPU_MIPSR2_IRQ_VI) && !defined(cpu_has_vint)
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# define cpu_has_vint		(cpu_data[0].options & MIPS_CPU_VINT)
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#elif !defined(cpu_has_vint)
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# define cpu_has_vint			0
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#endif
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#if defined(CONFIG_CPU_MIPSR2_IRQ_EI) && !defined(cpu_has_veic)
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# define cpu_has_veic		(cpu_data[0].options & MIPS_CPU_VEIC)
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#elif !defined(cpu_has_veic)
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# define cpu_has_veic			0
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#endif
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#ifndef cpu_has_inclusive_pcaches
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#define cpu_has_inclusive_pcaches	(cpu_data[0].options & MIPS_CPU_INCLUSIVE_CACHES)
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#endif
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#ifndef cpu_dcache_line_size
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#define cpu_dcache_line_size()	cpu_data[0].dcache.linesz
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#endif
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#ifndef cpu_icache_line_size
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#define cpu_icache_line_size()	cpu_data[0].icache.linesz
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#endif
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#ifndef cpu_scache_line_size
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#define cpu_scache_line_size()	cpu_data[0].scache.linesz
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#endif
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#ifndef cpu_hwrena_impl_bits
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#define cpu_hwrena_impl_bits		0
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#endif
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#endif /* __ASM_CPU_FEATURES_H */
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