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awilliam
GitHub Repository: awilliam/linux-vfio
 Path: blob/master/arch/mips/include/asm/cpu-info.h
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/*

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 * This file is subject to the terms and conditions of the GNU General Public

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 * License.  See the file "COPYING" in the main directory of this archive

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 * for more details.

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 *

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 * Copyright (C) 1994 Waldorf GMBH

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 * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2001, 2002, 2003 Ralf Baechle

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 * Copyright (C) 1996 Paul M. Antoine

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 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.

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 * Copyright (C) 2004  Maciej W. Rozycki

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 */

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#ifndef __ASM_CPU_INFO_H

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#define __ASM_CPU_INFO_H

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#include <linux/types.h>

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#include <asm/cache.h>

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/*

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 * Descriptor for a cache

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 */

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struct cache_desc {

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	unsigned int waysize;	/* Bytes per way */

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	unsigned short sets;	/* Number of lines per set */

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	unsigned char ways;	/* Number of ways */

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	unsigned char linesz;	/* Size of line in bytes */

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	unsigned char waybit;	/* Bits to select in a cache set */

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	unsigned char flags;	/* Flags describing cache properties */

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};

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/*

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 * Flag definitions

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 */

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#define MIPS_CACHE_NOT_PRESENT	0x00000001

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#define MIPS_CACHE_VTAG		0x00000002	/* Virtually tagged cache */

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#define MIPS_CACHE_ALIASES	0x00000004	/* Cache could have aliases */

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#define MIPS_CACHE_IC_F_DC	0x00000008	/* Ic can refill from D-cache */

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#define MIPS_IC_SNOOPS_REMOTE	0x00000010	/* Ic snoops remote stores */

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#define MIPS_CACHE_PINDEX	0x00000020	/* Physically indexed cache */

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struct cpuinfo_mips {

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	unsigned int		udelay_val;

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	unsigned int		asid_cache;

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	/*

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	 * Capability and feature descriptor structure for MIPS CPU

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	 */

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	unsigned long		options;

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	unsigned long		ases;

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	unsigned int		processor_id;

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	unsigned int		fpu_id;

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	unsigned int		cputype;

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	int			isa_level;

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	int			tlbsize;

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	struct cache_desc	icache;	/* Primary I-cache */

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	struct cache_desc	dcache;	/* Primary D or combined I/D cache */

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	struct cache_desc	scache;	/* Secondary cache */

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	struct cache_desc	tcache;	/* Tertiary/split secondary cache */

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	int			srsets;	/* Shadow register sets */

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	int			core;	/* physical core number */

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#ifdef CONFIG_64BIT

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	int			vmbits;	/* Virtual memory size in bits */

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#endif

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#if defined(CONFIG_MIPS_MT_SMP) || defined(CONFIG_MIPS_MT_SMTC)

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	/*

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	 * In the MIPS MT "SMTC" model, each TC is considered

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	 * to be a "CPU" for the purposes of scheduling, but

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	 * exception resources, ASID spaces, etc, are common

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	 * to all TCs within the same VPE.

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	 */

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	int			vpe_id;  /* Virtual Processor number */

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#endif

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#ifdef CONFIG_MIPS_MT_SMTC

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	int			tc_id;   /* Thread Context number */

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#endif

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	void 			*data;	/* Additional data */

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	unsigned int		watch_reg_count;   /* Number that exist */

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	unsigned int		watch_reg_use_cnt; /* Usable by ptrace */

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#define NUM_WATCH_REGS 4

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	u16			watch_reg_masks[NUM_WATCH_REGS];

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	unsigned int		kscratch_mask; /* Usable KScratch mask. */

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} __attribute__((aligned(SMP_CACHE_BYTES)));

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extern struct cpuinfo_mips cpu_data[];

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#define current_cpu_data cpu_data[smp_processor_id()]

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#define raw_current_cpu_data cpu_data[raw_smp_processor_id()]

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extern void cpu_probe(void);

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extern void cpu_report(void);

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extern const char *__cpu_name[];

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#define cpu_name_string()	__cpu_name[smp_processor_id()]

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#endif /* __ASM_CPU_INFO_H */

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