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awilliam
GitHub Repository: awilliam/linux-vfio
 Path: blob/master/arch/mips/pci/ops-mace.c
10820 views
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/*

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 * This file is subject to the terms and conditions of the GNU General Public

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 * License.  See the file "COPYING" in the main directory of this archive

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 * for more details.

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 *

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 * Copyright (C) 2000, 2001 Keith M Wesolowski

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 */

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#include <linux/kernel.h>

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#include <linux/init.h>

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#include <linux/pci.h>

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#include <linux/types.h>

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#include <asm/pci.h>

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#include <asm/ip32/mace.h>

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#if 0

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# define DPRINTK(args...) printk(args);

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#else

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# define DPRINTK(args...)

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#endif

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/*

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 * O2 has up to 5 PCI devices connected into the MACE bridge.  The device

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 * map looks like this:

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 *

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 * 0  aic7xxx 0

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 * 1  aic7xxx 1

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 * 2  expansion slot

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 * 3  N/C

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 * 4  N/C

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 */

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static inline int mkaddr(struct pci_bus *bus, unsigned int devfn,

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	unsigned int reg)

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{

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	return ((bus->number & 0xff) << 16) |

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		((devfn & 0xff) << 8) |

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		(reg & 0xfc);

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}

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static int

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mace_pci_read_config(struct pci_bus *bus, unsigned int devfn,

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		     int reg, int size, u32 *val)

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{

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	u32 control = mace->pci.control;

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	/* disable master aborts interrupts during config read */

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	mace->pci.control = control & ~MACEPCI_CONTROL_MAR_INT;

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	mace->pci.config_addr = mkaddr(bus, devfn, reg);

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	switch (size) {

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	case 1:

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		*val = mace->pci.config_data.b[(reg & 3) ^ 3];

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		break;

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	case 2:

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		*val = mace->pci.config_data.w[((reg >> 1) & 1) ^ 1];

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		break;

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	case 4:

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		*val = mace->pci.config_data.l;

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		break;

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	}

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	/* ack possible master abort */

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	mace->pci.error &= ~MACEPCI_ERROR_MASTER_ABORT;

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	mace->pci.control = control;

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	/*

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	 * someone forgot to set the ultra bit for the onboard

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	 * scsi chips; we fake it here

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	 */

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	if (bus->number == 0 && reg == 0x40 && size == 4 &&

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	    (devfn == (1 << 3) || devfn == (2 << 3)))

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		*val |= 0x1000;

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	DPRINTK("read%d: reg=%08x,val=%02x\n", size * 8, reg, *val);

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	return PCIBIOS_SUCCESSFUL;

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}

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static int

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mace_pci_write_config(struct pci_bus *bus, unsigned int devfn,

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		      int reg, int size, u32 val)

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{

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	mace->pci.config_addr = mkaddr(bus, devfn, reg);

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	switch (size) {

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	case 1:

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		mace->pci.config_data.b[(reg & 3) ^ 3] = val;

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		break;

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	case 2:

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		mace->pci.config_data.w[((reg >> 1) & 1) ^ 1] = val;

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		break;

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	case 4:

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		mace->pci.config_data.l = val;

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		break;

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	}

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	DPRINTK("write%d: reg=%08x,val=%02x\n", size * 8, reg, val);

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	return PCIBIOS_SUCCESSFUL;

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}

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struct pci_ops mace_pci_ops = {

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	.read = mace_pci_read_config,

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	.write = mace_pci_write_config,

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};

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