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awilliam
GitHub Repository: awilliam/linux-vfio
 Path: blob/master/arch/mips/pci/ops-nile4.c
10820 views
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#include <linux/kernel.h>

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#include <linux/init.h>

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#include <linux/pci.h>

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#include <asm/bootinfo.h>

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#include <asm/lasat/lasat.h>

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#include <asm/gt64120.h>

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#include <asm/nile4.h>

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#define PCI_ACCESS_READ  0

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#define PCI_ACCESS_WRITE 1

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#define LO(reg) (reg / 4)

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#define HI(reg) (reg / 4 + 1)

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volatile unsigned long *const vrc_pciregs = (void *) Vrc5074_BASE;

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static DEFINE_SPINLOCK(nile4_pci_lock);

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static int nile4_pcibios_config_access(unsigned char access_type,

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	struct pci_bus *bus, unsigned int devfn, int where, u32 *val)

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{

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	unsigned char busnum = bus->number;

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	u32 adr, mask, err;

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	if ((busnum == 0) && (PCI_SLOT(devfn) > 8))

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		/* The addressing scheme chosen leaves room for just

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		 * 8 devices on the first busnum (besides the PCI

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		 * controller itself) */

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		return PCIBIOS_DEVICE_NOT_FOUND;

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	if ((busnum == 0) && (devfn == PCI_DEVFN(0, 0))) {

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		/* Access controller registers directly */

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		if (access_type == PCI_ACCESS_WRITE) {

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			vrc_pciregs[(0x200 + where) >> 2] = *val;

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		} else {

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			*val = vrc_pciregs[(0x200 + where) >> 2];

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		}

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		return PCIBIOS_SUCCESSFUL;

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	}

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	/* Temporarily map PCI Window 1 to config space */

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	mask = vrc_pciregs[LO(NILE4_PCIINIT1)];

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	vrc_pciregs[LO(NILE4_PCIINIT1)] = 0x0000001a | (busnum ? 0x200 : 0);

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	/* Clear PCI Error register. This also clears the Error Type

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	 * bits in the Control register */

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	vrc_pciregs[LO(NILE4_PCIERR)] = 0;

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	vrc_pciregs[HI(NILE4_PCIERR)] = 0;

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	/* Setup address */

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	if (busnum == 0)

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		adr =

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		    KSEG1ADDR(PCI_WINDOW1) +

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		    ((1 << (PCI_SLOT(devfn) + 15)) | (PCI_FUNC(devfn) << 8)

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		     | (where & ~3));

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	else

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		adr = KSEG1ADDR(PCI_WINDOW1) | (busnum << 16) | (devfn << 8) |

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		      (where & ~3);

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	if (access_type == PCI_ACCESS_WRITE)

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		*(u32 *) adr = *val;

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	else

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		*val = *(u32 *) adr;

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	/* Check for master or target abort */

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	err = (vrc_pciregs[HI(NILE4_PCICTRL)] >> 5) & 0x7;

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	/* Restore PCI Window 1 */

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	vrc_pciregs[LO(NILE4_PCIINIT1)] = mask;

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	if (err)

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		return PCIBIOS_DEVICE_NOT_FOUND;

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	return PCIBIOS_SUCCESSFUL;

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}

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static int nile4_pcibios_read(struct pci_bus *bus, unsigned int devfn,

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	int where, int size, u32 *val)

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{

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	unsigned long flags;

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	u32 data = 0;

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	int err;

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	if ((size == 2) && (where & 1))

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		return PCIBIOS_BAD_REGISTER_NUMBER;

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	else if ((size == 4) && (where & 3))

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		return PCIBIOS_BAD_REGISTER_NUMBER;

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	spin_lock_irqsave(&nile4_pci_lock, flags);

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	err = nile4_pcibios_config_access(PCI_ACCESS_READ, bus, devfn, where,

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					&data);

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	spin_unlock_irqrestore(&nile4_pci_lock, flags);

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	if (err)

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		return err;

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	if (size == 1)

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		*val = (data >> ((where & 3) << 3)) & 0xff;

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	else if (size == 2)

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		*val = (data >> ((where & 3) << 3)) & 0xffff;

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	else

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		*val = data;

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	return PCIBIOS_SUCCESSFUL;

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}

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static int nile4_pcibios_write(struct pci_bus *bus, unsigned int devfn,

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	int where, int size, u32 val)

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{

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	unsigned long flags;

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	u32 data = 0;

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	int err;

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	if ((size == 2) && (where & 1))

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		return PCIBIOS_BAD_REGISTER_NUMBER;

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	else if ((size == 4) && (where & 3))

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		return PCIBIOS_BAD_REGISTER_NUMBER;

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	spin_lock_irqsave(&nile4_pci_lock, flags);

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	err = nile4_pcibios_config_access(PCI_ACCESS_READ, bus, devfn, where,

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					  &data);

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	spin_unlock_irqrestore(&nile4_pci_lock, flags);

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	if (err)

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		return err;

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	if (size == 1)

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		data = (data & ~(0xff << ((where & 3) << 3))) |

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		    (val << ((where & 3) << 3));

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	else if (size == 2)

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		data = (data & ~(0xffff << ((where & 3) << 3))) |

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		    (val << ((where & 3) << 3));

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	else

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		data = val;

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	if (nile4_pcibios_config_access

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	    (PCI_ACCESS_WRITE, bus, devfn, where, &data))

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		return -1;

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	return PCIBIOS_SUCCESSFUL;

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}

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struct pci_ops nile4_pci_ops = {

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	.read = nile4_pcibios_read,

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	.write = nile4_pcibios_write,

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};

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