Path: blob/master/arch/mips/pnx833x/common/platform.c
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/*1* platform.c: platform support for PNX833X.2*3* Copyright 2008 NXP Semiconductors4* Chris Steel <[email protected]>5* Daniel Laird <[email protected]>6*7* Based on software written by:8* Nikita Youshchenko <[email protected]>, based on PNX8550 code.9*10* This program is free software; you can redistribute it and/or modify11* it under the terms of the GNU General Public License as published by12* the Free Software Foundation; either version 2 of the License, or13* (at your option) any later version.14*15* This program is distributed in the hope that it will be useful,16* but WITHOUT ANY WARRANTY; without even the implied warranty of17* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the18* GNU General Public License for more details.19*20* You should have received a copy of the GNU General Public License21* along with this program; if not, write to the Free Software22* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.23*/24#include <linux/device.h>25#include <linux/dma-mapping.h>26#include <linux/platform_device.h>27#include <linux/kernel.h>28#include <linux/init.h>29#include <linux/resource.h>30#include <linux/serial.h>31#include <linux/serial_pnx8xxx.h>32#include <linux/mtd/nand.h>33#include <linux/mtd/partitions.h>3435#ifdef CONFIG_I2C_PNX010536/* Until i2c driver available in kernel.*/37#include <linux/i2c-pnx0105.h>38#endif3940#include <irq.h>41#include <irq-mapping.h>42#include <pnx833x.h>4344static u64 uart_dmamask = DMA_BIT_MASK(32);4546static struct resource pnx833x_uart_resources[] = {47[0] = {48.start = PNX833X_UART0_PORTS_START,49.end = PNX833X_UART0_PORTS_END,50.flags = IORESOURCE_MEM,51},52[1] = {53.start = PNX833X_PIC_UART0_INT,54.end = PNX833X_PIC_UART0_INT,55.flags = IORESOURCE_IRQ,56},57[2] = {58.start = PNX833X_UART1_PORTS_START,59.end = PNX833X_UART1_PORTS_END,60.flags = IORESOURCE_MEM,61},62[3] = {63.start = PNX833X_PIC_UART1_INT,64.end = PNX833X_PIC_UART1_INT,65.flags = IORESOURCE_IRQ,66},67};6869struct pnx8xxx_port pnx8xxx_ports[] = {70[0] = {71.port = {72.type = PORT_PNX8XXX,73.iotype = UPIO_MEM,74.membase = (void __iomem *)PNX833X_UART0_PORTS_START,75.mapbase = PNX833X_UART0_PORTS_START,76.irq = PNX833X_PIC_UART0_INT,77.uartclk = 3692300,78.fifosize = 16,79.flags = UPF_BOOT_AUTOCONF,80.line = 0,81},82},83[1] = {84.port = {85.type = PORT_PNX8XXX,86.iotype = UPIO_MEM,87.membase = (void __iomem *)PNX833X_UART1_PORTS_START,88.mapbase = PNX833X_UART1_PORTS_START,89.irq = PNX833X_PIC_UART1_INT,90.uartclk = 3692300,91.fifosize = 16,92.flags = UPF_BOOT_AUTOCONF,93.line = 1,94},95},96};9798static struct platform_device pnx833x_uart_device = {99.name = "pnx8xxx-uart",100.id = -1,101.dev = {102.dma_mask = &uart_dmamask,103.coherent_dma_mask = DMA_BIT_MASK(32),104.platform_data = pnx8xxx_ports,105},106.num_resources = ARRAY_SIZE(pnx833x_uart_resources),107.resource = pnx833x_uart_resources,108};109110static u64 ehci_dmamask = DMA_BIT_MASK(32);111112static struct resource pnx833x_usb_ehci_resources[] = {113[0] = {114.start = PNX833X_USB_PORTS_START,115.end = PNX833X_USB_PORTS_END,116.flags = IORESOURCE_MEM,117},118[1] = {119.start = PNX833X_PIC_USB_INT,120.end = PNX833X_PIC_USB_INT,121.flags = IORESOURCE_IRQ,122},123};124125static struct platform_device pnx833x_usb_ehci_device = {126.name = "pnx833x-ehci",127.id = -1,128.dev = {129.dma_mask = &ehci_dmamask,130.coherent_dma_mask = DMA_BIT_MASK(32),131},132.num_resources = ARRAY_SIZE(pnx833x_usb_ehci_resources),133.resource = pnx833x_usb_ehci_resources,134};135136#ifdef CONFIG_I2C_PNX0105137static struct resource pnx833x_i2c0_resources[] = {138{139.start = PNX833X_I2C0_PORTS_START,140.end = PNX833X_I2C0_PORTS_END,141.flags = IORESOURCE_MEM,142},143{144.start = PNX833X_PIC_I2C0_INT,145.end = PNX833X_PIC_I2C0_INT,146.flags = IORESOURCE_IRQ,147},148};149150static struct resource pnx833x_i2c1_resources[] = {151{152.start = PNX833X_I2C1_PORTS_START,153.end = PNX833X_I2C1_PORTS_END,154.flags = IORESOURCE_MEM,155},156{157.start = PNX833X_PIC_I2C1_INT,158.end = PNX833X_PIC_I2C1_INT,159.flags = IORESOURCE_IRQ,160},161};162163static struct i2c_pnx0105_dev pnx833x_i2c_dev[] = {164{165.base = PNX833X_I2C0_PORTS_START,166.irq = -1, /* should be PNX833X_PIC_I2C0_INT but polling is faster */167.clock = 6, /* 0 == 400 kHz, 4 == 100 kHz(Maximum HDMI), 6 = 50kHz(Preferred HDCP) */168.bus_addr = 0, /* no slave support */169},170{171.base = PNX833X_I2C1_PORTS_START,172.irq = -1, /* on high freq, polling is faster */173/*.irq = PNX833X_PIC_I2C1_INT,*/174.clock = 4, /* 0 == 400 kHz, 4 == 100 kHz. 100 kHz seems a safe default for now */175.bus_addr = 0, /* no slave support */176},177};178179static struct platform_device pnx833x_i2c0_device = {180.name = "i2c-pnx0105",181.id = 0,182.dev = {183.platform_data = &pnx833x_i2c_dev[0],184},185.num_resources = ARRAY_SIZE(pnx833x_i2c0_resources),186.resource = pnx833x_i2c0_resources,187};188189static struct platform_device pnx833x_i2c1_device = {190.name = "i2c-pnx0105",191.id = 1,192.dev = {193.platform_data = &pnx833x_i2c_dev[1],194},195.num_resources = ARRAY_SIZE(pnx833x_i2c1_resources),196.resource = pnx833x_i2c1_resources,197};198#endif199200static u64 ethernet_dmamask = DMA_BIT_MASK(32);201202static struct resource pnx833x_ethernet_resources[] = {203[0] = {204.start = PNX8335_IP3902_PORTS_START,205.end = PNX8335_IP3902_PORTS_END,206.flags = IORESOURCE_MEM,207},208[1] = {209.start = PNX8335_PIC_ETHERNET_INT,210.end = PNX8335_PIC_ETHERNET_INT,211.flags = IORESOURCE_IRQ,212},213};214215static struct platform_device pnx833x_ethernet_device = {216.name = "ip3902-eth",217.id = -1,218.dev = {219.dma_mask = ðernet_dmamask,220.coherent_dma_mask = DMA_BIT_MASK(32),221},222.num_resources = ARRAY_SIZE(pnx833x_ethernet_resources),223.resource = pnx833x_ethernet_resources,224};225226static struct resource pnx833x_sata_resources[] = {227[0] = {228.start = PNX8335_SATA_PORTS_START,229.end = PNX8335_SATA_PORTS_END,230.flags = IORESOURCE_MEM,231},232[1] = {233.start = PNX8335_PIC_SATA_INT,234.end = PNX8335_PIC_SATA_INT,235.flags = IORESOURCE_IRQ,236},237};238239static struct platform_device pnx833x_sata_device = {240.name = "pnx833x-sata",241.id = -1,242.num_resources = ARRAY_SIZE(pnx833x_sata_resources),243.resource = pnx833x_sata_resources,244};245246static const char *part_probes[] = {247"cmdlinepart",248NULL249};250251static void252pnx833x_flash_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)253{254struct nand_chip *this = mtd->priv;255unsigned long nandaddr = (unsigned long)this->IO_ADDR_W;256257if (cmd == NAND_CMD_NONE)258return;259260if (ctrl & NAND_CLE)261writeb(cmd, (void __iomem *)(nandaddr + PNX8335_NAND_CLE_MASK));262else263writeb(cmd, (void __iomem *)(nandaddr + PNX8335_NAND_ALE_MASK));264}265266static struct platform_nand_data pnx833x_flash_nand_data = {267.chip = {268.nr_chips = 1,269.chip_delay = 25,270.part_probe_types = part_probes,271},272.ctrl = {273.cmd_ctrl = pnx833x_flash_nand_cmd_ctrl274}275};276277/*278* Set start to be the correct address (PNX8335_NAND_BASE with no 0xb!!),279* 12 bytes more seems to be the standard that allows for NAND access.280*/281static struct resource pnx833x_flash_nand_resource = {282.start = PNX8335_NAND_BASE,283.end = PNX8335_NAND_BASE + 12,284.flags = IORESOURCE_MEM,285};286287static struct platform_device pnx833x_flash_nand = {288.name = "gen_nand",289.id = -1,290.num_resources = 1,291.resource = &pnx833x_flash_nand_resource,292.dev = {293.platform_data = &pnx833x_flash_nand_data,294},295};296297static struct platform_device *pnx833x_platform_devices[] __initdata = {298&pnx833x_uart_device,299&pnx833x_usb_ehci_device,300#ifdef CONFIG_I2C_PNX0105301&pnx833x_i2c0_device,302&pnx833x_i2c1_device,303#endif304&pnx833x_ethernet_device,305&pnx833x_sata_device,306&pnx833x_flash_nand,307};308309static int __init pnx833x_platform_init(void)310{311int res;312313res = platform_add_devices(pnx833x_platform_devices,314ARRAY_SIZE(pnx833x_platform_devices));315316return res;317}318319arch_initcall(pnx833x_platform_init);320321322