Path: blob/master/arch/mn10300/include/asm/hardirq.h
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/* MN10300 Hardware IRQ statistics and management1*2* Copyright (C) 2007 Matsushita Electric Industrial Co., Ltd.3* Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.4* Modified by David Howells ([email protected])5*6* This program is free software; you can redistribute it and/or7* modify it under the terms of the GNU General Public Licence8* as published by the Free Software Foundation; either version9* 2 of the Licence, or (at your option) any later version.10*/11#ifndef _ASM_HARDIRQ_H12#define _ASM_HARDIRQ_H1314#include <linux/threads.h>15#include <linux/irq.h>16#include <asm/exceptions.h>1718/* assembly code in softirq.h is sensitive to the offsets of these fields */19typedef struct {20unsigned int __softirq_pending;21#ifdef CONFIG_MN10300_WD_TIMER22unsigned int __nmi_count; /* arch dependent */23unsigned int __irq_count; /* arch dependent */24#endif25} ____cacheline_aligned irq_cpustat_t;2627#include <linux/irq_cpustat.h> /* Standard mappings for irq_cpustat_t above */2829extern void ack_bad_irq(int irq);3031/*32* manipulate stubs in the MN10300 CPU Trap/Interrupt Vector table33* - these should jump to __common_exception in entry.S unless there's a good34* reason to do otherwise (see trap_preinit() in traps.c)35*/36typedef void (*intr_stub_fnx)(struct pt_regs *regs,37enum exception_code intcode);3839/*40* manipulate pointers in the Exception table (see entry.S)41* - these are indexed by decoding the lower 24 bits of the TBR register42* - note that the MN103E010 doesn't always trap through the correct vector,43* but does always set the TBR correctly44*/45extern asmlinkage void set_excp_vector(enum exception_code code,46intr_stub_fnx handler);4748#endif /* _ASM_HARDIRQ_H */495051