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awilliam
GitHub Repository: awilliam/linux-vfio
 Path: blob/master/arch/mn10300/proc-mn103e010/proc-init.c
10817 views
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/* MN103E010 Processor initialisation

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 *

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 * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.

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 * Written by David Howells ([email protected])

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 *

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 * This program is free software; you can redistribute it and/or

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 * modify it under the terms of the GNU General Public Licence

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 * as published by the Free Software Foundation; either version

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 * 2 of the Licence, or (at your option) any later version.

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 */

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#include <linux/kernel.h>

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#include <asm/fpu.h>

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#include <asm/rtc.h>

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#include <asm/busctl-regs.h>

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/*

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 * initialise the on-silicon processor peripherals

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 */

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asmlinkage void __init processor_init(void)

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{

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	int loop;

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	/* set up the exception table first */

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	for (loop = 0x000; loop < 0x400; loop += 8)

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		__set_intr_stub(loop, __common_exception);

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	__set_intr_stub(EXCEP_ITLBMISS,		itlb_miss);

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	__set_intr_stub(EXCEP_DTLBMISS,		dtlb_miss);

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	__set_intr_stub(EXCEP_IAERROR,		itlb_aerror);

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	__set_intr_stub(EXCEP_DAERROR,		dtlb_aerror);

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	__set_intr_stub(EXCEP_BUSERROR,		raw_bus_error);

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	__set_intr_stub(EXCEP_DOUBLE_FAULT,	double_fault);

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	__set_intr_stub(EXCEP_FPU_DISABLED,	fpu_disabled);

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	__set_intr_stub(EXCEP_SYSCALL0,		system_call);

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	__set_intr_stub(EXCEP_NMI,		nmi_handler);

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	__set_intr_stub(EXCEP_WDT,		nmi_handler);

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	__set_intr_stub(EXCEP_IRQ_LEVEL0,	irq_handler);

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	__set_intr_stub(EXCEP_IRQ_LEVEL1,	irq_handler);

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	__set_intr_stub(EXCEP_IRQ_LEVEL2,	irq_handler);

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	__set_intr_stub(EXCEP_IRQ_LEVEL3,	irq_handler);

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	__set_intr_stub(EXCEP_IRQ_LEVEL4,	irq_handler);

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	__set_intr_stub(EXCEP_IRQ_LEVEL5,	irq_handler);

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	__set_intr_stub(EXCEP_IRQ_LEVEL6,	irq_handler);

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	IVAR0 = EXCEP_IRQ_LEVEL0;

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	IVAR1 = EXCEP_IRQ_LEVEL1;

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	IVAR2 = EXCEP_IRQ_LEVEL2;

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	IVAR3 = EXCEP_IRQ_LEVEL3;

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	IVAR4 = EXCEP_IRQ_LEVEL4;

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	IVAR5 = EXCEP_IRQ_LEVEL5;

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	IVAR6 = EXCEP_IRQ_LEVEL6;

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	mn10300_dcache_flush_inv();

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	mn10300_icache_inv();

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	/* disable all interrupts and set to priority 6 (lowest) */

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	for (loop = 0; loop < NR_IRQS; loop++)

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		GxICR(loop) = GxICR_LEVEL_6 | GxICR_DETECT;

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	/* clear the timers */

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	TM0MD	= 0;

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	TM1MD	= 0;

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	TM2MD	= 0;

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	TM3MD	= 0;

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	TM4MD	= 0;

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	TM5MD	= 0;

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	TM6MD	= 0;

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	TM6MDA	= 0;

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	TM6MDB	= 0;

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	TM7MD	= 0;

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	TM8MD	= 0;

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	TM9MD	= 0;

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	TM10MD	= 0;

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	TM11MD	= 0;

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	calibrate_clock();

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}

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/*

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 * determine the memory size and base from the memory controller regs

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 */

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void __init get_mem_info(unsigned long *mem_base, unsigned long *mem_size)

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{

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	unsigned long base, size;

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	*mem_base = 0;

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	*mem_size = 0;

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	base = SDBASE(0);

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	if (base & SDBASE_CE) {

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		size = (base & SDBASE_CBAM) << SDBASE_CBAM_SHIFT;

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		size = ~size + 1;

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		base &= SDBASE_CBA;

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		printk(KERN_INFO "SDRAM[0]: %luMb @%08lx\n", size >> 20, base);

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		*mem_size += size;

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		*mem_base = base;

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	}

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	base = SDBASE(1);

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	if (base & SDBASE_CE) {

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		size = (base & SDBASE_CBAM) << SDBASE_CBAM_SHIFT;

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		size = ~size + 1;

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		base &= SDBASE_CBA;

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		printk(KERN_INFO "SDRAM[1]: %luMb @%08lx\n", size >> 20, base);

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		*mem_size += size;

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		if (*mem_base == 0)

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			*mem_base = base;

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	}

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}

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