CoCalc -- nand-regs.h

GitHub Repository: awilliam/linux-vfio
Path: blob/master/arch/mn10300/proc-mn2ws0050/include/proc/nand-regs.h
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/* NAND flash interface register definitions
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 *
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 * Copyright (C) 2008-2009 Panasonic Corporation
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 * All Rights Reserved.
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 *
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 * This program is free software; you can redistribute it and/or
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 * modify it under the terms of the GNU General Public License
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 * version 2 as published by the Free Software Foundation.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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 * GNU General Public License for more details.
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 */
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#ifndef	_PROC_NAND_REGS_H_
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#define	_PROC_NAND_REGS_H_
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/* command register */
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#define FCOMMAND_0		__SYSREG(0xd8f00000, u8) /* fcommand[24:31] */
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#define FCOMMAND_1		__SYSREG(0xd8f00001, u8) /* fcommand[16:23] */
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#define FCOMMAND_2		__SYSREG(0xd8f00002, u8) /* fcommand[8:15] */
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#define FCOMMAND_3		__SYSREG(0xd8f00003, u8) /* fcommand[0:7] */
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/* for dma 16 byte trans, use FCOMMAND2 register */
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#define FCOMMAND2_0		__SYSREG(0xd8f00110, u8) /* fcommand2[24:31] */
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#define FCOMMAND2_1		__SYSREG(0xd8f00111, u8) /* fcommand2[16:23] */
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#define FCOMMAND2_2		__SYSREG(0xd8f00112, u8) /* fcommand2[8:15] */
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#define FCOMMAND2_3		__SYSREG(0xd8f00113, u8) /* fcommand2[0:7] */
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#define FCOMMAND_FIEN		0x80		/* nand flash I/F enable */
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#define FCOMMAND_BW_8BIT	0x00		/* 8bit bus width */
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#define FCOMMAND_BW_16BIT	0x40		/* 16bit bus width */
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#define FCOMMAND_BLOCKSZ_SMALL	0x00		/* small block */
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#define FCOMMAND_BLOCKSZ_LARGE	0x20		/* large block */
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#define FCOMMAND_DMASTART	0x10		/* dma start */
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#define FCOMMAND_RYBY		0x08		/* ready/busy flag */
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#define FCOMMAND_RYBYINTMSK	0x04		/* mask ready/busy interrupt */
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#define FCOMMAND_XFWP		0x02		/* write protect enable */
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#define FCOMMAND_XFCE		0x01		/* flash device disable */
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#define FCOMMAND_SEQKILL	0x10		/* stop seq-read */
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#define FCOMMAND_ANUM		0x07		/* address cycle */
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#define FCOMMAND_ANUM_NONE	0x00		/* address cycle none */
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#define FCOMMAND_ANUM_1CYC	0x01		/* address cycle 1cycle */
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#define FCOMMAND_ANUM_2CYC	0x02		/* address cycle 2cycle */
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#define FCOMMAND_ANUM_3CYC	0x03		/* address cycle 3cycle */
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#define FCOMMAND_ANUM_4CYC	0x04		/* address cycle 4cycle */
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#define FCOMMAND_ANUM_5CYC	0x05		/* address cycle 5cycle */
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#define FCOMMAND_FCMD_READ0	0x00		/* read1 command */
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#define FCOMMAND_FCMD_SEQIN	0x80		/* page program 1st command */
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#define FCOMMAND_FCMD_PAGEPROG	0x10		/* page program 2nd command */
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#define FCOMMAND_FCMD_RESET	0xff		/* reset command */
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#define FCOMMAND_FCMD_ERASE1	0x60		/* erase 1st command */
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#define FCOMMAND_FCMD_ERASE2	0xd0		/* erase 2nd command */
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#define FCOMMAND_FCMD_STATUS	0x70		/* read status command */
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#define FCOMMAND_FCMD_READID	0x90		/* read id command */
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#define FCOMMAND_FCMD_READOOB	0x50		/* read3 command */
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/* address register */
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#define FADD			__SYSREG(0xd8f00004, u32)
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/* address register 2 */
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#define FADD2			__SYSREG(0xd8f00008, u32)
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/* error judgement register */
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#define FJUDGE			__SYSREG(0xd8f0000c, u32)
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#define FJUDGE_NOERR		0x0		/* no error */
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#define FJUDGE_1BITERR		0x1		/* 1bit error in data area */
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#define FJUDGE_PARITYERR	0x2		/* parity error */
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#define FJUDGE_UNCORRECTABLE	0x3		/* uncorrectable error */
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#define FJUDGE_ERRJDG_MSK	0x3		/* mask of judgement result */
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/* 1st ECC store register */
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#define FECC11			__SYSREG(0xd8f00010, u32)
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/* 2nd ECC store register */
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#define FECC12			__SYSREG(0xd8f00014, u32)
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/* 3rd ECC store register */
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#define FECC21			__SYSREG(0xd8f00018, u32)
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/* 4th ECC store register */
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#define FECC22			__SYSREG(0xd8f0001c, u32)
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/* 5th ECC store register */
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#define FECC31			__SYSREG(0xd8f00020, u32)
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/* 6th ECC store register */
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#define FECC32			__SYSREG(0xd8f00024, u32)
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/* 7th ECC store register */
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#define FECC41			__SYSREG(0xd8f00028, u32)
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/* 8th ECC store register */
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#define FECC42			__SYSREG(0xd8f0002c, u32)
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/* data register */
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#define FDATA			__SYSREG(0xd8f00030, u32)
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/* access pulse register */
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#define FPWS			__SYSREG(0xd8f00100, u32)
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#define FPWS_PWS1W_2CLK		0x00000000 /* write pulse width 1clock */
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#define FPWS_PWS1W_3CLK		0x01000000 /* write pulse width 2clock */
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#define FPWS_PWS1W_4CLK		0x02000000 /* write pulse width 4clock */
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#define FPWS_PWS1W_5CLK		0x03000000 /* write pulse width 5clock */
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#define FPWS_PWS1W_6CLK		0x04000000 /* write pulse width 6clock */
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#define FPWS_PWS1W_7CLK		0x05000000 /* write pulse width 7clock */
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#define FPWS_PWS1W_8CLK		0x06000000 /* write pulse width 8clock */
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#define FPWS_PWS1R_3CLK		0x00010000 /* read pulse width 3clock */
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#define FPWS_PWS1R_4CLK		0x00020000 /* read pulse width 4clock */
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#define FPWS_PWS1R_5CLK		0x00030000 /* read pulse width 5clock */
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#define FPWS_PWS1R_6CLK		0x00040000 /* read pulse width 6clock */
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#define FPWS_PWS1R_7CLK		0x00050000 /* read pulse width 7clock */
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#define FPWS_PWS1R_8CLK		0x00060000 /* read pulse width 8clock */
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#define FPWS_PWS2W_2CLK		0x00000100 /* write pulse interval 2clock */
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#define FPWS_PWS2W_3CLK		0x00000200 /* write pulse interval 3clock */
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#define FPWS_PWS2W_4CLK		0x00000300 /* write pulse interval 4clock */
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#define FPWS_PWS2W_5CLK		0x00000400 /* write pulse interval 5clock */
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#define FPWS_PWS2W_6CLK		0x00000500 /* write pulse interval 6clock */
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#define FPWS_PWS2R_2CLK		0x00000001 /* read pulse interval 2clock */
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#define FPWS_PWS2R_3CLK		0x00000002 /* read pulse interval 3clock */
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#define FPWS_PWS2R_4CLK		0x00000003 /* read pulse interval 4clock */
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#define FPWS_PWS2R_5CLK		0x00000004 /* read pulse interval 5clock */
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#define FPWS_PWS2R_6CLK		0x00000005 /* read pulse interval 6clock */
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/* command register 2 */
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#define FCOMMAND2		__SYSREG(0xd8f00110, u32)
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/* transfer frequency register */
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#define FNUM			__SYSREG(0xd8f00114, u32)
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#define FSDATA_ADDR		0xd8f00400
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/* active data register */
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#define FSDATA			__SYSREG(FSDATA_ADDR, u32)
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#endif /* _PROC_NAND_REGS_H_ */
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