Path: blob/master/arch/mn10300/unit-asb2364/include/unit/serial.h
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/* Unit-specific 8250 serial ports1*2* Copyright (C) 2005 Red Hat, Inc. All Rights Reserved.3* Written by David Howells ([email protected])4*5* This program is free software; you can redistribute it and/or6* modify it under the terms of the GNU General Public License7* as published by the Free Software Foundation; either version8* 2 of the License, or (at your option) any later version.9*/1011#ifndef _ASM_UNIT_SERIAL_H12#define _ASM_UNIT_SERIAL_H1314#include <asm/cpu-regs.h>15#include <proc/irq.h>16#include <unit/fpga-regs.h>17#include <linux/serial_reg.h>1819#define SERIAL_PORT0_BASE_ADDRESS 0xA82000002021#define SERIAL_IRQ XIRQ1 /* single serial (TL16C550C) (Lo) */2223/*24* The ASB2364 has an 12.288 MHz clock25* for your UART.26*27* It'd be nice if someone built a serial card with a 24.576 MHz28* clock, since the 16550A is capable of handling a top speed of 1.529* megabits/second; but this requires the faster clock.30*/31#define BASE_BAUD (12288000 / 16)3233/*34* dispose of the /dev/ttyS0 and /dev/ttyS1 serial ports35*/36#ifndef CONFIG_GDBSTUB_ON_TTYSx3738#define SERIAL_PORT_DFNS \39{ \40.baud_base = BASE_BAUD, \41.irq = SERIAL_IRQ, \42.flags = STD_COM_FLAGS, \43.iomem_base = (u8 *) SERIAL_PORT0_BASE_ADDRESS, \44.iomem_reg_shift = 1, \45.io_type = SERIAL_IO_MEM, \46},4748#ifndef __ASSEMBLY__4950static inline void __debug_to_serial(const char *p, int n)51{52}5354#endif /* !__ASSEMBLY__ */5556#else /* CONFIG_GDBSTUB_ON_TTYSx */5758#define SERIAL_PORT_DFNS /* stolen by gdb-stub */5960#if defined(CONFIG_GDBSTUB_ON_TTYS0)61#define GDBPORT_SERIAL_RX __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_RX * 2, u8)62#define GDBPORT_SERIAL_TX __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_TX * 2, u8)63#define GDBPORT_SERIAL_DLL __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_DLL * 2, u8)64#define GDBPORT_SERIAL_DLM __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_DLM * 2, u8)65#define GDBPORT_SERIAL_IER __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_IER * 2, u8)66#define GDBPORT_SERIAL_IIR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_IIR * 2, u8)67#define GDBPORT_SERIAL_FCR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_FCR * 2, u8)68#define GDBPORT_SERIAL_LCR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_LCR * 2, u8)69#define GDBPORT_SERIAL_MCR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_MCR * 2, u8)70#define GDBPORT_SERIAL_LSR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_LSR * 2, u8)71#define GDBPORT_SERIAL_MSR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_MSR * 2, u8)72#define GDBPORT_SERIAL_SCR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_SCR * 2, u8)73#define GDBPORT_SERIAL_IRQ SERIAL_IRQ7475#elif defined(CONFIG_GDBSTUB_ON_TTYS1)76#error The ASB2364 does not have a /dev/ttyS177#endif7879#ifndef __ASSEMBLY__8081static inline void __debug_to_serial(const char *p, int n)82{83char ch;8485#define LSR_WAIT_FOR(STATE) \86do {} while (!(GDBPORT_SERIAL_LSR & UART_LSR_##STATE))87#define FLOWCTL_QUERY(LINE) \88({ GDBPORT_SERIAL_MSR & UART_MSR_##LINE; })89#define FLOWCTL_WAIT_FOR(LINE) \90do {} while (!(GDBPORT_SERIAL_MSR & UART_MSR_##LINE))91#define FLOWCTL_CLEAR(LINE) \92do { GDBPORT_SERIAL_MCR &= ~UART_MCR_##LINE; } while (0)93#define FLOWCTL_SET(LINE) \94do { GDBPORT_SERIAL_MCR |= UART_MCR_##LINE; } while (0)9596FLOWCTL_SET(DTR);9798for (; n > 0; n--) {99LSR_WAIT_FOR(THRE);100FLOWCTL_WAIT_FOR(CTS);101102ch = *p++;103if (ch == 0x0a) {104GDBPORT_SERIAL_TX = 0x0d;105LSR_WAIT_FOR(THRE);106FLOWCTL_WAIT_FOR(CTS);107}108GDBPORT_SERIAL_TX = ch;109}110111FLOWCTL_CLEAR(DTR);112}113114#endif /* !__ASSEMBLY__ */115116#endif /* CONFIG_GDBSTUB_ON_TTYSx */117118#define SERIAL_INITIALIZE \119do { \120/* release reset */ \121ASB2364_FPGA_REG_RESET_UART = 0x0001; \122SyncExBus(); \123} while (0)124125#define SERIAL_CHECK_INTERRUPT \126do { \127if ((ASB2364_FPGA_REG_IRQ_UART & 0x0001) == 0x0001) { \128return IRQ_NONE; \129} \130} while (0)131132#define SERIAL_CLEAR_INTERRUPT \133do { \134ASB2364_FPGA_REG_IRQ_UART = 0x0001; \135SyncExBus(); \136} while (0)137138#define SERIAL_SET_INT_MASK \139do { \140ASB2364_FPGA_REG_MASK_UART = 0x0001; \141SyncExBus(); \142} while (0)143144#define SERIAL_CLEAR_INT_MASK \145do { \146ASB2364_FPGA_REG_MASK_UART = 0x0000; \147SyncExBus(); \148} while (0)149150#endif /* _ASM_UNIT_SERIAL_H */151152153