Path: blob/master/arch/powerpc/include/asm/cell-pmu.h
15117 views
/*1* Cell Broadband Engine Performance Monitor2*3* (C) Copyright IBM Corporation 20064*5* Author:6* David Erb ([email protected])7* Kevin Corry ([email protected])8*9* This program is free software; you can redistribute it and/or modify10* it under the terms of the GNU General Public License as published by11* the Free Software Foundation; either version 2, or (at your option)12* any later version.13*14* This program is distributed in the hope that it will be useful,15* but WITHOUT ANY WARRANTY; without even the implied warranty of16* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the17* GNU General Public License for more details.18*19* You should have received a copy of the GNU General Public License20* along with this program; if not, write to the Free Software21* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.22*/2324#ifndef __ASM_CELL_PMU_H__25#define __ASM_CELL_PMU_H__2627/* The Cell PMU has four hardware performance counters, which can be28* configured as four 32-bit counters or eight 16-bit counters.29*/30#define NR_PHYS_CTRS 431#define NR_CTRS (NR_PHYS_CTRS * 2)3233/* Macros for the pm_control register. */34#define CBE_PM_16BIT_CTR(ctr) (1 << (24 - ((ctr) & (NR_PHYS_CTRS - 1))))35#define CBE_PM_ENABLE_PERF_MON 0x8000000036#define CBE_PM_STOP_AT_MAX 0x4000000037#define CBE_PM_TRACE_MODE_GET(pm_control) (((pm_control) >> 28) & 0x3)38#define CBE_PM_TRACE_MODE_SET(mode) (((mode) & 0x3) << 28)39#define CBE_PM_TRACE_BUF_OVFLW(bit) (((bit) & 0x1) << 17)40#define CBE_PM_COUNT_MODE_SET(count) (((count) & 0x3) << 18)41#define CBE_PM_FREEZE_ALL_CTRS 0x0010000042#define CBE_PM_ENABLE_EXT_TRACE 0x0000800043#define CBE_PM_SPU_ADDR_TRACE_SET(msk) (((msk) & 0x3) << 9)4445/* Macros for the trace_address register. */46#define CBE_PM_TRACE_BUF_FULL 0x0000080047#define CBE_PM_TRACE_BUF_EMPTY 0x0000040048#define CBE_PM_TRACE_BUF_DATA_COUNT(ta) ((ta) & 0x3ff)49#define CBE_PM_TRACE_BUF_MAX_COUNT 0x4005051/* Macros for the pm07_control registers. */52#define CBE_PM_CTR_INPUT_MUX(pm07_control) (((pm07_control) >> 26) & 0x3f)53#define CBE_PM_CTR_INPUT_CONTROL 0x0200000054#define CBE_PM_CTR_POLARITY 0x0100000055#define CBE_PM_CTR_COUNT_CYCLES 0x0080000056#define CBE_PM_CTR_ENABLE 0x0040000057#define PM07_CTR_INPUT_MUX(x) (((x) & 0x3F) << 26)58#define PM07_CTR_INPUT_CONTROL(x) (((x) & 1) << 25)59#define PM07_CTR_POLARITY(x) (((x) & 1) << 24)60#define PM07_CTR_COUNT_CYCLES(x) (((x) & 1) << 23)61#define PM07_CTR_ENABLE(x) (((x) & 1) << 22)6263/* Macros for the pm_status register. */64#define CBE_PM_CTR_OVERFLOW_INTR(ctr) (1 << (31 - ((ctr) & 7)))6566enum pm_reg_name {67group_control,68debug_bus_control,69trace_address,70ext_tr_timer,71pm_status,72pm_control,73pm_interval,74pm_start_stop,75};7677/* Routines for reading/writing the PMU registers. */78extern u32 cbe_read_phys_ctr(u32 cpu, u32 phys_ctr);79extern void cbe_write_phys_ctr(u32 cpu, u32 phys_ctr, u32 val);80extern u32 cbe_read_ctr(u32 cpu, u32 ctr);81extern void cbe_write_ctr(u32 cpu, u32 ctr, u32 val);8283extern u32 cbe_read_pm07_control(u32 cpu, u32 ctr);84extern void cbe_write_pm07_control(u32 cpu, u32 ctr, u32 val);85extern u32 cbe_read_pm(u32 cpu, enum pm_reg_name reg);86extern void cbe_write_pm(u32 cpu, enum pm_reg_name reg, u32 val);8788extern u32 cbe_get_ctr_size(u32 cpu, u32 phys_ctr);89extern void cbe_set_ctr_size(u32 cpu, u32 phys_ctr, u32 ctr_size);9091extern void cbe_enable_pm(u32 cpu);92extern void cbe_disable_pm(u32 cpu);9394extern void cbe_read_trace_buffer(u32 cpu, u64 *buf);9596extern void cbe_enable_pm_interrupts(u32 cpu, u32 thread, u32 mask);97extern void cbe_disable_pm_interrupts(u32 cpu);98extern u32 cbe_get_and_clear_pm_interrupts(u32 cpu);99extern void cbe_sync_irq(int node);100101#define CBE_COUNT_SUPERVISOR_MODE 0102#define CBE_COUNT_HYPERVISOR_MODE 1103#define CBE_COUNT_PROBLEM_MODE 2104#define CBE_COUNT_ALL_MODES 3105106#endif /* __ASM_CELL_PMU_H__ */107108109