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awilliam
GitHub Repository: awilliam/linux-vfio
 Path: blob/master/arch/powerpc/kernel/cpu_setup_44x.S
10817 views
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/*

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 * This file contains low level CPU setup functions.

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 * Valentine Barshak <[email protected]>

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 * MontaVista Software, Inc (c) 2007

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 *

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 * Based on cpu_setup_6xx code by

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 * Benjamin Herrenschmidt <[email protected]>

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 *

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 * This program is free software; you can redistribute it and/or

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 * modify it under the terms of the GNU General Public License

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 * as published by the Free Software Foundation; either version

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 * 2 of the License, or (at your option) any later version.

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 *

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 */

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#include <asm/processor.h>

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#include <asm/cputable.h>

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#include <asm/ppc_asm.h>

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_GLOBAL(__setup_cpu_440ep)

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	b	__init_fpu_44x

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_GLOBAL(__setup_cpu_440epx)

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	mflr	r4

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	bl	__init_fpu_44x

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	bl	__plb_disable_wrp

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	bl	__fixup_440A_mcheck

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	mtlr	r4

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	blr

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_GLOBAL(__setup_cpu_440grx)

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	mflr	r4

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	bl	__plb_disable_wrp

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	bl	__fixup_440A_mcheck

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	mtlr	r4

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	blr

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_GLOBAL(__setup_cpu_460ex)

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_GLOBAL(__setup_cpu_460gt)

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_GLOBAL(__setup_cpu_460sx)

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_GLOBAL(__setup_cpu_apm821xx)

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	mflr	r4

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	bl	__init_fpu_44x

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	bl	__fixup_440A_mcheck

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	mtlr	r4

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	blr

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_GLOBAL(__setup_cpu_440x5)

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_GLOBAL(__setup_cpu_440gx)

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_GLOBAL(__setup_cpu_440spe)

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	b	__fixup_440A_mcheck

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/* enable APU between CPU and FPU */

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_GLOBAL(__init_fpu_44x)

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	mfspr	r3,SPRN_CCR0

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	/* Clear DAPUIB flag in CCR0 */

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	rlwinm	r3,r3,0,12,10

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	mtspr	SPRN_CCR0,r3

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	isync

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	blr

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/*

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 * Workaround for the incorrect write to DDR SDRAM errata.

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 * The write address can be corrupted during writes to

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 * DDR SDRAM when write pipelining is enabled on PLB0.

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 * Disable write pipelining here.

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 */

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#define DCRN_PLB4A0_ACR	0x81

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_GLOBAL(__plb_disable_wrp)

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	mfdcr	r3,DCRN_PLB4A0_ACR

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	/* clear WRP bit in PLB4A0_ACR */

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	rlwinm	r3,r3,0,8,6

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	mtdcr	DCRN_PLB4A0_ACR,r3

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	isync

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	blr

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