CoCalc -- ldstfp.S

GitHub Repository: awilliam/linux-vfio
Path: blob/master/arch/powerpc/lib/ldstfp.S
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/*
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 * Floating-point, VMX/Altivec and VSX loads and stores
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 * for use in instruction emulation.
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 *
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 * Copyright 2010 Paul Mackerras, IBM Corp. <[email protected]>
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 *
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 *  This program is free software; you can redistribute it and/or
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 *  modify it under the terms of the GNU General Public License
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 *  as published by the Free Software Foundation; either version
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 *  2 of the License, or (at your option) any later version.
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 */
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#include <asm/processor.h>
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#include <asm/ppc_asm.h>
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#include <asm/ppc-opcode.h>
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#include <asm/reg.h>
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#include <asm/asm-offsets.h>
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#include <linux/errno.h>
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#ifdef CONFIG_PPC_FPU
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#define STKFRM	(PPC_MIN_STKFRM + 16)
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	.macro	extab	instr,handler
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	.section __ex_table,"a"
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	PPC_LONG \instr,\handler
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	.previous
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	.endm
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	.macro	inst32	op
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reg = 0
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	.rept	32
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20:	\op	reg,0,r4
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	b	3f
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	extab	20b,99f
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reg = reg + 1
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	.endr
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	.endm
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/* Get the contents of frN into fr0; N is in r3. */
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_GLOBAL(get_fpr)
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	mflr	r0
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	rlwinm	r3,r3,3,0xf8
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	bcl	20,31,1f
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	blr			/* fr0 is already in fr0 */
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	nop
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reg = 1
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	.rept	31
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	fmr	fr0,reg
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	blr
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reg = reg + 1
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	.endr
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1:	mflr	r5
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	add	r5,r3,r5
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	mtctr	r5
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	mtlr	r0
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	bctr
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/* Put the contents of fr0 into frN; N is in r3. */
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_GLOBAL(put_fpr)
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	mflr	r0
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	rlwinm	r3,r3,3,0xf8
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	bcl	20,31,1f
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	blr			/* fr0 is already in fr0 */
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	nop
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reg = 1
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	.rept	31
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	fmr	reg,fr0
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	blr
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reg = reg + 1
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	.endr
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1:	mflr	r5
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	add	r5,r3,r5
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	mtctr	r5
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	mtlr	r0
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	bctr
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/* Load FP reg N from float at *p.  N is in r3, p in r4. */
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_GLOBAL(do_lfs)
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	PPC_STLU r1,-STKFRM(r1)
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	mflr	r0
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	PPC_STL	r0,STKFRM+PPC_LR_STKOFF(r1)
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	mfmsr	r6
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	ori	r7,r6,MSR_FP
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	cmpwi	cr7,r3,0
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	MTMSRD(r7)
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	isync
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	beq	cr7,1f
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	stfd	fr0,STKFRM-16(r1)
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1:	li	r9,-EFAULT
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2:	lfs	fr0,0(r4)
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	li	r9,0
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3:	bl	put_fpr
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	beq	cr7,4f
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	lfd	fr0,STKFRM-16(r1)
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4:	PPC_LL	r0,STKFRM+PPC_LR_STKOFF(r1)
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	mtlr	r0
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	MTMSRD(r6)
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	isync
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	mr	r3,r9
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	addi	r1,r1,STKFRM
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	blr
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	extab	2b,3b
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/* Load FP reg N from double at *p.  N is in r3, p in r4. */
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_GLOBAL(do_lfd)
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	PPC_STLU r1,-STKFRM(r1)
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	mflr	r0
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	PPC_STL	r0,STKFRM+PPC_LR_STKOFF(r1)
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	mfmsr	r6
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	ori	r7,r6,MSR_FP
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	cmpwi	cr7,r3,0
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	MTMSRD(r7)
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	isync
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	beq	cr7,1f
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	stfd	fr0,STKFRM-16(r1)
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1:	li	r9,-EFAULT
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2:	lfd	fr0,0(r4)
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	li	r9,0
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3:	beq	cr7,4f
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	bl	put_fpr
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	lfd	fr0,STKFRM-16(r1)
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4:	PPC_LL	r0,STKFRM+PPC_LR_STKOFF(r1)
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	mtlr	r0
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	MTMSRD(r6)
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	isync
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	mr	r3,r9
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	addi	r1,r1,STKFRM
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	blr
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	extab	2b,3b
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/* Store FP reg N to float at *p.  N is in r3, p in r4. */
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_GLOBAL(do_stfs)
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	PPC_STLU r1,-STKFRM(r1)
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	mflr	r0
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	PPC_STL	r0,STKFRM+PPC_LR_STKOFF(r1)
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	mfmsr	r6
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	ori	r7,r6,MSR_FP
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	cmpwi	cr7,r3,0
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	MTMSRD(r7)
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	isync
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	beq	cr7,1f
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	stfd	fr0,STKFRM-16(r1)
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	bl	get_fpr
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1:	li	r9,-EFAULT
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2:	stfs	fr0,0(r4)
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	li	r9,0
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3:	beq	cr7,4f
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	lfd	fr0,STKFRM-16(r1)
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4:	PPC_LL	r0,STKFRM+PPC_LR_STKOFF(r1)
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	mtlr	r0
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	MTMSRD(r6)
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	isync
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	mr	r3,r9
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	addi	r1,r1,STKFRM
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	blr
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	extab	2b,3b
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/* Store FP reg N to double at *p.  N is in r3, p in r4. */
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_GLOBAL(do_stfd)
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	PPC_STLU r1,-STKFRM(r1)
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	mflr	r0
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	PPC_STL	r0,STKFRM+PPC_LR_STKOFF(r1)
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	mfmsr	r6
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	ori	r7,r6,MSR_FP
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	cmpwi	cr7,r3,0
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	MTMSRD(r7)
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	isync
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	beq	cr7,1f
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	stfd	fr0,STKFRM-16(r1)
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	bl	get_fpr
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1:	li	r9,-EFAULT
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2:	stfd	fr0,0(r4)
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	li	r9,0
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3:	beq	cr7,4f
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	lfd	fr0,STKFRM-16(r1)
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4:	PPC_LL	r0,STKFRM+PPC_LR_STKOFF(r1)
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	mtlr	r0
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	MTMSRD(r6)
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	isync
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	mr	r3,r9
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	addi	r1,r1,STKFRM
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	blr
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	extab	2b,3b
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#ifdef CONFIG_ALTIVEC
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/* Get the contents of vrN into vr0; N is in r3. */
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_GLOBAL(get_vr)
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	mflr	r0
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	rlwinm	r3,r3,3,0xf8
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	bcl	20,31,1f
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	blr			/* vr0 is already in vr0 */
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	nop
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reg = 1
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	.rept	31
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	vor	vr0,reg,reg	/* assembler doesn't know vmr? */
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	blr
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reg = reg + 1
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	.endr
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1:	mflr	r5
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	add	r5,r3,r5
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	mtctr	r5
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	mtlr	r0
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	bctr
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/* Put the contents of vr0 into vrN; N is in r3. */
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_GLOBAL(put_vr)
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	mflr	r0
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	rlwinm	r3,r3,3,0xf8
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	bcl	20,31,1f
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	blr			/* vr0 is already in vr0 */
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	nop
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reg = 1
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	.rept	31
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	vor	reg,vr0,vr0
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	blr
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reg = reg + 1
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	.endr
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1:	mflr	r5
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	add	r5,r3,r5
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	mtctr	r5
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	mtlr	r0
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	bctr
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/* Load vector reg N from *p.  N is in r3, p in r4. */
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_GLOBAL(do_lvx)
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	PPC_STLU r1,-STKFRM(r1)
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	mflr	r0
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	PPC_STL	r0,STKFRM+PPC_LR_STKOFF(r1)
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	mfmsr	r6
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	oris	r7,r6,MSR_VEC@h
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	cmpwi	cr7,r3,0
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	li	r8,STKFRM-16
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	MTMSRD(r7)
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	isync
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	beq	cr7,1f
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	stvx	vr0,r1,r8
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1:	li	r9,-EFAULT
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2:	lvx	vr0,0,r4
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	li	r9,0
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3:	beq	cr7,4f
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	bl	put_vr
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	lvx	vr0,r1,r8
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4:	PPC_LL	r0,STKFRM+PPC_LR_STKOFF(r1)
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	mtlr	r0
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	MTMSRD(r6)
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	isync
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	mr	r3,r9
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	addi	r1,r1,STKFRM
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	blr
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	extab	2b,3b
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/* Store vector reg N to *p.  N is in r3, p in r4. */
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_GLOBAL(do_stvx)
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	PPC_STLU r1,-STKFRM(r1)
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	mflr	r0
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	PPC_STL	r0,STKFRM+PPC_LR_STKOFF(r1)
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	mfmsr	r6
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	oris	r7,r6,MSR_VEC@h
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	cmpwi	cr7,r3,0
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	li	r8,STKFRM-16
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	MTMSRD(r7)
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	isync
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	beq	cr7,1f
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	stvx	vr0,r1,r8
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	bl	get_vr
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1:	li	r9,-EFAULT
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2:	stvx	vr0,0,r4
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	li	r9,0
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3:	beq	cr7,4f
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	lvx	vr0,r1,r8
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4:	PPC_LL	r0,STKFRM+PPC_LR_STKOFF(r1)
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	mtlr	r0
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	MTMSRD(r6)
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	isync
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	mr	r3,r9
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	addi	r1,r1,STKFRM
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	blr
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	extab	2b,3b
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#endif /* CONFIG_ALTIVEC */
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#ifdef CONFIG_VSX
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/* Get the contents of vsrN into vsr0; N is in r3. */
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_GLOBAL(get_vsr)
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	mflr	r0
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	rlwinm	r3,r3,3,0x1f8
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	bcl	20,31,1f
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	blr			/* vsr0 is already in vsr0 */
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	nop
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reg = 1
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	.rept	63
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	XXLOR(0,reg,reg)
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	blr
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reg = reg + 1
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	.endr
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1:	mflr	r5
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	add	r5,r3,r5
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	mtctr	r5
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	mtlr	r0
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	bctr
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/* Put the contents of vsr0 into vsrN; N is in r3. */
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_GLOBAL(put_vsr)
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	mflr	r0
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	rlwinm	r3,r3,3,0x1f8
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	bcl	20,31,1f
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	blr			/* vr0 is already in vr0 */
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	nop
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reg = 1
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	.rept	63
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	XXLOR(reg,0,0)
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	blr
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reg = reg + 1
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	.endr
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1:	mflr	r5
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	add	r5,r3,r5
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	mtctr	r5
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	mtlr	r0
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	bctr
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/* Load VSX reg N from vector doubleword *p.  N is in r3, p in r4. */
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_GLOBAL(do_lxvd2x)
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	PPC_STLU r1,-STKFRM(r1)
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	mflr	r0
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	PPC_STL	r0,STKFRM+PPC_LR_STKOFF(r1)
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	mfmsr	r6
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	oris	r7,r6,MSR_VSX@h
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	cmpwi	cr7,r3,0
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	li	r8,STKFRM-16
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	MTMSRD(r7)
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	isync
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	beq	cr7,1f
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	STXVD2X(0,r1,r8)
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1:	li	r9,-EFAULT
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2:	LXVD2X(0,0,r4)
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	li	r9,0
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3:	beq	cr7,4f
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	bl	put_vsr
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	LXVD2X(0,r1,r8)
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4:	PPC_LL	r0,STKFRM+PPC_LR_STKOFF(r1)
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	mtlr	r0
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	MTMSRD(r6)
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	isync
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	mr	r3,r9
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	addi	r1,r1,STKFRM
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	blr
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	extab	2b,3b
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/* Store VSX reg N to vector doubleword *p.  N is in r3, p in r4. */
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_GLOBAL(do_stxvd2x)
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	PPC_STLU r1,-STKFRM(r1)
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	mflr	r0
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	PPC_STL	r0,STKFRM+PPC_LR_STKOFF(r1)
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	mfmsr	r6
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	oris	r7,r6,MSR_VSX@h
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	cmpwi	cr7,r3,0
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	li	r8,STKFRM-16
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	MTMSRD(r7)
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	isync
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	beq	cr7,1f
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	STXVD2X(0,r1,r8)
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	bl	get_vsr
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1:	li	r9,-EFAULT
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2:	STXVD2X(0,0,r4)
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	li	r9,0
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3:	beq	cr7,4f
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	LXVD2X(0,r1,r8)
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4:	PPC_LL	r0,STKFRM+PPC_LR_STKOFF(r1)
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	mtlr	r0
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	MTMSRD(r6)
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	isync
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	mr	r3,r9
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	addi	r1,r1,STKFRM
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	blr
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	extab	2b,3b
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#endif /* CONFIG_VSX */
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#endif	/* CONFIG_PPC_FPU */
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