Path: blob/master/arch/powerpc/platforms/40x/ep405.c
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/*1* Architecture- / platform-specific boot-time initialization code for2* IBM PowerPC 4xx based boards. Adapted from original3* code by Gary Thomas, Cort Dougan <[email protected]>, and Dan Malek4* <[email protected]>.5*6* Copyright(c) 1999-2000 Grant Erickson <[email protected]>7*8* Rewritten and ported to the merged powerpc tree:9* Copyright 2007 IBM Corporation10* Josh Boyer <[email protected]>11*12* Adapted to EP405 by Ben. Herrenschmidt <[email protected]>13*14* TODO: Wire up the PCI IRQ mux and the southbridge interrupts15*16* 2002 (c) MontaVista, Software, Inc. This file is licensed under17* the terms of the GNU General Public License version 2. This program18* is licensed "as is" without any warranty of any kind, whether express19* or implied.20*/2122#include <linux/init.h>23#include <linux/of_platform.h>2425#include <asm/machdep.h>26#include <asm/prom.h>27#include <asm/udbg.h>28#include <asm/time.h>29#include <asm/uic.h>30#include <asm/pci-bridge.h>31#include <asm/ppc4xx.h>3233static struct device_node *bcsr_node;34static void __iomem *bcsr_regs;3536/* BCSR registers */37#define BCSR_ID 038#define BCSR_PCI_CTRL 139#define BCSR_FLASH_NV_POR_CTRL 240#define BCSR_FENET_UART_CTRL 341#define BCSR_PCI_IRQ 442#define BCSR_XIRQ_SELECT 543#define BCSR_XIRQ_ROUTING 644#define BCSR_XIRQ_STATUS 745#define BCSR_XIRQ_STATUS2 846#define BCSR_SW_STAT_LED_CTRL 947#define BCSR_GPIO_IRQ_PAR_CTRL 1048/* there's more, can't be bothered typing them tho */495051static __initdata struct of_device_id ep405_of_bus[] = {52{ .compatible = "ibm,plb3", },53{ .compatible = "ibm,opb", },54{ .compatible = "ibm,ebc", },55{},56};5758static int __init ep405_device_probe(void)59{60of_platform_bus_probe(NULL, ep405_of_bus, NULL);6162return 0;63}64machine_device_initcall(ep405, ep405_device_probe);6566static void __init ep405_init_bcsr(void)67{68const u8 *irq_routing;69int i;7071/* Find the bloody thing & map it */72bcsr_node = of_find_compatible_node(NULL, NULL, "ep405-bcsr");73if (bcsr_node == NULL) {74printk(KERN_ERR "EP405 BCSR not found !\n");75return;76}77bcsr_regs = of_iomap(bcsr_node, 0);78if (bcsr_regs == NULL) {79printk(KERN_ERR "EP405 BCSR failed to map !\n");80return;81}8283/* Get the irq-routing property and apply the routing to the CPLD */84irq_routing = of_get_property(bcsr_node, "irq-routing", NULL);85if (irq_routing == NULL)86return;87for (i = 0; i < 16; i++) {88u8 irq = irq_routing[i];89out_8(bcsr_regs + BCSR_XIRQ_SELECT, i);90out_8(bcsr_regs + BCSR_XIRQ_ROUTING, irq);91}92in_8(bcsr_regs + BCSR_XIRQ_SELECT);93mb();94out_8(bcsr_regs + BCSR_GPIO_IRQ_PAR_CTRL, 0xfe);95}9697static void __init ep405_setup_arch(void)98{99/* Find & init the BCSR CPLD */100ep405_init_bcsr();101102ppc_pci_set_flags(PPC_PCI_REASSIGN_ALL_RSRC);103}104105static int __init ep405_probe(void)106{107unsigned long root = of_get_flat_dt_root();108109if (!of_flat_dt_is_compatible(root, "ep405"))110return 0;111112return 1;113}114115define_machine(ep405) {116.name = "EP405",117.probe = ep405_probe,118.setup_arch = ep405_setup_arch,119.progress = udbg_progress,120.init_IRQ = uic_init_tree,121.get_irq = uic_get_irq,122.restart = ppc4xx_reset_system,123.calibrate_decr = generic_calibrate_decr,124};125126127