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awilliam
GitHub Repository: awilliam/linux-vfio
 Path: blob/master/arch/powerpc/platforms/cell/interrupt.h
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#ifndef ASM_CELL_PIC_H

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#define ASM_CELL_PIC_H

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#ifdef __KERNEL__

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/*

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 * Mapping of IIC pending bits into per-node interrupt numbers.

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 *

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 * Interrupt numbers are in the range 0...0x1ff where the top bit

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 * (0x100) represent the source node. Only 2 nodes are supported with

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 * the current code though it's trivial to extend that if necessary using

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 * higher level bits

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 *

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 * The bottom 8 bits are split into 2 type bits and 6 data bits that

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 * depend on the type:

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 *

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 * 00 (0x00 | data) : normal interrupt. data is (class << 4) | source

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 * 01 (0x40 | data) : IO exception. data is the exception number as

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 *                    defined by bit numbers in IIC_SR

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 * 10 (0x80 | data) : IPI. data is the IPI number (obtained from the priority)

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 *                    and node is always 0 (IPIs are per-cpu, their source is

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 *                    not relevant)

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 * 11 (0xc0 | data) : reserved

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 *

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 * In addition, interrupt number 0x80000000 is defined as always invalid

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 * (that is the node field is expected to never extend to move than 23 bits)

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 *

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 */

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enum {

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	IIC_IRQ_INVALID		= 0x80000000u,

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	IIC_IRQ_NODE_MASK	= 0x100,

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	IIC_IRQ_NODE_SHIFT	= 8,

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	IIC_IRQ_MAX		= 0x1ff,

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	IIC_IRQ_TYPE_MASK	= 0xc0,

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	IIC_IRQ_TYPE_NORMAL	= 0x00,

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	IIC_IRQ_TYPE_IOEXC	= 0x40,

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	IIC_IRQ_TYPE_IPI	= 0x80,

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	IIC_IRQ_CLASS_SHIFT	= 4,

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	IIC_IRQ_CLASS_0		= 0x00,

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	IIC_IRQ_CLASS_1		= 0x10,

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	IIC_IRQ_CLASS_2		= 0x20,

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	IIC_SOURCE_COUNT	= 0x200,

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	/* Here are defined the various source/dest units. Avoid using those

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	 * definitions if you can, they are mostly here for reference

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	 */

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	IIC_UNIT_SPU_0		= 0x4,

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	IIC_UNIT_SPU_1		= 0x7,

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	IIC_UNIT_SPU_2		= 0x3,

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	IIC_UNIT_SPU_3		= 0x8,

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	IIC_UNIT_SPU_4		= 0x2,

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	IIC_UNIT_SPU_5		= 0x9,

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	IIC_UNIT_SPU_6		= 0x1,

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	IIC_UNIT_SPU_7		= 0xa,

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	IIC_UNIT_IOC_0		= 0x0,

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	IIC_UNIT_IOC_1		= 0xb,

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	IIC_UNIT_THREAD_0	= 0xe, /* target only */

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	IIC_UNIT_THREAD_1	= 0xf, /* target only */

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	IIC_UNIT_IIC		= 0xe, /* source only (IO exceptions) */

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	/* Base numbers for the external interrupts */

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	IIC_IRQ_EXT_IOIF0	=

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		IIC_IRQ_TYPE_NORMAL | IIC_IRQ_CLASS_2 | IIC_UNIT_IOC_0,

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	IIC_IRQ_EXT_IOIF1	=

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		IIC_IRQ_TYPE_NORMAL | IIC_IRQ_CLASS_2 | IIC_UNIT_IOC_1,

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	/* Base numbers for the IIC_ISR interrupts */

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	IIC_IRQ_IOEX_TMI	= IIC_IRQ_TYPE_IOEXC | IIC_IRQ_CLASS_1 | 63,

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	IIC_IRQ_IOEX_PMI	= IIC_IRQ_TYPE_IOEXC | IIC_IRQ_CLASS_1 | 62,

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	IIC_IRQ_IOEX_ATI	= IIC_IRQ_TYPE_IOEXC | IIC_IRQ_CLASS_1 | 61,

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	IIC_IRQ_IOEX_MATBFI	= IIC_IRQ_TYPE_IOEXC | IIC_IRQ_CLASS_1 | 60,

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	IIC_IRQ_IOEX_ELDI	= IIC_IRQ_TYPE_IOEXC | IIC_IRQ_CLASS_1 | 59,

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	/* Which bits in IIC_ISR are edge sensitive */

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	IIC_ISR_EDGE_MASK	= 0x4ul,

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};

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extern void iic_init_IRQ(void);

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extern void iic_message_pass(int cpu, int msg);

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extern void iic_request_IPIs(void);

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extern void iic_setup_cpu(void);

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extern u8 iic_get_target_id(int cpu);

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extern void spider_init_IRQ(void);

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extern void iic_set_interrupt_routing(int cpu, int thread, int priority);

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#endif

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#endif /* ASM_CELL_PIC_H */

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