Path: blob/master/arch/powerpc/platforms/cell/spu_base.c
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/*1* Low-level SPU handling2*3* (C) Copyright IBM Deutschland Entwicklung GmbH 20054*5* Author: Arnd Bergmann <[email protected]>6*7* This program is free software; you can redistribute it and/or modify8* it under the terms of the GNU General Public License as published by9* the Free Software Foundation; either version 2, or (at your option)10* any later version.11*12* This program is distributed in the hope that it will be useful,13* but WITHOUT ANY WARRANTY; without even the implied warranty of14* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the15* GNU General Public License for more details.16*17* You should have received a copy of the GNU General Public License18* along with this program; if not, write to the Free Software19* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.20*/2122#undef DEBUG2324#include <linux/interrupt.h>25#include <linux/list.h>26#include <linux/module.h>27#include <linux/ptrace.h>28#include <linux/slab.h>29#include <linux/wait.h>30#include <linux/mm.h>31#include <linux/io.h>32#include <linux/mutex.h>33#include <linux/linux_logo.h>34#include <linux/syscore_ops.h>35#include <asm/spu.h>36#include <asm/spu_priv1.h>37#include <asm/spu_csa.h>38#include <asm/xmon.h>39#include <asm/prom.h>40#include <asm/kexec.h>4142const struct spu_management_ops *spu_management_ops;43EXPORT_SYMBOL_GPL(spu_management_ops);4445const struct spu_priv1_ops *spu_priv1_ops;46EXPORT_SYMBOL_GPL(spu_priv1_ops);4748struct cbe_spu_info cbe_spu_info[MAX_NUMNODES];49EXPORT_SYMBOL_GPL(cbe_spu_info);5051/*52* The spufs fault-handling code needs to call force_sig_info to raise signals53* on DMA errors. Export it here to avoid general kernel-wide access to this54* function55*/56EXPORT_SYMBOL_GPL(force_sig_info);5758/*59* Protects cbe_spu_info and spu->number.60*/61static DEFINE_SPINLOCK(spu_lock);6263/*64* List of all spus in the system.65*66* This list is iterated by callers from irq context and callers that67* want to sleep. Thus modifications need to be done with both68* spu_full_list_lock and spu_full_list_mutex held, while iterating69* through it requires either of these locks.70*71* In addition spu_full_list_lock protects all assignmens to72* spu->mm.73*/74static LIST_HEAD(spu_full_list);75static DEFINE_SPINLOCK(spu_full_list_lock);76static DEFINE_MUTEX(spu_full_list_mutex);7778struct spu_slb {79u64 esid, vsid;80};8182void spu_invalidate_slbs(struct spu *spu)83{84struct spu_priv2 __iomem *priv2 = spu->priv2;85unsigned long flags;8687spin_lock_irqsave(&spu->register_lock, flags);88if (spu_mfc_sr1_get(spu) & MFC_STATE1_RELOCATE_MASK)89out_be64(&priv2->slb_invalidate_all_W, 0UL);90spin_unlock_irqrestore(&spu->register_lock, flags);91}92EXPORT_SYMBOL_GPL(spu_invalidate_slbs);9394/* This is called by the MM core when a segment size is changed, to95* request a flush of all the SPEs using a given mm96*/97void spu_flush_all_slbs(struct mm_struct *mm)98{99struct spu *spu;100unsigned long flags;101102spin_lock_irqsave(&spu_full_list_lock, flags);103list_for_each_entry(spu, &spu_full_list, full_list) {104if (spu->mm == mm)105spu_invalidate_slbs(spu);106}107spin_unlock_irqrestore(&spu_full_list_lock, flags);108}109110/* The hack below stinks... try to do something better one of111* these days... Does it even work properly with NR_CPUS == 1 ?112*/113static inline void mm_needs_global_tlbie(struct mm_struct *mm)114{115int nr = (NR_CPUS > 1) ? NR_CPUS : NR_CPUS + 1;116117/* Global TLBIE broadcast required with SPEs. */118bitmap_fill(cpumask_bits(mm_cpumask(mm)), nr);119}120121void spu_associate_mm(struct spu *spu, struct mm_struct *mm)122{123unsigned long flags;124125spin_lock_irqsave(&spu_full_list_lock, flags);126spu->mm = mm;127spin_unlock_irqrestore(&spu_full_list_lock, flags);128if (mm)129mm_needs_global_tlbie(mm);130}131EXPORT_SYMBOL_GPL(spu_associate_mm);132133int spu_64k_pages_available(void)134{135return mmu_psize_defs[MMU_PAGE_64K].shift != 0;136}137EXPORT_SYMBOL_GPL(spu_64k_pages_available);138139static void spu_restart_dma(struct spu *spu)140{141struct spu_priv2 __iomem *priv2 = spu->priv2;142143if (!test_bit(SPU_CONTEXT_SWITCH_PENDING, &spu->flags))144out_be64(&priv2->mfc_control_RW, MFC_CNTL_RESTART_DMA_COMMAND);145else {146set_bit(SPU_CONTEXT_FAULT_PENDING, &spu->flags);147mb();148}149}150151static inline void spu_load_slb(struct spu *spu, int slbe, struct spu_slb *slb)152{153struct spu_priv2 __iomem *priv2 = spu->priv2;154155pr_debug("%s: adding SLB[%d] 0x%016llx 0x%016llx\n",156__func__, slbe, slb->vsid, slb->esid);157158out_be64(&priv2->slb_index_W, slbe);159/* set invalid before writing vsid */160out_be64(&priv2->slb_esid_RW, 0);161/* now it's safe to write the vsid */162out_be64(&priv2->slb_vsid_RW, slb->vsid);163/* setting the new esid makes the entry valid again */164out_be64(&priv2->slb_esid_RW, slb->esid);165}166167static int __spu_trap_data_seg(struct spu *spu, unsigned long ea)168{169struct mm_struct *mm = spu->mm;170struct spu_slb slb;171int psize;172173pr_debug("%s\n", __func__);174175slb.esid = (ea & ESID_MASK) | SLB_ESID_V;176177switch(REGION_ID(ea)) {178case USER_REGION_ID:179#ifdef CONFIG_PPC_MM_SLICES180psize = get_slice_psize(mm, ea);181#else182psize = mm->context.user_psize;183#endif184slb.vsid = (get_vsid(mm->context.id, ea, MMU_SEGSIZE_256M)185<< SLB_VSID_SHIFT) | SLB_VSID_USER;186break;187case VMALLOC_REGION_ID:188if (ea < VMALLOC_END)189psize = mmu_vmalloc_psize;190else191psize = mmu_io_psize;192slb.vsid = (get_kernel_vsid(ea, MMU_SEGSIZE_256M)193<< SLB_VSID_SHIFT) | SLB_VSID_KERNEL;194break;195case KERNEL_REGION_ID:196psize = mmu_linear_psize;197slb.vsid = (get_kernel_vsid(ea, MMU_SEGSIZE_256M)198<< SLB_VSID_SHIFT) | SLB_VSID_KERNEL;199break;200default:201/* Future: support kernel segments so that drivers202* can use SPUs.203*/204pr_debug("invalid region access at %016lx\n", ea);205return 1;206}207slb.vsid |= mmu_psize_defs[psize].sllp;208209spu_load_slb(spu, spu->slb_replace, &slb);210211spu->slb_replace++;212if (spu->slb_replace >= 8)213spu->slb_replace = 0;214215spu_restart_dma(spu);216spu->stats.slb_flt++;217return 0;218}219220extern int hash_page(unsigned long ea, unsigned long access, unsigned long trap); //XXX221static int __spu_trap_data_map(struct spu *spu, unsigned long ea, u64 dsisr)222{223int ret;224225pr_debug("%s, %llx, %lx\n", __func__, dsisr, ea);226227/*228* Handle kernel space hash faults immediately. User hash229* faults need to be deferred to process context.230*/231if ((dsisr & MFC_DSISR_PTE_NOT_FOUND) &&232(REGION_ID(ea) != USER_REGION_ID)) {233234spin_unlock(&spu->register_lock);235ret = hash_page(ea, _PAGE_PRESENT, 0x300);236spin_lock(&spu->register_lock);237238if (!ret) {239spu_restart_dma(spu);240return 0;241}242}243244spu->class_1_dar = ea;245spu->class_1_dsisr = dsisr;246247spu->stop_callback(spu, 1);248249spu->class_1_dar = 0;250spu->class_1_dsisr = 0;251252return 0;253}254255static void __spu_kernel_slb(void *addr, struct spu_slb *slb)256{257unsigned long ea = (unsigned long)addr;258u64 llp;259260if (REGION_ID(ea) == KERNEL_REGION_ID)261llp = mmu_psize_defs[mmu_linear_psize].sllp;262else263llp = mmu_psize_defs[mmu_virtual_psize].sllp;264265slb->vsid = (get_kernel_vsid(ea, MMU_SEGSIZE_256M) << SLB_VSID_SHIFT) |266SLB_VSID_KERNEL | llp;267slb->esid = (ea & ESID_MASK) | SLB_ESID_V;268}269270/**271* Given an array of @nr_slbs SLB entries, @slbs, return non-zero if the272* address @new_addr is present.273*/274static inline int __slb_present(struct spu_slb *slbs, int nr_slbs,275void *new_addr)276{277unsigned long ea = (unsigned long)new_addr;278int i;279280for (i = 0; i < nr_slbs; i++)281if (!((slbs[i].esid ^ ea) & ESID_MASK))282return 1;283284return 0;285}286287/**288* Setup the SPU kernel SLBs, in preparation for a context save/restore. We289* need to map both the context save area, and the save/restore code.290*291* Because the lscsa and code may cross segment boundaires, we check to see292* if mappings are required for the start and end of each range. We currently293* assume that the mappings are smaller that one segment - if not, something294* is seriously wrong.295*/296void spu_setup_kernel_slbs(struct spu *spu, struct spu_lscsa *lscsa,297void *code, int code_size)298{299struct spu_slb slbs[4];300int i, nr_slbs = 0;301/* start and end addresses of both mappings */302void *addrs[] = {303lscsa, (void *)lscsa + sizeof(*lscsa) - 1,304code, code + code_size - 1305};306307/* check the set of addresses, and create a new entry in the slbs array308* if there isn't already a SLB for that address */309for (i = 0; i < ARRAY_SIZE(addrs); i++) {310if (__slb_present(slbs, nr_slbs, addrs[i]))311continue;312313__spu_kernel_slb(addrs[i], &slbs[nr_slbs]);314nr_slbs++;315}316317spin_lock_irq(&spu->register_lock);318/* Add the set of SLBs */319for (i = 0; i < nr_slbs; i++)320spu_load_slb(spu, i, &slbs[i]);321spin_unlock_irq(&spu->register_lock);322}323EXPORT_SYMBOL_GPL(spu_setup_kernel_slbs);324325static irqreturn_t326spu_irq_class_0(int irq, void *data)327{328struct spu *spu;329unsigned long stat, mask;330331spu = data;332333spin_lock(&spu->register_lock);334mask = spu_int_mask_get(spu, 0);335stat = spu_int_stat_get(spu, 0) & mask;336337spu->class_0_pending |= stat;338spu->class_0_dar = spu_mfc_dar_get(spu);339spu->stop_callback(spu, 0);340spu->class_0_pending = 0;341spu->class_0_dar = 0;342343spu_int_stat_clear(spu, 0, stat);344spin_unlock(&spu->register_lock);345346return IRQ_HANDLED;347}348349static irqreturn_t350spu_irq_class_1(int irq, void *data)351{352struct spu *spu;353unsigned long stat, mask, dar, dsisr;354355spu = data;356357/* atomically read & clear class1 status. */358spin_lock(&spu->register_lock);359mask = spu_int_mask_get(spu, 1);360stat = spu_int_stat_get(spu, 1) & mask;361dar = spu_mfc_dar_get(spu);362dsisr = spu_mfc_dsisr_get(spu);363if (stat & CLASS1_STORAGE_FAULT_INTR)364spu_mfc_dsisr_set(spu, 0ul);365spu_int_stat_clear(spu, 1, stat);366367pr_debug("%s: %lx %lx %lx %lx\n", __func__, mask, stat,368dar, dsisr);369370if (stat & CLASS1_SEGMENT_FAULT_INTR)371__spu_trap_data_seg(spu, dar);372373if (stat & CLASS1_STORAGE_FAULT_INTR)374__spu_trap_data_map(spu, dar, dsisr);375376if (stat & CLASS1_LS_COMPARE_SUSPEND_ON_GET_INTR)377;378379if (stat & CLASS1_LS_COMPARE_SUSPEND_ON_PUT_INTR)380;381382spu->class_1_dsisr = 0;383spu->class_1_dar = 0;384385spin_unlock(&spu->register_lock);386387return stat ? IRQ_HANDLED : IRQ_NONE;388}389390static irqreturn_t391spu_irq_class_2(int irq, void *data)392{393struct spu *spu;394unsigned long stat;395unsigned long mask;396const int mailbox_intrs =397CLASS2_MAILBOX_THRESHOLD_INTR | CLASS2_MAILBOX_INTR;398399spu = data;400spin_lock(&spu->register_lock);401stat = spu_int_stat_get(spu, 2);402mask = spu_int_mask_get(spu, 2);403/* ignore interrupts we're not waiting for */404stat &= mask;405/* mailbox interrupts are level triggered. mask them now before406* acknowledging */407if (stat & mailbox_intrs)408spu_int_mask_and(spu, 2, ~(stat & mailbox_intrs));409/* acknowledge all interrupts before the callbacks */410spu_int_stat_clear(spu, 2, stat);411412pr_debug("class 2 interrupt %d, %lx, %lx\n", irq, stat, mask);413414if (stat & CLASS2_MAILBOX_INTR)415spu->ibox_callback(spu);416417if (stat & CLASS2_SPU_STOP_INTR)418spu->stop_callback(spu, 2);419420if (stat & CLASS2_SPU_HALT_INTR)421spu->stop_callback(spu, 2);422423if (stat & CLASS2_SPU_DMA_TAG_GROUP_COMPLETE_INTR)424spu->mfc_callback(spu);425426if (stat & CLASS2_MAILBOX_THRESHOLD_INTR)427spu->wbox_callback(spu);428429spu->stats.class2_intr++;430431spin_unlock(&spu->register_lock);432433return stat ? IRQ_HANDLED : IRQ_NONE;434}435436static int spu_request_irqs(struct spu *spu)437{438int ret = 0;439440if (spu->irqs[0] != NO_IRQ) {441snprintf(spu->irq_c0, sizeof (spu->irq_c0), "spe%02d.0",442spu->number);443ret = request_irq(spu->irqs[0], spu_irq_class_0,444IRQF_DISABLED,445spu->irq_c0, spu);446if (ret)447goto bail0;448}449if (spu->irqs[1] != NO_IRQ) {450snprintf(spu->irq_c1, sizeof (spu->irq_c1), "spe%02d.1",451spu->number);452ret = request_irq(spu->irqs[1], spu_irq_class_1,453IRQF_DISABLED,454spu->irq_c1, spu);455if (ret)456goto bail1;457}458if (spu->irqs[2] != NO_IRQ) {459snprintf(spu->irq_c2, sizeof (spu->irq_c2), "spe%02d.2",460spu->number);461ret = request_irq(spu->irqs[2], spu_irq_class_2,462IRQF_DISABLED,463spu->irq_c2, spu);464if (ret)465goto bail2;466}467return 0;468469bail2:470if (spu->irqs[1] != NO_IRQ)471free_irq(spu->irqs[1], spu);472bail1:473if (spu->irqs[0] != NO_IRQ)474free_irq(spu->irqs[0], spu);475bail0:476return ret;477}478479static void spu_free_irqs(struct spu *spu)480{481if (spu->irqs[0] != NO_IRQ)482free_irq(spu->irqs[0], spu);483if (spu->irqs[1] != NO_IRQ)484free_irq(spu->irqs[1], spu);485if (spu->irqs[2] != NO_IRQ)486free_irq(spu->irqs[2], spu);487}488489void spu_init_channels(struct spu *spu)490{491static const struct {492unsigned channel;493unsigned count;494} zero_list[] = {495{ 0x00, 1, }, { 0x01, 1, }, { 0x03, 1, }, { 0x04, 1, },496{ 0x18, 1, }, { 0x19, 1, }, { 0x1b, 1, }, { 0x1d, 1, },497}, count_list[] = {498{ 0x00, 0, }, { 0x03, 0, }, { 0x04, 0, }, { 0x15, 16, },499{ 0x17, 1, }, { 0x18, 0, }, { 0x19, 0, }, { 0x1b, 0, },500{ 0x1c, 1, }, { 0x1d, 0, }, { 0x1e, 1, },501};502struct spu_priv2 __iomem *priv2;503int i;504505priv2 = spu->priv2;506507/* initialize all channel data to zero */508for (i = 0; i < ARRAY_SIZE(zero_list); i++) {509int count;510511out_be64(&priv2->spu_chnlcntptr_RW, zero_list[i].channel);512for (count = 0; count < zero_list[i].count; count++)513out_be64(&priv2->spu_chnldata_RW, 0);514}515516/* initialize channel counts to meaningful values */517for (i = 0; i < ARRAY_SIZE(count_list); i++) {518out_be64(&priv2->spu_chnlcntptr_RW, count_list[i].channel);519out_be64(&priv2->spu_chnlcnt_RW, count_list[i].count);520}521}522EXPORT_SYMBOL_GPL(spu_init_channels);523524static struct sysdev_class spu_sysdev_class = {525.name = "spu",526};527528int spu_add_sysdev_attr(struct sysdev_attribute *attr)529{530struct spu *spu;531532mutex_lock(&spu_full_list_mutex);533list_for_each_entry(spu, &spu_full_list, full_list)534sysdev_create_file(&spu->sysdev, attr);535mutex_unlock(&spu_full_list_mutex);536537return 0;538}539EXPORT_SYMBOL_GPL(spu_add_sysdev_attr);540541int spu_add_sysdev_attr_group(struct attribute_group *attrs)542{543struct spu *spu;544int rc = 0;545546mutex_lock(&spu_full_list_mutex);547list_for_each_entry(spu, &spu_full_list, full_list) {548rc = sysfs_create_group(&spu->sysdev.kobj, attrs);549550/* we're in trouble here, but try unwinding anyway */551if (rc) {552printk(KERN_ERR "%s: can't create sysfs group '%s'\n",553__func__, attrs->name);554555list_for_each_entry_continue_reverse(spu,556&spu_full_list, full_list)557sysfs_remove_group(&spu->sysdev.kobj, attrs);558break;559}560}561562mutex_unlock(&spu_full_list_mutex);563564return rc;565}566EXPORT_SYMBOL_GPL(spu_add_sysdev_attr_group);567568569void spu_remove_sysdev_attr(struct sysdev_attribute *attr)570{571struct spu *spu;572573mutex_lock(&spu_full_list_mutex);574list_for_each_entry(spu, &spu_full_list, full_list)575sysdev_remove_file(&spu->sysdev, attr);576mutex_unlock(&spu_full_list_mutex);577}578EXPORT_SYMBOL_GPL(spu_remove_sysdev_attr);579580void spu_remove_sysdev_attr_group(struct attribute_group *attrs)581{582struct spu *spu;583584mutex_lock(&spu_full_list_mutex);585list_for_each_entry(spu, &spu_full_list, full_list)586sysfs_remove_group(&spu->sysdev.kobj, attrs);587mutex_unlock(&spu_full_list_mutex);588}589EXPORT_SYMBOL_GPL(spu_remove_sysdev_attr_group);590591static int spu_create_sysdev(struct spu *spu)592{593int ret;594595spu->sysdev.id = spu->number;596spu->sysdev.cls = &spu_sysdev_class;597ret = sysdev_register(&spu->sysdev);598if (ret) {599printk(KERN_ERR "Can't register SPU %d with sysfs\n",600spu->number);601return ret;602}603604sysfs_add_device_to_node(&spu->sysdev, spu->node);605606return 0;607}608609static int __init create_spu(void *data)610{611struct spu *spu;612int ret;613static int number;614unsigned long flags;615struct timespec ts;616617ret = -ENOMEM;618spu = kzalloc(sizeof (*spu), GFP_KERNEL);619if (!spu)620goto out;621622spu->alloc_state = SPU_FREE;623624spin_lock_init(&spu->register_lock);625spin_lock(&spu_lock);626spu->number = number++;627spin_unlock(&spu_lock);628629ret = spu_create_spu(spu, data);630631if (ret)632goto out_free;633634spu_mfc_sdr_setup(spu);635spu_mfc_sr1_set(spu, 0x33);636ret = spu_request_irqs(spu);637if (ret)638goto out_destroy;639640ret = spu_create_sysdev(spu);641if (ret)642goto out_free_irqs;643644mutex_lock(&cbe_spu_info[spu->node].list_mutex);645list_add(&spu->cbe_list, &cbe_spu_info[spu->node].spus);646cbe_spu_info[spu->node].n_spus++;647mutex_unlock(&cbe_spu_info[spu->node].list_mutex);648649mutex_lock(&spu_full_list_mutex);650spin_lock_irqsave(&spu_full_list_lock, flags);651list_add(&spu->full_list, &spu_full_list);652spin_unlock_irqrestore(&spu_full_list_lock, flags);653mutex_unlock(&spu_full_list_mutex);654655spu->stats.util_state = SPU_UTIL_IDLE_LOADED;656ktime_get_ts(&ts);657spu->stats.tstamp = timespec_to_ns(&ts);658659INIT_LIST_HEAD(&spu->aff_list);660661goto out;662663out_free_irqs:664spu_free_irqs(spu);665out_destroy:666spu_destroy_spu(spu);667out_free:668kfree(spu);669out:670return ret;671}672673static const char *spu_state_names[] = {674"user", "system", "iowait", "idle"675};676677static unsigned long long spu_acct_time(struct spu *spu,678enum spu_utilization_state state)679{680struct timespec ts;681unsigned long long time = spu->stats.times[state];682683/*684* If the spu is idle or the context is stopped, utilization685* statistics are not updated. Apply the time delta from the686* last recorded state of the spu.687*/688if (spu->stats.util_state == state) {689ktime_get_ts(&ts);690time += timespec_to_ns(&ts) - spu->stats.tstamp;691}692693return time / NSEC_PER_MSEC;694}695696697static ssize_t spu_stat_show(struct sys_device *sysdev,698struct sysdev_attribute *attr, char *buf)699{700struct spu *spu = container_of(sysdev, struct spu, sysdev);701702return sprintf(buf, "%s %llu %llu %llu %llu "703"%llu %llu %llu %llu %llu %llu %llu %llu\n",704spu_state_names[spu->stats.util_state],705spu_acct_time(spu, SPU_UTIL_USER),706spu_acct_time(spu, SPU_UTIL_SYSTEM),707spu_acct_time(spu, SPU_UTIL_IOWAIT),708spu_acct_time(spu, SPU_UTIL_IDLE_LOADED),709spu->stats.vol_ctx_switch,710spu->stats.invol_ctx_switch,711spu->stats.slb_flt,712spu->stats.hash_flt,713spu->stats.min_flt,714spu->stats.maj_flt,715spu->stats.class2_intr,716spu->stats.libassist);717}718719static SYSDEV_ATTR(stat, 0644, spu_stat_show, NULL);720721#ifdef CONFIG_KEXEC722723struct crash_spu_info {724struct spu *spu;725u32 saved_spu_runcntl_RW;726u32 saved_spu_status_R;727u32 saved_spu_npc_RW;728u64 saved_mfc_sr1_RW;729u64 saved_mfc_dar;730u64 saved_mfc_dsisr;731};732733#define CRASH_NUM_SPUS 16 /* Enough for current hardware */734static struct crash_spu_info crash_spu_info[CRASH_NUM_SPUS];735736static void crash_kexec_stop_spus(void)737{738struct spu *spu;739int i;740u64 tmp;741742for (i = 0; i < CRASH_NUM_SPUS; i++) {743if (!crash_spu_info[i].spu)744continue;745746spu = crash_spu_info[i].spu;747748crash_spu_info[i].saved_spu_runcntl_RW =749in_be32(&spu->problem->spu_runcntl_RW);750crash_spu_info[i].saved_spu_status_R =751in_be32(&spu->problem->spu_status_R);752crash_spu_info[i].saved_spu_npc_RW =753in_be32(&spu->problem->spu_npc_RW);754755crash_spu_info[i].saved_mfc_dar = spu_mfc_dar_get(spu);756crash_spu_info[i].saved_mfc_dsisr = spu_mfc_dsisr_get(spu);757tmp = spu_mfc_sr1_get(spu);758crash_spu_info[i].saved_mfc_sr1_RW = tmp;759760tmp &= ~MFC_STATE1_MASTER_RUN_CONTROL_MASK;761spu_mfc_sr1_set(spu, tmp);762763__delay(200);764}765}766767static void crash_register_spus(struct list_head *list)768{769struct spu *spu;770int ret;771772list_for_each_entry(spu, list, full_list) {773if (WARN_ON(spu->number >= CRASH_NUM_SPUS))774continue;775776crash_spu_info[spu->number].spu = spu;777}778779ret = crash_shutdown_register(&crash_kexec_stop_spus);780if (ret)781printk(KERN_ERR "Could not register SPU crash handler");782}783784#else785static inline void crash_register_spus(struct list_head *list)786{787}788#endif789790static void spu_shutdown(void)791{792struct spu *spu;793794mutex_lock(&spu_full_list_mutex);795list_for_each_entry(spu, &spu_full_list, full_list) {796spu_free_irqs(spu);797spu_destroy_spu(spu);798}799mutex_unlock(&spu_full_list_mutex);800}801802static struct syscore_ops spu_syscore_ops = {803.shutdown = spu_shutdown,804};805806static int __init init_spu_base(void)807{808int i, ret = 0;809810for (i = 0; i < MAX_NUMNODES; i++) {811mutex_init(&cbe_spu_info[i].list_mutex);812INIT_LIST_HEAD(&cbe_spu_info[i].spus);813}814815if (!spu_management_ops)816goto out;817818/* create sysdev class for spus */819ret = sysdev_class_register(&spu_sysdev_class);820if (ret)821goto out;822823ret = spu_enumerate_spus(create_spu);824825if (ret < 0) {826printk(KERN_WARNING "%s: Error initializing spus\n",827__func__);828goto out_unregister_sysdev_class;829}830831if (ret > 0)832fb_append_extra_logo(&logo_spe_clut224, ret);833834mutex_lock(&spu_full_list_mutex);835xmon_register_spus(&spu_full_list);836crash_register_spus(&spu_full_list);837mutex_unlock(&spu_full_list_mutex);838spu_add_sysdev_attr(&attr_stat);839register_syscore_ops(&spu_syscore_ops);840841spu_init_affinity();842843return 0;844845out_unregister_sysdev_class:846sysdev_class_unregister(&spu_sysdev_class);847out:848return ret;849}850module_init(init_spu_base);851852MODULE_LICENSE("GPL");853MODULE_AUTHOR("Arnd Bergmann <[email protected]>");854855856