CoCalc -- ppc-opc.c

GitHub Repository: awilliam/linux-vfio
Path: blob/master/arch/powerpc/xmon/ppc-opc.c
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/* ppc-opc.c -- PowerPC opcode list
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   Copyright 1994, 1995, 1996, 1997, 1998, 2000, 2001, 2002, 2003, 2004,
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   2005 Free Software Foundation, Inc.
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   Written by Ian Lance Taylor, Cygnus Support
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   This file is part of GDB, GAS, and the GNU binutils.
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   GDB, GAS, and the GNU binutils are free software; you can redistribute
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   them and/or modify them under the terms of the GNU General Public
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   License as published by the Free Software Foundation; either version
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   2, or (at your option) any later version.
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   GDB, GAS, and the GNU binutils are distributed in the hope that they
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   will be useful, but WITHOUT ANY WARRANTY; without even the implied
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   warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
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   the GNU General Public License for more details.
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   You should have received a copy of the GNU General Public License
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   along with this file; see the file COPYING.  If not, write to the Free
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   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
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   02110-1301, USA.  */
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#include <linux/stddef.h>
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#include <linux/kernel.h>
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#include "nonstdio.h"
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#include "ppc.h"
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#define ATTRIBUTE_UNUSED
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#define _(x)	x
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/* This file holds the PowerPC opcode table.  The opcode table
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   includes almost all of the extended instruction mnemonics.  This
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   permits the disassembler to use them, and simplifies the assembler
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   logic, at the cost of increasing the table size.  The table is
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   strictly constant data, so the compiler should be able to put it in
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   the .text section.
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   This file also holds the operand table.  All knowledge about
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   inserting operands into instructions and vice-versa is kept in this
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   file.  */
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/* Local insertion and extraction functions.  */
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static unsigned long insert_bat (unsigned long, long, int, const char **);
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static long extract_bat (unsigned long, int, int *);
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static unsigned long insert_bba (unsigned long, long, int, const char **);
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static long extract_bba (unsigned long, int, int *);
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static unsigned long insert_bd (unsigned long, long, int, const char **);
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static long extract_bd (unsigned long, int, int *);
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static unsigned long insert_bdm (unsigned long, long, int, const char **);
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static long extract_bdm (unsigned long, int, int *);
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static unsigned long insert_bdp (unsigned long, long, int, const char **);
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static long extract_bdp (unsigned long, int, int *);
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static unsigned long insert_bo (unsigned long, long, int, const char **);
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static long extract_bo (unsigned long, int, int *);
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static unsigned long insert_boe (unsigned long, long, int, const char **);
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static long extract_boe (unsigned long, int, int *);
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static unsigned long insert_dq (unsigned long, long, int, const char **);
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static long extract_dq (unsigned long, int, int *);
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static unsigned long insert_ds (unsigned long, long, int, const char **);
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static long extract_ds (unsigned long, int, int *);
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static unsigned long insert_de (unsigned long, long, int, const char **);
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static long extract_de (unsigned long, int, int *);
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static unsigned long insert_des (unsigned long, long, int, const char **);
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static long extract_des (unsigned long, int, int *);
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static unsigned long insert_fxm (unsigned long, long, int, const char **);
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static long extract_fxm (unsigned long, int, int *);
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static unsigned long insert_li (unsigned long, long, int, const char **);
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static long extract_li (unsigned long, int, int *);
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static unsigned long insert_mbe (unsigned long, long, int, const char **);
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static long extract_mbe (unsigned long, int, int *);
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static unsigned long insert_mb6 (unsigned long, long, int, const char **);
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static long extract_mb6 (unsigned long, int, int *);
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static unsigned long insert_nb (unsigned long, long, int, const char **);
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static long extract_nb (unsigned long, int, int *);
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static unsigned long insert_nsi (unsigned long, long, int, const char **);
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static long extract_nsi (unsigned long, int, int *);
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static unsigned long insert_ral (unsigned long, long, int, const char **);
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static unsigned long insert_ram (unsigned long, long, int, const char **);
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static unsigned long insert_raq (unsigned long, long, int, const char **);
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static unsigned long insert_ras (unsigned long, long, int, const char **);
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static unsigned long insert_rbs (unsigned long, long, int, const char **);
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static long extract_rbs (unsigned long, int, int *);
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static unsigned long insert_rsq (unsigned long, long, int, const char **);
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static unsigned long insert_rtq (unsigned long, long, int, const char **);
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static unsigned long insert_sh6 (unsigned long, long, int, const char **);
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static long extract_sh6 (unsigned long, int, int *);
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static unsigned long insert_spr (unsigned long, long, int, const char **);
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static long extract_spr (unsigned long, int, int *);
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static unsigned long insert_sprg (unsigned long, long, int, const char **);
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static long extract_sprg (unsigned long, int, int *);
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static unsigned long insert_tbr (unsigned long, long, int, const char **);
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static long extract_tbr (unsigned long, int, int *);
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static unsigned long insert_ev2 (unsigned long, long, int, const char **);
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static long extract_ev2 (unsigned long, int, int *);
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static unsigned long insert_ev4 (unsigned long, long, int, const char **);
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static long extract_ev4 (unsigned long, int, int *);
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static unsigned long insert_ev8 (unsigned long, long, int, const char **);
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static long extract_ev8 (unsigned long, int, int *);
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/* The operands table.
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   The fields are bits, shift, insert, extract, flags.
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   We used to put parens around the various additions, like the one
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   for BA just below.  However, that caused trouble with feeble
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   compilers with a limit on depth of a parenthesized expression, like
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   (reportedly) the compiler in Microsoft Developer Studio 5.  So we
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   omit the parens, since the macros are never used in a context where
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   the addition will be ambiguous.  */
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const struct powerpc_operand powerpc_operands[] =
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{
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  /* The zero index is used to indicate the end of the list of
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     operands.  */
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#define UNUSED 0
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  { 0, 0, NULL, NULL, 0 },
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  /* The BA field in an XL form instruction.  */
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#define BA UNUSED + 1
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#define BA_MASK (0x1f << 16)
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  { 5, 16, NULL, NULL, PPC_OPERAND_CR },
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  /* The BA field in an XL form instruction when it must be the same
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     as the BT field in the same instruction.  */
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#define BAT BA + 1
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  { 5, 16, insert_bat, extract_bat, PPC_OPERAND_FAKE },
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  /* The BB field in an XL form instruction.  */
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#define BB BAT + 1
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#define BB_MASK (0x1f << 11)
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  { 5, 11, NULL, NULL, PPC_OPERAND_CR },
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  /* The BB field in an XL form instruction when it must be the same
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     as the BA field in the same instruction.  */
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#define BBA BB + 1
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  { 5, 11, insert_bba, extract_bba, PPC_OPERAND_FAKE },
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  /* The BD field in a B form instruction.  The lower two bits are
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     forced to zero.  */
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#define BD BBA + 1
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  { 16, 0, insert_bd, extract_bd, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
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  /* The BD field in a B form instruction when absolute addressing is
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     used.  */
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#define BDA BD + 1
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  { 16, 0, insert_bd, extract_bd, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
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  /* The BD field in a B form instruction when the - modifier is used.
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     This sets the y bit of the BO field appropriately.  */
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#define BDM BDA + 1
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  { 16, 0, insert_bdm, extract_bdm,
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      PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
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  /* The BD field in a B form instruction when the - modifier is used
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     and absolute address is used.  */
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#define BDMA BDM + 1
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  { 16, 0, insert_bdm, extract_bdm,
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      PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
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  /* The BD field in a B form instruction when the + modifier is used.
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     This sets the y bit of the BO field appropriately.  */
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#define BDP BDMA + 1
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  { 16, 0, insert_bdp, extract_bdp,
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      PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
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  /* The BD field in a B form instruction when the + modifier is used
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     and absolute addressing is used.  */
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#define BDPA BDP + 1
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  { 16, 0, insert_bdp, extract_bdp,
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      PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
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  /* The BF field in an X or XL form instruction.  */
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#define BF BDPA + 1
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  { 3, 23, NULL, NULL, PPC_OPERAND_CR },
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  /* An optional BF field.  This is used for comparison instructions,
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     in which an omitted BF field is taken as zero.  */
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#define OBF BF + 1
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  { 3, 23, NULL, NULL, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
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  /* The BFA field in an X or XL form instruction.  */
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#define BFA OBF + 1
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  { 3, 18, NULL, NULL, PPC_OPERAND_CR },
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  /* The BI field in a B form or XL form instruction.  */
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#define BI BFA + 1
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#define BI_MASK (0x1f << 16)
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  { 5, 16, NULL, NULL, PPC_OPERAND_CR },
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  /* The BO field in a B form instruction.  Certain values are
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     illegal.  */
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#define BO BI + 1
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#define BO_MASK (0x1f << 21)
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  { 5, 21, insert_bo, extract_bo, 0 },
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  /* The BO field in a B form instruction when the + or - modifier is
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     used.  This is like the BO field, but it must be even.  */
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#define BOE BO + 1
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  { 5, 21, insert_boe, extract_boe, 0 },
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#define BH BOE + 1
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  { 2, 11, NULL, NULL, PPC_OPERAND_OPTIONAL },
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  /* The BT field in an X or XL form instruction.  */
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#define BT BH + 1
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  { 5, 21, NULL, NULL, PPC_OPERAND_CR },
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  /* The condition register number portion of the BI field in a B form
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     or XL form instruction.  This is used for the extended
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     conditional branch mnemonics, which set the lower two bits of the
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     BI field.  This field is optional.  */
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#define CR BT + 1
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  { 3, 18, NULL, NULL, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
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  /* The CRB field in an X form instruction.  */
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#define CRB CR + 1
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  { 5, 6, NULL, NULL, 0 },
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  /* The CRFD field in an X form instruction.  */
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#define CRFD CRB + 1
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  { 3, 23, NULL, NULL, PPC_OPERAND_CR },
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  /* The CRFS field in an X form instruction.  */
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#define CRFS CRFD + 1
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  { 3, 0, NULL, NULL, PPC_OPERAND_CR },
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  /* The CT field in an X form instruction.  */
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#define CT CRFS + 1
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  { 5, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
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  /* The D field in a D form instruction.  This is a displacement off
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     a register, and implies that the next operand is a register in
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     parentheses.  */
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#define D CT + 1
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  { 16, 0, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
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  /* The DE field in a DE form instruction.  This is like D, but is 12
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     bits only.  */
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#define DE D + 1
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  { 14, 0, insert_de, extract_de, PPC_OPERAND_PARENS },
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  /* The DES field in a DES form instruction.  This is like DS, but is 14
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     bits only (12 stored.)  */
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#define DES DE + 1
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  { 14, 0, insert_des, extract_des, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
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  /* The DQ field in a DQ form instruction.  This is like D, but the
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     lower four bits are forced to zero. */
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#define DQ DES + 1
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  { 16, 0, insert_dq, extract_dq,
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      PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DQ },
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  /* The DS field in a DS form instruction.  This is like D, but the
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     lower two bits are forced to zero.  */
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#define DS DQ + 1
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  { 16, 0, insert_ds, extract_ds,
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      PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DS },
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  /* The E field in a wrteei instruction.  */
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#define E DS + 1
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  { 1, 15, NULL, NULL, 0 },
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  /* The FL1 field in a POWER SC form instruction.  */
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#define FL1 E + 1
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  { 4, 12, NULL, NULL, 0 },
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  /* The FL2 field in a POWER SC form instruction.  */
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#define FL2 FL1 + 1
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  { 3, 2, NULL, NULL, 0 },
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  /* The FLM field in an XFL form instruction.  */
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#define FLM FL2 + 1
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  { 8, 17, NULL, NULL, 0 },
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  /* The FRA field in an X or A form instruction.  */
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#define FRA FLM + 1
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#define FRA_MASK (0x1f << 16)
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  { 5, 16, NULL, NULL, PPC_OPERAND_FPR },
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  /* The FRB field in an X or A form instruction.  */
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#define FRB FRA + 1
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#define FRB_MASK (0x1f << 11)
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  { 5, 11, NULL, NULL, PPC_OPERAND_FPR },
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  /* The FRC field in an A form instruction.  */
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#define FRC FRB + 1
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#define FRC_MASK (0x1f << 6)
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  { 5, 6, NULL, NULL, PPC_OPERAND_FPR },
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  /* The FRS field in an X form instruction or the FRT field in a D, X
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     or A form instruction.  */
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#define FRS FRC + 1
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#define FRT FRS
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  { 5, 21, NULL, NULL, PPC_OPERAND_FPR },
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  /* The FXM field in an XFX instruction.  */
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#define FXM FRS + 1
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#define FXM_MASK (0xff << 12)
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  { 8, 12, insert_fxm, extract_fxm, 0 },
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  /* Power4 version for mfcr.  */
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#define FXM4 FXM + 1
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  { 8, 12, insert_fxm, extract_fxm, PPC_OPERAND_OPTIONAL },
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  /* The L field in a D or X form instruction.  */
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#define L FXM4 + 1
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  { 1, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
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  /* The LEV field in a POWER SVC form instruction.  */
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#define SVC_LEV L + 1
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  { 7, 5, NULL, NULL, 0 },
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  /* The LEV field in an SC form instruction.  */
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#define LEV SVC_LEV + 1
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  { 7, 5, NULL, NULL, PPC_OPERAND_OPTIONAL },
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  /* The LI field in an I form instruction.  The lower two bits are
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     forced to zero.  */
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#define LI LEV + 1
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  { 26, 0, insert_li, extract_li, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
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  /* The LI field in an I form instruction when used as an absolute
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     address.  */
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#define LIA LI + 1
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  { 26, 0, insert_li, extract_li, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
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  /* The LS field in an X (sync) form instruction.  */
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#define LS LIA + 1
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  { 2, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
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  /* The MB field in an M form instruction.  */
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#define MB LS + 1
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#define MB_MASK (0x1f << 6)
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  { 5, 6, NULL, NULL, 0 },
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  /* The ME field in an M form instruction.  */
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#define ME MB + 1
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#define ME_MASK (0x1f << 1)
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  { 5, 1, NULL, NULL, 0 },
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  /* The MB and ME fields in an M form instruction expressed a single
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     operand which is a bitmask indicating which bits to select.  This
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     is a two operand form using PPC_OPERAND_NEXT.  See the
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     description in opcode/ppc.h for what this means.  */
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#define MBE ME + 1
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  { 5, 6, NULL, NULL, PPC_OPERAND_OPTIONAL | PPC_OPERAND_NEXT },
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  { 32, 0, insert_mbe, extract_mbe, 0 },
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  /* The MB or ME field in an MD or MDS form instruction.  The high
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     bit is wrapped to the low end.  */
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#define MB6 MBE + 2
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#define ME6 MB6
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#define MB6_MASK (0x3f << 5)
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  { 6, 5, insert_mb6, extract_mb6, 0 },
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  /* The MO field in an mbar instruction.  */
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#define MO MB6 + 1
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  { 5, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
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  /* The NB field in an X form instruction.  The value 32 is stored as
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     0.  */
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#define NB MO + 1
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  { 6, 11, insert_nb, extract_nb, 0 },
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  /* The NSI field in a D form instruction.  This is the same as the
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     SI field, only negated.  */
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#define NSI NB + 1
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  { 16, 0, insert_nsi, extract_nsi,
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      PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED },
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  /* The RA field in an D, DS, DQ, X, XO, M, or MDS form instruction.  */
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#define RA NSI + 1
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#define RA_MASK (0x1f << 16)
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  { 5, 16, NULL, NULL, PPC_OPERAND_GPR },
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  /* As above, but 0 in the RA field means zero, not r0.  */
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#define RA0 RA + 1
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  { 5, 16, NULL, NULL, PPC_OPERAND_GPR_0 },
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  /* The RA field in the DQ form lq instruction, which has special
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     value restrictions.  */
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#define RAQ RA0 + 1
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  { 5, 16, insert_raq, NULL, PPC_OPERAND_GPR_0 },
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  /* The RA field in a D or X form instruction which is an updating
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     load, which means that the RA field may not be zero and may not
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     equal the RT field.  */
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#define RAL RAQ + 1
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  { 5, 16, insert_ral, NULL, PPC_OPERAND_GPR_0 },
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  /* The RA field in an lmw instruction, which has special value
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     restrictions.  */
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#define RAM RAL + 1
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  { 5, 16, insert_ram, NULL, PPC_OPERAND_GPR_0 },
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  /* The RA field in a D or X form instruction which is an updating
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     store or an updating floating point load, which means that the RA
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     field may not be zero.  */
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#define RAS RAM + 1
401
  { 5, 16, insert_ras, NULL, PPC_OPERAND_GPR_0 },
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  /* The RA field of the tlbwe instruction, which is optional.  */
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#define RAOPT RAS + 1
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  { 5, 16, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },
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407
  /* The RB field in an X, XO, M, or MDS form instruction.  */
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#define RB RAOPT + 1
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#define RB_MASK (0x1f << 11)
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  { 5, 11, NULL, NULL, PPC_OPERAND_GPR },
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412
  /* The RB field in an X form instruction when it must be the same as
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     the RS field in the instruction.  This is used for extended
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     mnemonics like mr.  */
415
#define RBS RB + 1
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  { 5, 1, insert_rbs, extract_rbs, PPC_OPERAND_FAKE },
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418
  /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form
419
     instruction or the RT field in a D, DS, X, XFX or XO form
420
     instruction.  */
421
#define RS RBS + 1
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#define RT RS
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#define RT_MASK (0x1f << 21)
424
  { 5, 21, NULL, NULL, PPC_OPERAND_GPR },
425

426
  /* The RS field of the DS form stq instruction, which has special
427
     value restrictions.  */
428
#define RSQ RS + 1
429
  { 5, 21, insert_rsq, NULL, PPC_OPERAND_GPR_0 },
430

431
  /* The RT field of the DQ form lq instruction, which has special
432
     value restrictions.  */
433
#define RTQ RSQ + 1
434
  { 5, 21, insert_rtq, NULL, PPC_OPERAND_GPR_0 },
435

436
  /* The RS field of the tlbwe instruction, which is optional.  */
437
#define RSO RTQ + 1
438
#define RTO RSO
439
  { 5, 21, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },
440

441
  /* The SH field in an X or M form instruction.  */
442
#define SH RSO + 1
443
#define SH_MASK (0x1f << 11)
444
  { 5, 11, NULL, NULL, 0 },
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446
  /* The SH field in an MD form instruction.  This is split.  */
447
#define SH6 SH + 1
448
#define SH6_MASK ((0x1f << 11) | (1 << 1))
449
  { 6, 1, insert_sh6, extract_sh6, 0 },
450

451
  /* The SH field of the tlbwe instruction, which is optional.  */
452
#define SHO SH6 + 1
453
  { 5, 11,NULL, NULL, PPC_OPERAND_OPTIONAL },
454

455
  /* The SI field in a D form instruction.  */
456
#define SI SHO + 1
457
  { 16, 0, NULL, NULL, PPC_OPERAND_SIGNED },
458

459
  /* The SI field in a D form instruction when we accept a wide range
460
     of positive values.  */
461
#define SISIGNOPT SI + 1
462
  { 16, 0, NULL, NULL, PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
463

464
  /* The SPR field in an XFX form instruction.  This is flipped--the
465
     lower 5 bits are stored in the upper 5 and vice- versa.  */
466
#define SPR SISIGNOPT + 1
467
#define PMR SPR
468
#define SPR_MASK (0x3ff << 11)
469
  { 10, 11, insert_spr, extract_spr, 0 },
470

471
  /* The BAT index number in an XFX form m[ft]ibat[lu] instruction.  */
472
#define SPRBAT SPR + 1
473
#define SPRBAT_MASK (0x3 << 17)
474
  { 2, 17, NULL, NULL, 0 },
475

476
  /* The SPRG register number in an XFX form m[ft]sprg instruction.  */
477
#define SPRG SPRBAT + 1
478
  { 5, 16, insert_sprg, extract_sprg, 0 },
479

480
  /* The SR field in an X form instruction.  */
481
#define SR SPRG + 1
482
  { 4, 16, NULL, NULL, 0 },
483

484
  /* The STRM field in an X AltiVec form instruction.  */
485
#define STRM SR + 1
486
#define STRM_MASK (0x3 << 21)
487
  { 2, 21, NULL, NULL, 0 },
488

489
  /* The SV field in a POWER SC form instruction.  */
490
#define SV STRM + 1
491
  { 14, 2, NULL, NULL, 0 },
492

493
  /* The TBR field in an XFX form instruction.  This is like the SPR
494
     field, but it is optional.  */
495
#define TBR SV + 1
496
  { 10, 11, insert_tbr, extract_tbr, PPC_OPERAND_OPTIONAL },
497

498
  /* The TO field in a D or X form instruction.  */
499
#define TO TBR + 1
500
#define TO_MASK (0x1f << 21)
501
  { 5, 21, NULL, NULL, 0 },
502

503
  /* The U field in an X form instruction.  */
504
#define U TO + 1
505
  { 4, 12, NULL, NULL, 0 },
506

507
  /* The UI field in a D form instruction.  */
508
#define UI U + 1
509
  { 16, 0, NULL, NULL, 0 },
510

511
  /* The VA field in a VA, VX or VXR form instruction.  */
512
#define VA UI + 1
513
#define VA_MASK	(0x1f << 16)
514
  { 5, 16, NULL, NULL, PPC_OPERAND_VR },
515

516
  /* The VB field in a VA, VX or VXR form instruction.  */
517
#define VB VA + 1
518
#define VB_MASK (0x1f << 11)
519
  { 5, 11, NULL, NULL, PPC_OPERAND_VR },
520

521
  /* The VC field in a VA form instruction.  */
522
#define VC VB + 1
523
#define VC_MASK (0x1f << 6)
524
  { 5, 6, NULL, NULL, PPC_OPERAND_VR },
525

526
  /* The VD or VS field in a VA, VX, VXR or X form instruction.  */
527
#define VD VC + 1
528
#define VS VD
529
#define VD_MASK (0x1f << 21)
530
  { 5, 21, NULL, NULL, PPC_OPERAND_VR },
531

532
  /* The SIMM field in a VX form instruction.  */
533
#define SIMM VD + 1
534
  { 5, 16, NULL, NULL, PPC_OPERAND_SIGNED},
535

536
  /* The UIMM field in a VX form instruction.  */
537
#define UIMM SIMM + 1
538
  { 5, 16, NULL, NULL, 0 },
539

540
  /* The SHB field in a VA form instruction.  */
541
#define SHB UIMM + 1
542
  { 4, 6, NULL, NULL, 0 },
543

544
  /* The other UIMM field in a EVX form instruction.  */
545
#define EVUIMM SHB + 1
546
  { 5, 11, NULL, NULL, 0 },
547

548
  /* The other UIMM field in a half word EVX form instruction.  */
549
#define EVUIMM_2 EVUIMM + 1
550
  { 32, 11, insert_ev2, extract_ev2, PPC_OPERAND_PARENS },
551

552
  /* The other UIMM field in a word EVX form instruction.  */
553
#define EVUIMM_4 EVUIMM_2 + 1
554
  { 32, 11, insert_ev4, extract_ev4, PPC_OPERAND_PARENS },
555

556
  /* The other UIMM field in a double EVX form instruction.  */
557
#define EVUIMM_8 EVUIMM_4 + 1
558
  { 32, 11, insert_ev8, extract_ev8, PPC_OPERAND_PARENS },
559

560
  /* The WS field.  */
561
#define WS EVUIMM_8 + 1
562
#define WS_MASK (0x7 << 11)
563
  { 3, 11, NULL, NULL, 0 },
564

565
  /* The L field in an mtmsrd or A form instruction.  */
566
#define MTMSRD_L WS + 1
567
#define A_L MTMSRD_L
568
  { 1, 16, NULL, NULL, PPC_OPERAND_OPTIONAL },
569

570
  /* The DCM field in a Z form instruction.  */
571
#define DCM MTMSRD_L + 1
572
  { 6, 16, NULL, NULL, 0 },
573

574
  /* Likewise, the DGM field in a Z form instruction.  */
575
#define DGM DCM + 1
576
  { 6, 16, NULL, NULL, 0 },
577

578
#define TE DGM + 1
579
  { 5, 11, NULL, NULL, 0 },
580

581
#define RMC TE + 1
582
  { 2, 21, NULL, NULL, 0 },
583

584
#define R RMC + 1
585
  { 1, 15, NULL, NULL, 0 },
586

587
#define SP R + 1
588
  { 2, 11, NULL, NULL, 0 },
589

590
#define S SP + 1
591
  { 1, 11, NULL, NULL, 0 },
592

593
  /* SH field starting at bit position 16.  */
594
#define SH16 S + 1
595
  { 6, 10, NULL, NULL, 0 },
596

597
  /* The L field in an X form with the RT field fixed instruction.  */
598
#define XRT_L SH16 + 1
599
  { 2, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
600

601
  /* The EH field in larx instruction.  */
602
#define EH XRT_L + 1
603
  { 1, 0, NULL, NULL, PPC_OPERAND_OPTIONAL },
604
};
605

606
/* The functions used to insert and extract complicated operands.  */
607

608
/* The BA field in an XL form instruction when it must be the same as
609
   the BT field in the same instruction.  This operand is marked FAKE.
610
   The insertion function just copies the BT field into the BA field,
611
   and the extraction function just checks that the fields are the
612
   same.  */
613

614
static unsigned long
615
insert_bat (unsigned long insn,
616
	    long value ATTRIBUTE_UNUSED,
617
	    int dialect ATTRIBUTE_UNUSED,
618
	    const char **errmsg ATTRIBUTE_UNUSED)
619
{
620
  return insn | (((insn >> 21) & 0x1f) << 16);
621
}
622

623
static long
624
extract_bat (unsigned long insn,
625
	     int dialect ATTRIBUTE_UNUSED,
626
	     int *invalid)
627
{
628
  if (((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f))
629
    *invalid = 1;
630
  return 0;
631
}
632

633
/* The BB field in an XL form instruction when it must be the same as
634
   the BA field in the same instruction.  This operand is marked FAKE.
635
   The insertion function just copies the BA field into the BB field,
636
   and the extraction function just checks that the fields are the
637
   same.  */
638

639
static unsigned long
640
insert_bba (unsigned long insn,
641
	    long value ATTRIBUTE_UNUSED,
642
	    int dialect ATTRIBUTE_UNUSED,
643
	    const char **errmsg ATTRIBUTE_UNUSED)
644
{
645
  return insn | (((insn >> 16) & 0x1f) << 11);
646
}
647

648
static long
649
extract_bba (unsigned long insn,
650
	     int dialect ATTRIBUTE_UNUSED,
651
	     int *invalid)
652
{
653
  if (((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f))
654
    *invalid = 1;
655
  return 0;
656
}
657

658
/* The BD field in a B form instruction.  The lower two bits are
659
   forced to zero.  */
660

661
static unsigned long
662
insert_bd (unsigned long insn,
663
	   long value,
664
	   int dialect ATTRIBUTE_UNUSED,
665
	   const char **errmsg ATTRIBUTE_UNUSED)
666
{
667
  return insn | (value & 0xfffc);
668
}
669

670
static long
671
extract_bd (unsigned long insn,
672
	    int dialect ATTRIBUTE_UNUSED,
673
	    int *invalid ATTRIBUTE_UNUSED)
674
{
675
  return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
676
}
677

678
/* The BD field in a B form instruction when the - modifier is used.
679
   This modifier means that the branch is not expected to be taken.
680
   For chips built to versions of the architecture prior to version 2
681
   (ie. not Power4 compatible), we set the y bit of the BO field to 1
682
   if the offset is negative.  When extracting, we require that the y
683
   bit be 1 and that the offset be positive, since if the y bit is 0
684
   we just want to print the normal form of the instruction.
685
   Power4 compatible targets use two bits, "a", and "t", instead of
686
   the "y" bit.  "at" == 00 => no hint, "at" == 01 => unpredictable,
687
   "at" == 10 => not taken, "at" == 11 => taken.  The "t" bit is 00001
688
   in BO field, the "a" bit is 00010 for branch on CR(BI) and 01000
689
   for branch on CTR.  We only handle the taken/not-taken hint here.  */
690

691
static unsigned long
692
insert_bdm (unsigned long insn,
693
	    long value,
694
	    int dialect,
695
	    const char **errmsg ATTRIBUTE_UNUSED)
696
{
697
  if ((dialect & PPC_OPCODE_POWER4) == 0)
698
    {
699
      if ((value & 0x8000) != 0)
700
	insn |= 1 << 21;
701
    }
702
  else
703
    {
704
      if ((insn & (0x14 << 21)) == (0x04 << 21))
705
	insn |= 0x02 << 21;
706
      else if ((insn & (0x14 << 21)) == (0x10 << 21))
707
	insn |= 0x08 << 21;
708
    }
709
  return insn | (value & 0xfffc);
710
}
711

712
static long
713
extract_bdm (unsigned long insn,
714
	     int dialect,
715
	     int *invalid)
716
{
717
  if ((dialect & PPC_OPCODE_POWER4) == 0)
718
    {
719
      if (((insn & (1 << 21)) == 0) != ((insn & (1 << 15)) == 0))
720
	*invalid = 1;
721
    }
722
  else
723
    {
724
      if ((insn & (0x17 << 21)) != (0x06 << 21)
725
	  && (insn & (0x1d << 21)) != (0x18 << 21))
726
	*invalid = 1;
727
    }
728

729
  return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
730
}
731

732
/* The BD field in a B form instruction when the + modifier is used.
733
   This is like BDM, above, except that the branch is expected to be
734
   taken.  */
735

736
static unsigned long
737
insert_bdp (unsigned long insn,
738
	    long value,
739
	    int dialect,
740
	    const char **errmsg ATTRIBUTE_UNUSED)
741
{
742
  if ((dialect & PPC_OPCODE_POWER4) == 0)
743
    {
744
      if ((value & 0x8000) == 0)
745
	insn |= 1 << 21;
746
    }
747
  else
748
    {
749
      if ((insn & (0x14 << 21)) == (0x04 << 21))
750
	insn |= 0x03 << 21;
751
      else if ((insn & (0x14 << 21)) == (0x10 << 21))
752
	insn |= 0x09 << 21;
753
    }
754
  return insn | (value & 0xfffc);
755
}
756

757
static long
758
extract_bdp (unsigned long insn,
759
	     int dialect,
760
	     int *invalid)
761
{
762
  if ((dialect & PPC_OPCODE_POWER4) == 0)
763
    {
764
      if (((insn & (1 << 21)) == 0) == ((insn & (1 << 15)) == 0))
765
	*invalid = 1;
766
    }
767
  else
768
    {
769
      if ((insn & (0x17 << 21)) != (0x07 << 21)
770
	  && (insn & (0x1d << 21)) != (0x19 << 21))
771
	*invalid = 1;
772
    }
773

774
  return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
775
}
776

777
/* Check for legal values of a BO field.  */
778

779
static int
780
valid_bo (long value, int dialect)
781
{
782
  if ((dialect & PPC_OPCODE_POWER4) == 0)
783
    {
784
      /* Certain encodings have bits that are required to be zero.
785
	 These are (z must be zero, y may be anything):
786
	     001zy
787
	     011zy
788
	     1z00y
789
	     1z01y
790
	     1z1zz
791
      */
792
      switch (value & 0x14)
793
	{
794
	default:
795
	case 0:
796
	  return 1;
797
	case 0x4:
798
	  return (value & 0x2) == 0;
799
	case 0x10:
800
	  return (value & 0x8) == 0;
801
	case 0x14:
802
	  return value == 0x14;
803
	}
804
    }
805
  else
806
    {
807
      /* Certain encodings have bits that are required to be zero.
808
	 These are (z must be zero, a & t may be anything):
809
	     0000z
810
	     0001z
811
	     0100z
812
	     0101z
813
	     001at
814
	     011at
815
	     1a00t
816
	     1a01t
817
	     1z1zz
818
      */
819
      if ((value & 0x14) == 0)
820
	return (value & 0x1) == 0;
821
      else if ((value & 0x14) == 0x14)
822
	return value == 0x14;
823
      else
824
	return 1;
825
    }
826
}
827

828
/* The BO field in a B form instruction.  Warn about attempts to set
829
   the field to an illegal value.  */
830

831
static unsigned long
832
insert_bo (unsigned long insn,
833
	   long value,
834
	   int dialect,
835
	   const char **errmsg)
836
{
837
  if (!valid_bo (value, dialect))
838
    *errmsg = _("invalid conditional option");
839
  return insn | ((value & 0x1f) << 21);
840
}
841

842
static long
843
extract_bo (unsigned long insn,
844
	    int dialect,
845
	    int *invalid)
846
{
847
  long value;
848

849
  value = (insn >> 21) & 0x1f;
850
  if (!valid_bo (value, dialect))
851
    *invalid = 1;
852
  return value;
853
}
854

855
/* The BO field in a B form instruction when the + or - modifier is
856
   used.  This is like the BO field, but it must be even.  When
857
   extracting it, we force it to be even.  */
858

859
static unsigned long
860
insert_boe (unsigned long insn,
861
	    long value,
862
	    int dialect,
863
	    const char **errmsg)
864
{
865
  if (!valid_bo (value, dialect))
866
    *errmsg = _("invalid conditional option");
867
  else if ((value & 1) != 0)
868
    *errmsg = _("attempt to set y bit when using + or - modifier");
869

870
  return insn | ((value & 0x1f) << 21);
871
}
872

873
static long
874
extract_boe (unsigned long insn,
875
	     int dialect,
876
	     int *invalid)
877
{
878
  long value;
879

880
  value = (insn >> 21) & 0x1f;
881
  if (!valid_bo (value, dialect))
882
    *invalid = 1;
883
  return value & 0x1e;
884
}
885

886
/* The DQ field in a DQ form instruction.  This is like D, but the
887
   lower four bits are forced to zero. */
888

889
static unsigned long
890
insert_dq (unsigned long insn,
891
	   long value,
892
	   int dialect ATTRIBUTE_UNUSED,
893
	   const char **errmsg)
894
{
895
  if ((value & 0xf) != 0)
896
    *errmsg = _("offset not a multiple of 16");
897
  return insn | (value & 0xfff0);
898
}
899

900
static long
901
extract_dq (unsigned long insn,
902
	    int dialect ATTRIBUTE_UNUSED,
903
	    int *invalid ATTRIBUTE_UNUSED)
904
{
905
  return ((insn & 0xfff0) ^ 0x8000) - 0x8000;
906
}
907

908
static unsigned long
909
insert_ev2 (unsigned long insn,
910
	    long value,
911
	    int dialect ATTRIBUTE_UNUSED,
912
	    const char **errmsg)
913
{
914
  if ((value & 1) != 0)
915
    *errmsg = _("offset not a multiple of 2");
916
  if ((value > 62) != 0)
917
    *errmsg = _("offset greater than 62");
918
  return insn | ((value & 0x3e) << 10);
919
}
920

921
static long
922
extract_ev2 (unsigned long insn,
923
	     int dialect ATTRIBUTE_UNUSED,
924
	     int *invalid ATTRIBUTE_UNUSED)
925
{
926
  return (insn >> 10) & 0x3e;
927
}
928

929
static unsigned long
930
insert_ev4 (unsigned long insn,
931
	    long value,
932
	    int dialect ATTRIBUTE_UNUSED,
933
	    const char **errmsg)
934
{
935
  if ((value & 3) != 0)
936
    *errmsg = _("offset not a multiple of 4");
937
  if ((value > 124) != 0)
938
    *errmsg = _("offset greater than 124");
939
  return insn | ((value & 0x7c) << 9);
940
}
941

942
static long
943
extract_ev4 (unsigned long insn,
944
	     int dialect ATTRIBUTE_UNUSED,
945
	     int *invalid ATTRIBUTE_UNUSED)
946
{
947
  return (insn >> 9) & 0x7c;
948
}
949

950
static unsigned long
951
insert_ev8 (unsigned long insn,
952
	    long value,
953
	    int dialect ATTRIBUTE_UNUSED,
954
	    const char **errmsg)
955
{
956
  if ((value & 7) != 0)
957
    *errmsg = _("offset not a multiple of 8");
958
  if ((value > 248) != 0)
959
    *errmsg = _("offset greater than 248");
960
  return insn | ((value & 0xf8) << 8);
961
}
962

963
static long
964
extract_ev8 (unsigned long insn,
965
	     int dialect ATTRIBUTE_UNUSED,
966
	     int *invalid ATTRIBUTE_UNUSED)
967
{
968
  return (insn >> 8) & 0xf8;
969
}
970

971
/* The DS field in a DS form instruction.  This is like D, but the
972
   lower two bits are forced to zero.  */
973

974
static unsigned long
975
insert_ds (unsigned long insn,
976
	   long value,
977
	   int dialect ATTRIBUTE_UNUSED,
978
	   const char **errmsg)
979
{
980
  if ((value & 3) != 0)
981
    *errmsg = _("offset not a multiple of 4");
982
  return insn | (value & 0xfffc);
983
}
984

985
static long
986
extract_ds (unsigned long insn,
987
	    int dialect ATTRIBUTE_UNUSED,
988
	    int *invalid ATTRIBUTE_UNUSED)
989
{
990
  return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
991
}
992

993
/* The DE field in a DE form instruction.  */
994

995
static unsigned long
996
insert_de (unsigned long insn,
997
	   long value,
998
	   int dialect ATTRIBUTE_UNUSED,
999
	   const char **errmsg)
1000
{
1001
  if (value > 2047 || value < -2048)
1002
    *errmsg = _("offset not between -2048 and 2047");
1003
  return insn | ((value << 4) & 0xfff0);
1004
}
1005

1006
static long
1007
extract_de (unsigned long insn,
1008
	    int dialect ATTRIBUTE_UNUSED,
1009
	    int *invalid ATTRIBUTE_UNUSED)
1010
{
1011
  return (insn & 0xfff0) >> 4;
1012
}
1013

1014
/* The DES field in a DES form instruction.  */
1015

1016
static unsigned long
1017
insert_des (unsigned long insn,
1018
	    long value,
1019
	    int dialect ATTRIBUTE_UNUSED,
1020
	    const char **errmsg)
1021
{
1022
  if (value > 8191 || value < -8192)
1023
    *errmsg = _("offset not between -8192 and 8191");
1024
  else if ((value & 3) != 0)
1025
    *errmsg = _("offset not a multiple of 4");
1026
  return insn | ((value << 2) & 0xfff0);
1027
}
1028

1029
static long
1030
extract_des (unsigned long insn,
1031
	     int dialect ATTRIBUTE_UNUSED,
1032
	     int *invalid ATTRIBUTE_UNUSED)
1033
{
1034
  return (((insn >> 2) & 0x3ffc) ^ 0x2000) - 0x2000;
1035
}
1036

1037
/* FXM mask in mfcr and mtcrf instructions.  */
1038

1039
static unsigned long
1040
insert_fxm (unsigned long insn,
1041
	    long value,
1042
	    int dialect,
1043
	    const char **errmsg)
1044
{
1045
  /* If we're handling the mfocrf and mtocrf insns ensure that exactly
1046
     one bit of the mask field is set.  */
1047
  if ((insn & (1 << 20)) != 0)
1048
    {
1049
      if (value == 0 || (value & -value) != value)
1050
	{
1051
	  *errmsg = _("invalid mask field");
1052
	  value = 0;
1053
	}
1054
    }
1055

1056
  /* If the optional field on mfcr is missing that means we want to use
1057
     the old form of the instruction that moves the whole cr.  In that
1058
     case we'll have VALUE zero.  There doesn't seem to be a way to
1059
     distinguish this from the case where someone writes mfcr %r3,0.  */
1060
  else if (value == 0)
1061
    ;
1062

1063
  /* If only one bit of the FXM field is set, we can use the new form
1064
     of the instruction, which is faster.  Unlike the Power4 branch hint
1065
     encoding, this is not backward compatible.  Do not generate the
1066
     new form unless -mpower4 has been given, or -many and the two
1067
     operand form of mfcr was used.  */
1068
  else if ((value & -value) == value
1069
	   && ((dialect & PPC_OPCODE_POWER4) != 0
1070
	       || ((dialect & PPC_OPCODE_ANY) != 0
1071
		   && (insn & (0x3ff << 1)) == 19 << 1)))
1072
    insn |= 1 << 20;
1073

1074
  /* Any other value on mfcr is an error.  */
1075
  else if ((insn & (0x3ff << 1)) == 19 << 1)
1076
    {
1077
      *errmsg = _("ignoring invalid mfcr mask");
1078
      value = 0;
1079
    }
1080

1081
  return insn | ((value & 0xff) << 12);
1082
}
1083

1084
static long
1085
extract_fxm (unsigned long insn,
1086
	     int dialect ATTRIBUTE_UNUSED,
1087
	     int *invalid)
1088
{
1089
  long mask = (insn >> 12) & 0xff;
1090

1091
  /* Is this a Power4 insn?  */
1092
  if ((insn & (1 << 20)) != 0)
1093
    {
1094
      /* Exactly one bit of MASK should be set.  */
1095
      if (mask == 0 || (mask & -mask) != mask)
1096
	*invalid = 1;
1097
    }
1098

1099
  /* Check that non-power4 form of mfcr has a zero MASK.  */
1100
  else if ((insn & (0x3ff << 1)) == 19 << 1)
1101
    {
1102
      if (mask != 0)
1103
	*invalid = 1;
1104
    }
1105

1106
  return mask;
1107
}
1108

1109
/* The LI field in an I form instruction.  The lower two bits are
1110
   forced to zero.  */
1111

1112
static unsigned long
1113
insert_li (unsigned long insn,
1114
	   long value,
1115
	   int dialect ATTRIBUTE_UNUSED,
1116
	   const char **errmsg)
1117
{
1118
  if ((value & 3) != 0)
1119
    *errmsg = _("ignoring least significant bits in branch offset");
1120
  return insn | (value & 0x3fffffc);
1121
}
1122

1123
static long
1124
extract_li (unsigned long insn,
1125
	    int dialect ATTRIBUTE_UNUSED,
1126
	    int *invalid ATTRIBUTE_UNUSED)
1127
{
1128
  return ((insn & 0x3fffffc) ^ 0x2000000) - 0x2000000;
1129
}
1130

1131
/* The MB and ME fields in an M form instruction expressed as a single
1132
   operand which is itself a bitmask.  The extraction function always
1133
   marks it as invalid, since we never want to recognize an
1134
   instruction which uses a field of this type.  */
1135

1136
static unsigned long
1137
insert_mbe (unsigned long insn,
1138
	    long value,
1139
	    int dialect ATTRIBUTE_UNUSED,
1140
	    const char **errmsg)
1141
{
1142
  unsigned long uval, mask;
1143
  int mb, me, mx, count, last;
1144

1145
  uval = value;
1146

1147
  if (uval == 0)
1148
    {
1149
      *errmsg = _("illegal bitmask");
1150
      return insn;
1151
    }
1152

1153
  mb = 0;
1154
  me = 32;
1155
  if ((uval & 1) != 0)
1156
    last = 1;
1157
  else
1158
    last = 0;
1159
  count = 0;
1160

1161
  /* mb: location of last 0->1 transition */
1162
  /* me: location of last 1->0 transition */
1163
  /* count: # transitions */
1164

1165
  for (mx = 0, mask = 1L << 31; mx < 32; ++mx, mask >>= 1)
1166
    {
1167
      if ((uval & mask) && !last)
1168
	{
1169
	  ++count;
1170
	  mb = mx;
1171
	  last = 1;
1172
	}
1173
      else if (!(uval & mask) && last)
1174
	{
1175
	  ++count;
1176
	  me = mx;
1177
	  last = 0;
1178
	}
1179
    }
1180
  if (me == 0)
1181
    me = 32;
1182

1183
  if (count != 2 && (count != 0 || ! last))
1184
    *errmsg = _("illegal bitmask");
1185

1186
  return insn | (mb << 6) | ((me - 1) << 1);
1187
}
1188

1189
static long
1190
extract_mbe (unsigned long insn,
1191
	     int dialect ATTRIBUTE_UNUSED,
1192
	     int *invalid)
1193
{
1194
  long ret;
1195
  int mb, me;
1196
  int i;
1197

1198
  *invalid = 1;
1199

1200
  mb = (insn >> 6) & 0x1f;
1201
  me = (insn >> 1) & 0x1f;
1202
  if (mb < me + 1)
1203
    {
1204
      ret = 0;
1205
      for (i = mb; i <= me; i++)
1206
	ret |= 1L << (31 - i);
1207
    }
1208
  else if (mb == me + 1)
1209
    ret = ~0;
1210
  else /* (mb > me + 1) */
1211
    {
1212
      ret = ~0;
1213
      for (i = me + 1; i < mb; i++)
1214
	ret &= ~(1L << (31 - i));
1215
    }
1216
  return ret;
1217
}
1218

1219
/* The MB or ME field in an MD or MDS form instruction.  The high bit
1220
   is wrapped to the low end.  */
1221

1222
static unsigned long
1223
insert_mb6 (unsigned long insn,
1224
	    long value,
1225
	    int dialect ATTRIBUTE_UNUSED,
1226
	    const char **errmsg ATTRIBUTE_UNUSED)
1227
{
1228
  return insn | ((value & 0x1f) << 6) | (value & 0x20);
1229
}
1230

1231
static long
1232
extract_mb6 (unsigned long insn,
1233
	     int dialect ATTRIBUTE_UNUSED,
1234
	     int *invalid ATTRIBUTE_UNUSED)
1235
{
1236
  return ((insn >> 6) & 0x1f) | (insn & 0x20);
1237
}
1238

1239
/* The NB field in an X form instruction.  The value 32 is stored as
1240
   0.  */
1241

1242
static unsigned long
1243
insert_nb (unsigned long insn,
1244
	   long value,
1245
	   int dialect ATTRIBUTE_UNUSED,
1246
	   const char **errmsg)
1247
{
1248
  if (value < 0 || value > 32)
1249
    *errmsg = _("value out of range");
1250
  if (value == 32)
1251
    value = 0;
1252
  return insn | ((value & 0x1f) << 11);
1253
}
1254

1255
static long
1256
extract_nb (unsigned long insn,
1257
	    int dialect ATTRIBUTE_UNUSED,
1258
	    int *invalid ATTRIBUTE_UNUSED)
1259
{
1260
  long ret;
1261

1262
  ret = (insn >> 11) & 0x1f;
1263
  if (ret == 0)
1264
    ret = 32;
1265
  return ret;
1266
}
1267

1268
/* The NSI field in a D form instruction.  This is the same as the SI
1269
   field, only negated.  The extraction function always marks it as
1270
   invalid, since we never want to recognize an instruction which uses
1271
   a field of this type.  */
1272

1273
static unsigned long
1274
insert_nsi (unsigned long insn,
1275
	    long value,
1276
	    int dialect ATTRIBUTE_UNUSED,
1277
	    const char **errmsg ATTRIBUTE_UNUSED)
1278
{
1279
  return insn | (-value & 0xffff);
1280
}
1281

1282
static long
1283
extract_nsi (unsigned long insn,
1284
	     int dialect ATTRIBUTE_UNUSED,
1285
	     int *invalid)
1286
{
1287
  *invalid = 1;
1288
  return -(((insn & 0xffff) ^ 0x8000) - 0x8000);
1289
}
1290

1291
/* The RA field in a D or X form instruction which is an updating
1292
   load, which means that the RA field may not be zero and may not
1293
   equal the RT field.  */
1294

1295
static unsigned long
1296
insert_ral (unsigned long insn,
1297
	    long value,
1298
	    int dialect ATTRIBUTE_UNUSED,
1299
	    const char **errmsg)
1300
{
1301
  if (value == 0
1302
      || (unsigned long) value == ((insn >> 21) & 0x1f))
1303
    *errmsg = "invalid register operand when updating";
1304
  return insn | ((value & 0x1f) << 16);
1305
}
1306

1307
/* The RA field in an lmw instruction, which has special value
1308
   restrictions.  */
1309

1310
static unsigned long
1311
insert_ram (unsigned long insn,
1312
	    long value,
1313
	    int dialect ATTRIBUTE_UNUSED,
1314
	    const char **errmsg)
1315
{
1316
  if ((unsigned long) value >= ((insn >> 21) & 0x1f))
1317
    *errmsg = _("index register in load range");
1318
  return insn | ((value & 0x1f) << 16);
1319
}
1320

1321
/* The RA field in the DQ form lq instruction, which has special
1322
   value restrictions.  */
1323

1324
static unsigned long
1325
insert_raq (unsigned long insn,
1326
	    long value,
1327
	    int dialect ATTRIBUTE_UNUSED,
1328
	    const char **errmsg)
1329
{
1330
  long rtvalue = (insn & RT_MASK) >> 21;
1331

1332
  if (value == rtvalue)
1333
    *errmsg = _("source and target register operands must be different");
1334
  return insn | ((value & 0x1f) << 16);
1335
}
1336

1337
/* The RA field in a D or X form instruction which is an updating
1338
   store or an updating floating point load, which means that the RA
1339
   field may not be zero.  */
1340

1341
static unsigned long
1342
insert_ras (unsigned long insn,
1343
	    long value,
1344
	    int dialect ATTRIBUTE_UNUSED,
1345
	    const char **errmsg)
1346
{
1347
  if (value == 0)
1348
    *errmsg = _("invalid register operand when updating");
1349
  return insn | ((value & 0x1f) << 16);
1350
}
1351

1352
/* The RB field in an X form instruction when it must be the same as
1353
   the RS field in the instruction.  This is used for extended
1354
   mnemonics like mr.  This operand is marked FAKE.  The insertion
1355
   function just copies the BT field into the BA field, and the
1356
   extraction function just checks that the fields are the same.  */
1357

1358
static unsigned long
1359
insert_rbs (unsigned long insn,
1360
	    long value ATTRIBUTE_UNUSED,
1361
	    int dialect ATTRIBUTE_UNUSED,
1362
	    const char **errmsg ATTRIBUTE_UNUSED)
1363
{
1364
  return insn | (((insn >> 21) & 0x1f) << 11);
1365
}
1366

1367
static long
1368
extract_rbs (unsigned long insn,
1369
	     int dialect ATTRIBUTE_UNUSED,
1370
	     int *invalid)
1371
{
1372
  if (((insn >> 21) & 0x1f) != ((insn >> 11) & 0x1f))
1373
    *invalid = 1;
1374
  return 0;
1375
}
1376

1377
/* The RT field of the DQ form lq instruction, which has special
1378
   value restrictions.  */
1379

1380
static unsigned long
1381
insert_rtq (unsigned long insn,
1382
	    long value,
1383
	    int dialect ATTRIBUTE_UNUSED,
1384
	    const char **errmsg)
1385
{
1386
  if ((value & 1) != 0)
1387
    *errmsg = _("target register operand must be even");
1388
  return insn | ((value & 0x1f) << 21);
1389
}
1390

1391
/* The RS field of the DS form stq instruction, which has special
1392
   value restrictions.  */
1393

1394
static unsigned long
1395
insert_rsq (unsigned long insn,
1396
	    long value ATTRIBUTE_UNUSED,
1397
	    int dialect ATTRIBUTE_UNUSED,
1398
	    const char **errmsg)
1399
{
1400
  if ((value & 1) != 0)
1401
    *errmsg = _("source register operand must be even");
1402
  return insn | ((value & 0x1f) << 21);
1403
}
1404

1405
/* The SH field in an MD form instruction.  This is split.  */
1406

1407
static unsigned long
1408
insert_sh6 (unsigned long insn,
1409
	    long value,
1410
	    int dialect ATTRIBUTE_UNUSED,
1411
	    const char **errmsg ATTRIBUTE_UNUSED)
1412
{
1413
  return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4);
1414
}
1415

1416
static long
1417
extract_sh6 (unsigned long insn,
1418
	     int dialect ATTRIBUTE_UNUSED,
1419
	     int *invalid ATTRIBUTE_UNUSED)
1420
{
1421
  return ((insn >> 11) & 0x1f) | ((insn << 4) & 0x20);
1422
}
1423

1424
/* The SPR field in an XFX form instruction.  This is flipped--the
1425
   lower 5 bits are stored in the upper 5 and vice- versa.  */
1426

1427
static unsigned long
1428
insert_spr (unsigned long insn,
1429
	    long value,
1430
	    int dialect ATTRIBUTE_UNUSED,
1431
	    const char **errmsg ATTRIBUTE_UNUSED)
1432
{
1433
  return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
1434
}
1435

1436
static long
1437
extract_spr (unsigned long insn,
1438
	     int dialect ATTRIBUTE_UNUSED,
1439
	     int *invalid ATTRIBUTE_UNUSED)
1440
{
1441
  return ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
1442
}
1443

1444
/* Some dialects have 8 SPRG registers instead of the standard 4.  */
1445

1446
static unsigned long
1447
insert_sprg (unsigned long insn,
1448
	     long value,
1449
	     int dialect,
1450
	     const char **errmsg)
1451
{
1452
  /* This check uses PPC_OPCODE_403 because PPC405 is later defined
1453
     as a synonym.  If ever a 405 specific dialect is added this
1454
     check should use that instead.  */
1455
  if (value > 7
1456
      || (value > 3
1457
	  && (dialect & (PPC_OPCODE_BOOKE | PPC_OPCODE_403)) == 0))
1458
    *errmsg = _("invalid sprg number");
1459

1460
  /* If this is mfsprg4..7 then use spr 260..263 which can be read in
1461
     user mode.  Anything else must use spr 272..279.  */
1462
  if (value <= 3 || (insn & 0x100) != 0)
1463
    value |= 0x10;
1464

1465
  return insn | ((value & 0x17) << 16);
1466
}
1467

1468
static long
1469
extract_sprg (unsigned long insn,
1470
	      int dialect,
1471
	      int *invalid)
1472
{
1473
  unsigned long val = (insn >> 16) & 0x1f;
1474

1475
  /* mfsprg can use 260..263 and 272..279.  mtsprg only uses spr 272..279
1476
     If not BOOKE or 405, then both use only 272..275.  */
1477
  if (val <= 3
1478
      || (val < 0x10 && (insn & 0x100) != 0)
1479
      || (val - 0x10 > 3
1480
	  && (dialect & (PPC_OPCODE_BOOKE | PPC_OPCODE_403)) == 0))
1481
    *invalid = 1;
1482
  return val & 7;
1483
}
1484

1485
/* The TBR field in an XFX instruction.  This is just like SPR, but it
1486
   is optional.  When TBR is omitted, it must be inserted as 268 (the
1487
   magic number of the TB register).  These functions treat 0
1488
   (indicating an omitted optional operand) as 268.  This means that
1489
   ``mftb 4,0'' is not handled correctly.  This does not matter very
1490
   much, since the architecture manual does not define mftb as
1491
   accepting any values other than 268 or 269.  */
1492

1493
#define TB (268)
1494

1495
static unsigned long
1496
insert_tbr (unsigned long insn,
1497
	    long value,
1498
	    int dialect ATTRIBUTE_UNUSED,
1499
	    const char **errmsg ATTRIBUTE_UNUSED)
1500
{
1501
  if (value == 0)
1502
    value = TB;
1503
  return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
1504
}
1505

1506
static long
1507
extract_tbr (unsigned long insn,
1508
	     int dialect ATTRIBUTE_UNUSED,
1509
	     int *invalid ATTRIBUTE_UNUSED)
1510
{
1511
  long ret;
1512

1513
  ret = ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
1514
  if (ret == TB)
1515
    ret = 0;
1516
  return ret;
1517
}
1518

1519
/* Macros used to form opcodes.  */
1520

1521
/* The main opcode.  */
1522
#define OP(x) ((((unsigned long)(x)) & 0x3f) << 26)
1523
#define OP_MASK OP (0x3f)
1524

1525
/* The main opcode combined with a trap code in the TO field of a D
1526
   form instruction.  Used for extended mnemonics for the trap
1527
   instructions.  */
1528
#define OPTO(x,to) (OP (x) | ((((unsigned long)(to)) & 0x1f) << 21))
1529
#define OPTO_MASK (OP_MASK | TO_MASK)
1530

1531
/* The main opcode combined with a comparison size bit in the L field
1532
   of a D form or X form instruction.  Used for extended mnemonics for
1533
   the comparison instructions.  */
1534
#define OPL(x,l) (OP (x) | ((((unsigned long)(l)) & 1) << 21))
1535
#define OPL_MASK OPL (0x3f,1)
1536

1537
/* An A form instruction.  */
1538
#define A(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1) | (((unsigned long)(rc)) & 1))
1539
#define A_MASK A (0x3f, 0x1f, 1)
1540

1541
/* An A_MASK with the FRB field fixed.  */
1542
#define AFRB_MASK (A_MASK | FRB_MASK)
1543

1544
/* An A_MASK with the FRC field fixed.  */
1545
#define AFRC_MASK (A_MASK | FRC_MASK)
1546

1547
/* An A_MASK with the FRA and FRC fields fixed.  */
1548
#define AFRAFRC_MASK (A_MASK | FRA_MASK | FRC_MASK)
1549

1550
/* An AFRAFRC_MASK, but with L bit clear.  */
1551
#define AFRALFRC_MASK (AFRAFRC_MASK & ~((unsigned long) 1 << 16))
1552

1553
/* A B form instruction.  */
1554
#define B(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 1) << 1) | ((lk) & 1))
1555
#define B_MASK B (0x3f, 1, 1)
1556

1557
/* A B form instruction setting the BO field.  */
1558
#define BBO(op, bo, aa, lk) (B ((op), (aa), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
1559
#define BBO_MASK BBO (0x3f, 0x1f, 1, 1)
1560

1561
/* A BBO_MASK with the y bit of the BO field removed.  This permits
1562
   matching a conditional branch regardless of the setting of the y
1563
   bit.  Similarly for the 'at' bits used for power4 branch hints.  */
1564
#define Y_MASK   (((unsigned long) 1) << 21)
1565
#define AT1_MASK (((unsigned long) 3) << 21)
1566
#define AT2_MASK (((unsigned long) 9) << 21)
1567
#define BBOY_MASK  (BBO_MASK &~ Y_MASK)
1568
#define BBOAT_MASK (BBO_MASK &~ AT1_MASK)
1569

1570
/* A B form instruction setting the BO field and the condition bits of
1571
   the BI field.  */
1572
#define BBOCB(op, bo, cb, aa, lk) \
1573
  (BBO ((op), (bo), (aa), (lk)) | ((((unsigned long)(cb)) & 0x3) << 16))
1574
#define BBOCB_MASK BBOCB (0x3f, 0x1f, 0x3, 1, 1)
1575

1576
/* A BBOCB_MASK with the y bit of the BO field removed.  */
1577
#define BBOYCB_MASK (BBOCB_MASK &~ Y_MASK)
1578
#define BBOATCB_MASK (BBOCB_MASK &~ AT1_MASK)
1579
#define BBOAT2CB_MASK (BBOCB_MASK &~ AT2_MASK)
1580

1581
/* A BBOYCB_MASK in which the BI field is fixed.  */
1582
#define BBOYBI_MASK (BBOYCB_MASK | BI_MASK)
1583
#define BBOATBI_MASK (BBOAT2CB_MASK | BI_MASK)
1584

1585
/* An Context form instruction.  */
1586
#define CTX(op, xop)   (OP (op) | (((unsigned long)(xop)) & 0x7))
1587
#define CTX_MASK CTX(0x3f, 0x7)
1588

1589
/* An User Context form instruction.  */
1590
#define UCTX(op, xop)  (OP (op) | (((unsigned long)(xop)) & 0x1f))
1591
#define UCTX_MASK UCTX(0x3f, 0x1f)
1592

1593
/* The main opcode mask with the RA field clear.  */
1594
#define DRA_MASK (OP_MASK | RA_MASK)
1595

1596
/* A DS form instruction.  */
1597
#define DSO(op, xop) (OP (op) | ((xop) & 0x3))
1598
#define DS_MASK DSO (0x3f, 3)
1599

1600
/* A DE form instruction.  */
1601
#define DEO(op, xop) (OP (op) | ((xop) & 0xf))
1602
#define DE_MASK DEO (0x3e, 0xf)
1603

1604
/* An EVSEL form instruction.  */
1605
#define EVSEL(op, xop) (OP (op) | (((unsigned long)(xop)) & 0xff) << 3)
1606
#define EVSEL_MASK EVSEL(0x3f, 0xff)
1607

1608
/* An M form instruction.  */
1609
#define M(op, rc) (OP (op) | ((rc) & 1))
1610
#define M_MASK M (0x3f, 1)
1611

1612
/* An M form instruction with the ME field specified.  */
1613
#define MME(op, me, rc) (M ((op), (rc)) | ((((unsigned long)(me)) & 0x1f) << 1))
1614

1615
/* An M_MASK with the MB and ME fields fixed.  */
1616
#define MMBME_MASK (M_MASK | MB_MASK | ME_MASK)
1617

1618
/* An M_MASK with the SH and ME fields fixed.  */
1619
#define MSHME_MASK (M_MASK | SH_MASK | ME_MASK)
1620

1621
/* An MD form instruction.  */
1622
#define MD(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x7) << 2) | ((rc) & 1))
1623
#define MD_MASK MD (0x3f, 0x7, 1)
1624

1625
/* An MD_MASK with the MB field fixed.  */
1626
#define MDMB_MASK (MD_MASK | MB6_MASK)
1627

1628
/* An MD_MASK with the SH field fixed.  */
1629
#define MDSH_MASK (MD_MASK | SH6_MASK)
1630

1631
/* An MDS form instruction.  */
1632
#define MDS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0xf) << 1) | ((rc) & 1))
1633
#define MDS_MASK MDS (0x3f, 0xf, 1)
1634

1635
/* An MDS_MASK with the MB field fixed.  */
1636
#define MDSMB_MASK (MDS_MASK | MB6_MASK)
1637

1638
/* An SC form instruction.  */
1639
#define SC(op, sa, lk) (OP (op) | ((((unsigned long)(sa)) & 1) << 1) | ((lk) & 1))
1640
#define SC_MASK (OP_MASK | (((unsigned long)0x3ff) << 16) | (((unsigned long)1) << 1) | 1)
1641

1642
/* An VX form instruction.  */
1643
#define VX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff))
1644

1645
/* The mask for an VX form instruction.  */
1646
#define VX_MASK	VX(0x3f, 0x7ff)
1647

1648
/* An VA form instruction.  */
1649
#define VXA(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x03f))
1650

1651
/* The mask for an VA form instruction.  */
1652
#define VXA_MASK VXA(0x3f, 0x3f)
1653

1654
/* An VXR form instruction.  */
1655
#define VXR(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | (((unsigned long)(xop)) & 0x3ff))
1656

1657
/* The mask for a VXR form instruction.  */
1658
#define VXR_MASK VXR(0x3f, 0x3ff, 1)
1659

1660
/* An X form instruction.  */
1661
#define X(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
1662

1663
/* A Z form instruction.  */
1664
#define Z(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1))
1665

1666
/* An X form instruction with the RC bit specified.  */
1667
#define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1))
1668

1669
/* A Z form instruction with the RC bit specified.  */
1670
#define ZRC(op, xop, rc) (Z ((op), (xop)) | ((rc) & 1))
1671

1672
/* The mask for an X form instruction.  */
1673
#define X_MASK XRC (0x3f, 0x3ff, 1)
1674

1675
/* The mask for a Z form instruction.  */
1676
#define Z_MASK ZRC (0x3f, 0x1ff, 1)
1677

1678
/* An X_MASK with the RA field fixed.  */
1679
#define XRA_MASK (X_MASK | RA_MASK)
1680

1681
/* An X_MASK with the RB field fixed.  */
1682
#define XRB_MASK (X_MASK | RB_MASK)
1683

1684
/* An X_MASK with the RT field fixed.  */
1685
#define XRT_MASK (X_MASK | RT_MASK)
1686

1687
/* An XRT_MASK mask with the L bits clear.  */
1688
#define XLRT_MASK (XRT_MASK & ~((unsigned long) 0x3 << 21))
1689

1690
/* An X_MASK with the RA and RB fields fixed.  */
1691
#define XRARB_MASK (X_MASK | RA_MASK | RB_MASK)
1692

1693
/* An XRARB_MASK, but with the L bit clear.  */
1694
#define XRLARB_MASK (XRARB_MASK & ~((unsigned long) 1 << 16))
1695

1696
/* An X_MASK with the RT and RA fields fixed.  */
1697
#define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK)
1698

1699
/* An XRTRA_MASK, but with L bit clear.  */
1700
#define XRTLRA_MASK (XRTRA_MASK & ~((unsigned long) 1 << 21))
1701

1702
/* An X form instruction with the L bit specified.  */
1703
#define XOPL(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 1) << 21))
1704

1705
/* The mask for an X form comparison instruction.  */
1706
#define XCMP_MASK (X_MASK | (((unsigned long)1) << 22))
1707

1708
/* The mask for an X form comparison instruction with the L field
1709
   fixed.  */
1710
#define XCMPL_MASK (XCMP_MASK | (((unsigned long)1) << 21))
1711

1712
/* An X form trap instruction with the TO field specified.  */
1713
#define XTO(op, xop, to) (X ((op), (xop)) | ((((unsigned long)(to)) & 0x1f) << 21))
1714
#define XTO_MASK (X_MASK | TO_MASK)
1715

1716
/* An X form tlb instruction with the SH field specified.  */
1717
#define XTLB(op, xop, sh) (X ((op), (xop)) | ((((unsigned long)(sh)) & 0x1f) << 11))
1718
#define XTLB_MASK (X_MASK | SH_MASK)
1719

1720
/* An X form sync instruction.  */
1721
#define XSYNC(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 3) << 21))
1722

1723
/* An X form sync instruction with everything filled in except the LS field.  */
1724
#define XSYNC_MASK (0xff9fffff)
1725

1726
/* An X_MASK, but with the EH bit clear.  */
1727
#define XEH_MASK (X_MASK & ~((unsigned long )1))
1728

1729
/* An X form AltiVec dss instruction.  */
1730
#define XDSS(op, xop, a) (X ((op), (xop)) | ((((unsigned long)(a)) & 1) << 25))
1731
#define XDSS_MASK XDSS(0x3f, 0x3ff, 1)
1732

1733
/* An XFL form instruction.  */
1734
#define XFL(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1))
1735
#define XFL_MASK (XFL (0x3f, 0x3ff, 1) | (((unsigned long)1) << 25) | (((unsigned long)1) << 16))
1736

1737
/* An X form isel instruction.  */
1738
#define XISEL(op, xop)  (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1))
1739
#define XISEL_MASK      XISEL(0x3f, 0x1f)
1740

1741
/* An XL form instruction with the LK field set to 0.  */
1742
#define XL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
1743

1744
/* An XL form instruction which uses the LK field.  */
1745
#define XLLK(op, xop, lk) (XL ((op), (xop)) | ((lk) & 1))
1746

1747
/* The mask for an XL form instruction.  */
1748
#define XL_MASK XLLK (0x3f, 0x3ff, 1)
1749

1750
/* An XL form instruction which explicitly sets the BO field.  */
1751
#define XLO(op, bo, xop, lk) \
1752
  (XLLK ((op), (xop), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
1753
#define XLO_MASK (XL_MASK | BO_MASK)
1754

1755
/* An XL form instruction which explicitly sets the y bit of the BO
1756
   field.  */
1757
#define XLYLK(op, xop, y, lk) (XLLK ((op), (xop), (lk)) | ((((unsigned long)(y)) & 1) << 21))
1758
#define XLYLK_MASK (XL_MASK | Y_MASK)
1759

1760
/* An XL form instruction which sets the BO field and the condition
1761
   bits of the BI field.  */
1762
#define XLOCB(op, bo, cb, xop, lk) \
1763
  (XLO ((op), (bo), (xop), (lk)) | ((((unsigned long)(cb)) & 3) << 16))
1764
#define XLOCB_MASK XLOCB (0x3f, 0x1f, 0x3, 0x3ff, 1)
1765

1766
/* An XL_MASK or XLYLK_MASK or XLOCB_MASK with the BB field fixed.  */
1767
#define XLBB_MASK (XL_MASK | BB_MASK)
1768
#define XLYBB_MASK (XLYLK_MASK | BB_MASK)
1769
#define XLBOCBBB_MASK (XLOCB_MASK | BB_MASK)
1770

1771
/* A mask for branch instructions using the BH field.  */
1772
#define XLBH_MASK (XL_MASK | (0x1c << 11))
1773

1774
/* An XL_MASK with the BO and BB fields fixed.  */
1775
#define XLBOBB_MASK (XL_MASK | BO_MASK | BB_MASK)
1776

1777
/* An XL_MASK with the BO, BI and BB fields fixed.  */
1778
#define XLBOBIBB_MASK (XL_MASK | BO_MASK | BI_MASK | BB_MASK)
1779

1780
/* An XO form instruction.  */
1781
#define XO(op, xop, oe, rc) \
1782
  (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1) | ((((unsigned long)(oe)) & 1) << 10) | (((unsigned long)(rc)) & 1))
1783
#define XO_MASK XO (0x3f, 0x1ff, 1, 1)
1784

1785
/* An XO_MASK with the RB field fixed.  */
1786
#define XORB_MASK (XO_MASK | RB_MASK)
1787

1788
/* An XS form instruction.  */
1789
#define XS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2) | (((unsigned long)(rc)) & 1))
1790
#define XS_MASK XS (0x3f, 0x1ff, 1)
1791

1792
/* A mask for the FXM version of an XFX form instruction.  */
1793
#define XFXFXM_MASK (X_MASK | (1 << 11) | (1 << 20))
1794

1795
/* An XFX form instruction with the FXM field filled in.  */
1796
#define XFXM(op, xop, fxm, p4) \
1797
  (X ((op), (xop)) | ((((unsigned long)(fxm)) & 0xff) << 12) \
1798
   | ((unsigned long)(p4) << 20))
1799

1800
/* An XFX form instruction with the SPR field filled in.  */
1801
#define XSPR(op, xop, spr) \
1802
  (X ((op), (xop)) | ((((unsigned long)(spr)) & 0x1f) << 16) | ((((unsigned long)(spr)) & 0x3e0) << 6))
1803
#define XSPR_MASK (X_MASK | SPR_MASK)
1804

1805
/* An XFX form instruction with the SPR field filled in except for the
1806
   SPRBAT field.  */
1807
#define XSPRBAT_MASK (XSPR_MASK &~ SPRBAT_MASK)
1808

1809
/* An XFX form instruction with the SPR field filled in except for the
1810
   SPRG field.  */
1811
#define XSPRG_MASK (XSPR_MASK & ~(0x17 << 16))
1812

1813
/* An X form instruction with everything filled in except the E field.  */
1814
#define XE_MASK (0xffff7fff)
1815

1816
/* An X form user context instruction.  */
1817
#define XUC(op, xop)  (OP (op) | (((unsigned long)(xop)) & 0x1f))
1818
#define XUC_MASK      XUC(0x3f, 0x1f)
1819

1820
/* The BO encodings used in extended conditional branch mnemonics.  */
1821
#define BODNZF	(0x0)
1822
#define BODNZFP	(0x1)
1823
#define BODZF	(0x2)
1824
#define BODZFP	(0x3)
1825
#define BODNZT	(0x8)
1826
#define BODNZTP	(0x9)
1827
#define BODZT	(0xa)
1828
#define BODZTP	(0xb)
1829

1830
#define BOF	(0x4)
1831
#define BOFP	(0x5)
1832
#define BOFM4	(0x6)
1833
#define BOFP4	(0x7)
1834
#define BOT	(0xc)
1835
#define BOTP	(0xd)
1836
#define BOTM4	(0xe)
1837
#define BOTP4	(0xf)
1838

1839
#define BODNZ	(0x10)
1840
#define BODNZP	(0x11)
1841
#define BODZ	(0x12)
1842
#define BODZP	(0x13)
1843
#define BODNZM4 (0x18)
1844
#define BODNZP4 (0x19)
1845
#define BODZM4	(0x1a)
1846
#define BODZP4	(0x1b)
1847

1848
#define BOU	(0x14)
1849

1850
/* The BI condition bit encodings used in extended conditional branch
1851
   mnemonics.  */
1852
#define CBLT	(0)
1853
#define CBGT	(1)
1854
#define CBEQ	(2)
1855
#define CBSO	(3)
1856

1857
/* The TO encodings used in extended trap mnemonics.  */
1858
#define TOLGT	(0x1)
1859
#define TOLLT	(0x2)
1860
#define TOEQ	(0x4)
1861
#define TOLGE	(0x5)
1862
#define TOLNL	(0x5)
1863
#define TOLLE	(0x6)
1864
#define TOLNG	(0x6)
1865
#define TOGT	(0x8)
1866
#define TOGE	(0xc)
1867
#define TONL	(0xc)
1868
#define TOLT	(0x10)
1869
#define TOLE	(0x14)
1870
#define TONG	(0x14)
1871
#define TONE	(0x18)
1872
#define TOU	(0x1f)
1873

1874
/* Smaller names for the flags so each entry in the opcodes table will
1875
   fit on a single line.  */
1876
#undef	PPC
1877
#define PPC     PPC_OPCODE_PPC
1878
#define PPCCOM	PPC_OPCODE_PPC | PPC_OPCODE_COMMON
1879
#define NOPOWER4 PPC_OPCODE_NOPOWER4 | PPCCOM
1880
#define POWER4	PPC_OPCODE_POWER4
1881
#define POWER5	PPC_OPCODE_POWER5
1882
#define POWER6	PPC_OPCODE_POWER6
1883
#define CELL	PPC_OPCODE_CELL
1884
#define PPC32   PPC_OPCODE_32 | PPC_OPCODE_PPC
1885
#define PPC64   PPC_OPCODE_64 | PPC_OPCODE_PPC
1886
#define PPC403	PPC_OPCODE_403
1887
#define PPC405	PPC403
1888
#define PPC440	PPC_OPCODE_440
1889
#define PPC750	PPC
1890
#define PPC860	PPC
1891
#define PPCVEC	PPC_OPCODE_ALTIVEC
1892
#define	POWER   PPC_OPCODE_POWER
1893
#define	POWER2	PPC_OPCODE_POWER | PPC_OPCODE_POWER2
1894
#define PPCPWR2	PPC_OPCODE_PPC | PPC_OPCODE_POWER | PPC_OPCODE_POWER2
1895
#define	POWER32	PPC_OPCODE_POWER | PPC_OPCODE_32
1896
#define	COM     PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON
1897
#define	COM32   PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_32
1898
#define	M601    PPC_OPCODE_POWER | PPC_OPCODE_601
1899
#define PWRCOM	PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_COMMON
1900
#define	MFDEC1	PPC_OPCODE_POWER
1901
#define	MFDEC2	PPC_OPCODE_PPC | PPC_OPCODE_601 | PPC_OPCODE_BOOKE
1902
#define BOOKE	PPC_OPCODE_BOOKE
1903
#define BOOKE64	PPC_OPCODE_BOOKE64
1904
#define CLASSIC	PPC_OPCODE_CLASSIC
1905
#define PPCE300 PPC_OPCODE_E300
1906
#define PPCSPE	PPC_OPCODE_SPE
1907
#define PPCISEL	PPC_OPCODE_ISEL
1908
#define PPCEFS	PPC_OPCODE_EFS
1909
#define PPCBRLK	PPC_OPCODE_BRLOCK
1910
#define PPCPMR	PPC_OPCODE_PMR
1911
#define PPCCHLK	PPC_OPCODE_CACHELCK
1912
#define PPCCHLK64	PPC_OPCODE_CACHELCK | PPC_OPCODE_BOOKE64
1913
#define PPCRFMCI	PPC_OPCODE_RFMCI
1914

1915
/* The opcode table.
1916

1917
   The format of the opcode table is:
1918

1919
   NAME	     OPCODE	MASK		FLAGS		{ OPERANDS }
1920

1921
   NAME is the name of the instruction.
1922
   OPCODE is the instruction opcode.
1923
   MASK is the opcode mask; this is used to tell the disassembler
1924
     which bits in the actual opcode must match OPCODE.
1925
   FLAGS are flags indicated what processors support the instruction.
1926
   OPERANDS is the list of operands.
1927

1928
   The disassembler reads the table in order and prints the first
1929
   instruction which matches, so this table is sorted to put more
1930
   specific instructions before more general instructions.  It is also
1931
   sorted by major opcode.  */
1932

1933
const struct powerpc_opcode powerpc_opcodes[] = {
1934
{ "attn",    X(0,256), X_MASK,		POWER4,		{ 0 } },
1935
{ "tdlgti",  OPTO(2,TOLGT), OPTO_MASK,	PPC64,		{ RA, SI } },
1936
{ "tdllti",  OPTO(2,TOLLT), OPTO_MASK,	PPC64,		{ RA, SI } },
1937
{ "tdeqi",   OPTO(2,TOEQ), OPTO_MASK,	PPC64,		{ RA, SI } },
1938
{ "tdlgei",  OPTO(2,TOLGE), OPTO_MASK,	PPC64,		{ RA, SI } },
1939
{ "tdlnli",  OPTO(2,TOLNL), OPTO_MASK,	PPC64,		{ RA, SI } },
1940
{ "tdllei",  OPTO(2,TOLLE), OPTO_MASK,	PPC64,		{ RA, SI } },
1941
{ "tdlngi",  OPTO(2,TOLNG), OPTO_MASK,	PPC64,		{ RA, SI } },
1942
{ "tdgti",   OPTO(2,TOGT), OPTO_MASK,	PPC64,		{ RA, SI } },
1943
{ "tdgei",   OPTO(2,TOGE), OPTO_MASK,	PPC64,		{ RA, SI } },
1944
{ "tdnli",   OPTO(2,TONL), OPTO_MASK,	PPC64,		{ RA, SI } },
1945
{ "tdlti",   OPTO(2,TOLT), OPTO_MASK,	PPC64,		{ RA, SI } },
1946
{ "tdlei",   OPTO(2,TOLE), OPTO_MASK,	PPC64,		{ RA, SI } },
1947
{ "tdngi",   OPTO(2,TONG), OPTO_MASK,	PPC64,		{ RA, SI } },
1948
{ "tdnei",   OPTO(2,TONE), OPTO_MASK,	PPC64,		{ RA, SI } },
1949
{ "tdi",     OP(2),	OP_MASK,	PPC64,		{ TO, RA, SI } },
1950

1951
{ "twlgti",  OPTO(3,TOLGT), OPTO_MASK,	PPCCOM,		{ RA, SI } },
1952
{ "tlgti",   OPTO(3,TOLGT), OPTO_MASK,	PWRCOM,		{ RA, SI } },
1953
{ "twllti",  OPTO(3,TOLLT), OPTO_MASK,	PPCCOM,		{ RA, SI } },
1954
{ "tllti",   OPTO(3,TOLLT), OPTO_MASK,	PWRCOM,		{ RA, SI } },
1955
{ "tweqi",   OPTO(3,TOEQ), OPTO_MASK,	PPCCOM,		{ RA, SI } },
1956
{ "teqi",    OPTO(3,TOEQ), OPTO_MASK,	PWRCOM,		{ RA, SI } },
1957
{ "twlgei",  OPTO(3,TOLGE), OPTO_MASK,	PPCCOM,		{ RA, SI } },
1958
{ "tlgei",   OPTO(3,TOLGE), OPTO_MASK,	PWRCOM,		{ RA, SI } },
1959
{ "twlnli",  OPTO(3,TOLNL), OPTO_MASK,	PPCCOM,		{ RA, SI } },
1960
{ "tlnli",   OPTO(3,TOLNL), OPTO_MASK,	PWRCOM,		{ RA, SI } },
1961
{ "twllei",  OPTO(3,TOLLE), OPTO_MASK,	PPCCOM,		{ RA, SI } },
1962
{ "tllei",   OPTO(3,TOLLE), OPTO_MASK,	PWRCOM,		{ RA, SI } },
1963
{ "twlngi",  OPTO(3,TOLNG), OPTO_MASK,	PPCCOM,		{ RA, SI } },
1964
{ "tlngi",   OPTO(3,TOLNG), OPTO_MASK,	PWRCOM,		{ RA, SI } },
1965
{ "twgti",   OPTO(3,TOGT), OPTO_MASK,	PPCCOM,		{ RA, SI } },
1966
{ "tgti",    OPTO(3,TOGT), OPTO_MASK,	PWRCOM,		{ RA, SI } },
1967
{ "twgei",   OPTO(3,TOGE), OPTO_MASK,	PPCCOM,		{ RA, SI } },
1968
{ "tgei",    OPTO(3,TOGE), OPTO_MASK,	PWRCOM,		{ RA, SI } },
1969
{ "twnli",   OPTO(3,TONL), OPTO_MASK,	PPCCOM,		{ RA, SI } },
1970
{ "tnli",    OPTO(3,TONL), OPTO_MASK,	PWRCOM,		{ RA, SI } },
1971
{ "twlti",   OPTO(3,TOLT), OPTO_MASK,	PPCCOM,		{ RA, SI } },
1972
{ "tlti",    OPTO(3,TOLT), OPTO_MASK,	PWRCOM,		{ RA, SI } },
1973
{ "twlei",   OPTO(3,TOLE), OPTO_MASK,	PPCCOM,		{ RA, SI } },
1974
{ "tlei",    OPTO(3,TOLE), OPTO_MASK,	PWRCOM,		{ RA, SI } },
1975
{ "twngi",   OPTO(3,TONG), OPTO_MASK,	PPCCOM,		{ RA, SI } },
1976
{ "tngi",    OPTO(3,TONG), OPTO_MASK,	PWRCOM,		{ RA, SI } },
1977
{ "twnei",   OPTO(3,TONE), OPTO_MASK,	PPCCOM,		{ RA, SI } },
1978
{ "tnei",    OPTO(3,TONE), OPTO_MASK,	PWRCOM,		{ RA, SI } },
1979
{ "twi",     OP(3),	OP_MASK,	PPCCOM,		{ TO, RA, SI } },
1980
{ "ti",      OP(3),	OP_MASK,	PWRCOM,		{ TO, RA, SI } },
1981

1982
{ "macchw",	XO(4,172,0,0), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
1983
{ "macchw.",	XO(4,172,0,1), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
1984
{ "macchwo",	XO(4,172,1,0), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
1985
{ "macchwo.",	XO(4,172,1,1), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
1986
{ "macchws",	XO(4,236,0,0), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
1987
{ "macchws.",	XO(4,236,0,1), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
1988
{ "macchwso",	XO(4,236,1,0), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
1989
{ "macchwso.",	XO(4,236,1,1), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
1990
{ "macchwsu",	XO(4,204,0,0), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
1991
{ "macchwsu.",	XO(4,204,0,1), XO_MASK, PPC405|PPC440,	{ RT, RA, RB } },
1992
{ "macchwsuo",	XO(4,204,1,0), XO_MASK, PPC405|PPC440,	{ RT, RA, RB } },
1993
{ "macchwsuo.",	XO(4,204,1,1), XO_MASK, PPC405|PPC440,	{ RT, RA, RB } },
1994
{ "macchwu",	XO(4,140,0,0), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
1995
{ "macchwu.",	XO(4,140,0,1), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
1996
{ "macchwuo",	XO(4,140,1,0), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
1997
{ "macchwuo.",	XO(4,140,1,1), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
1998
{ "machhw",	XO(4,44,0,0),  XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
1999
{ "machhw.",	XO(4,44,0,1),  XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2000
{ "machhwo",	XO(4,44,1,0),  XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2001
{ "machhwo.",	XO(4,44,1,1),  XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2002
{ "machhws",	XO(4,108,0,0), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2003
{ "machhws.",	XO(4,108,0,1), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2004
{ "machhwso",	XO(4,108,1,0), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2005
{ "machhwso.",	XO(4,108,1,1), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2006
{ "machhwsu",	XO(4,76,0,0),  XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2007
{ "machhwsu.",	XO(4,76,0,1),  XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2008
{ "machhwsuo",	XO(4,76,1,0),  XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2009
{ "machhwsuo.",	XO(4,76,1,1),  XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2010
{ "machhwu",	XO(4,12,0,0),  XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2011
{ "machhwu.",	XO(4,12,0,1),  XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2012
{ "machhwuo",	XO(4,12,1,0),  XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2013
{ "machhwuo.",	XO(4,12,1,1),  XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2014
{ "maclhw",	XO(4,428,0,0), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2015
{ "maclhw.",	XO(4,428,0,1), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2016
{ "maclhwo",	XO(4,428,1,0), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2017
{ "maclhwo.",	XO(4,428,1,1), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2018
{ "maclhws",	XO(4,492,0,0), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2019
{ "maclhws.",	XO(4,492,0,1), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2020
{ "maclhwso",	XO(4,492,1,0), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2021
{ "maclhwso.",	XO(4,492,1,1), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2022
{ "maclhwsu",	XO(4,460,0,0), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2023
{ "maclhwsu.",	XO(4,460,0,1), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2024
{ "maclhwsuo",	XO(4,460,1,0), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2025
{ "maclhwsuo.",	XO(4,460,1,1), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2026
{ "maclhwu",	XO(4,396,0,0), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2027
{ "maclhwu.",	XO(4,396,0,1), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2028
{ "maclhwuo",	XO(4,396,1,0), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2029
{ "maclhwuo.",	XO(4,396,1,1), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2030
{ "mulchw",	XRC(4,168,0),  X_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2031
{ "mulchw.",	XRC(4,168,1),  X_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2032
{ "mulchwu",	XRC(4,136,0),  X_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2033
{ "mulchwu.",	XRC(4,136,1),  X_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2034
{ "mulhhw",	XRC(4,40,0),   X_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2035
{ "mulhhw.",	XRC(4,40,1),   X_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2036
{ "mulhhwu",	XRC(4,8,0),    X_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2037
{ "mulhhwu.",	XRC(4,8,1),    X_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2038
{ "mullhw",	XRC(4,424,0),  X_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2039
{ "mullhw.",	XRC(4,424,1),  X_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2040
{ "mullhwu",	XRC(4,392,0),  X_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2041
{ "mullhwu.",	XRC(4,392,1),  X_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2042
{ "nmacchw",	XO(4,174,0,0), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2043
{ "nmacchw.",	XO(4,174,0,1), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2044
{ "nmacchwo",	XO(4,174,1,0), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2045
{ "nmacchwo.",	XO(4,174,1,1), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2046
{ "nmacchws",	XO(4,238,0,0), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2047
{ "nmacchws.",	XO(4,238,0,1), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2048
{ "nmacchwso",	XO(4,238,1,0), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2049
{ "nmacchwso.",	XO(4,238,1,1), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2050
{ "nmachhw",	XO(4,46,0,0),  XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2051
{ "nmachhw.",	XO(4,46,0,1),  XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2052
{ "nmachhwo",	XO(4,46,1,0),  XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2053
{ "nmachhwo.",	XO(4,46,1,1),  XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2054
{ "nmachhws",	XO(4,110,0,0), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2055
{ "nmachhws.",	XO(4,110,0,1), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2056
{ "nmachhwso",	XO(4,110,1,0), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2057
{ "nmachhwso.",	XO(4,110,1,1), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2058
{ "nmaclhw",	XO(4,430,0,0), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2059
{ "nmaclhw.",	XO(4,430,0,1), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2060
{ "nmaclhwo",	XO(4,430,1,0), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2061
{ "nmaclhwo.",	XO(4,430,1,1), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2062
{ "nmaclhws",	XO(4,494,0,0), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2063
{ "nmaclhws.",	XO(4,494,0,1), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2064
{ "nmaclhwso",	XO(4,494,1,0), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2065
{ "nmaclhwso.",	XO(4,494,1,1), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2066
{ "mfvscr",  VX(4, 1540), VX_MASK,	PPCVEC,		{ VD } },
2067
{ "mtvscr",  VX(4, 1604), VX_MASK,	PPCVEC,		{ VB } },
2068

2069
  /* Double-precision opcodes.  */
2070
  /* Some of these conflict with AltiVec, so move them before, since
2071
     PPCVEC includes the PPC_OPCODE_PPC set.  */
2072
{ "efscfd",   VX(4, 719), VX_MASK,	PPCEFS,		{ RS, RB } },
2073
{ "efdabs",   VX(4, 740), VX_MASK,	PPCEFS,		{ RS, RA } },
2074
{ "efdnabs",  VX(4, 741), VX_MASK,	PPCEFS,		{ RS, RA } },
2075
{ "efdneg",   VX(4, 742), VX_MASK,	PPCEFS,		{ RS, RA } },
2076
{ "efdadd",   VX(4, 736), VX_MASK,	PPCEFS,		{ RS, RA, RB } },
2077
{ "efdsub",   VX(4, 737), VX_MASK,	PPCEFS,		{ RS, RA, RB } },
2078
{ "efdmul",   VX(4, 744), VX_MASK,	PPCEFS,		{ RS, RA, RB } },
2079
{ "efddiv",   VX(4, 745), VX_MASK,	PPCEFS,		{ RS, RA, RB } },
2080
{ "efdcmpgt", VX(4, 748), VX_MASK,	PPCEFS,		{ CRFD, RA, RB } },
2081
{ "efdcmplt", VX(4, 749), VX_MASK,	PPCEFS,		{ CRFD, RA, RB } },
2082
{ "efdcmpeq", VX(4, 750), VX_MASK,	PPCEFS,		{ CRFD, RA, RB } },
2083
{ "efdtstgt", VX(4, 764), VX_MASK,	PPCEFS,		{ CRFD, RA, RB } },
2084
{ "efdtstlt", VX(4, 765), VX_MASK,	PPCEFS,		{ CRFD, RA, RB } },
2085
{ "efdtsteq", VX(4, 766), VX_MASK,	PPCEFS,		{ CRFD, RA, RB } },
2086
{ "efdcfsi",  VX(4, 753), VX_MASK,	PPCEFS,		{ RS, RB } },
2087
{ "efdcfsid", VX(4, 739), VX_MASK,	PPCEFS,		{ RS, RB } },
2088
{ "efdcfui",  VX(4, 752), VX_MASK,	PPCEFS,		{ RS, RB } },
2089
{ "efdcfuid", VX(4, 738), VX_MASK,	PPCEFS,		{ RS, RB } },
2090
{ "efdcfsf",  VX(4, 755), VX_MASK,	PPCEFS,		{ RS, RB } },
2091
{ "efdcfuf",  VX(4, 754), VX_MASK,	PPCEFS,		{ RS, RB } },
2092
{ "efdctsi",  VX(4, 757), VX_MASK,	PPCEFS,		{ RS, RB } },
2093
{ "efdctsidz",VX(4, 747), VX_MASK,	PPCEFS,		{ RS, RB } },
2094
{ "efdctsiz", VX(4, 762), VX_MASK,	PPCEFS,		{ RS, RB } },
2095
{ "efdctui",  VX(4, 756), VX_MASK,	PPCEFS,		{ RS, RB } },
2096
{ "efdctuidz",VX(4, 746), VX_MASK,	PPCEFS,		{ RS, RB } },
2097
{ "efdctuiz", VX(4, 760), VX_MASK,	PPCEFS,		{ RS, RB } },
2098
{ "efdctsf",  VX(4, 759), VX_MASK,	PPCEFS,		{ RS, RB } },
2099
{ "efdctuf",  VX(4, 758), VX_MASK,	PPCEFS,		{ RS, RB } },
2100
{ "efdcfs",   VX(4, 751), VX_MASK,	PPCEFS,		{ RS, RB } },
2101
  /* End of double-precision opcodes.  */
2102

2103
{ "vaddcuw", VX(4,  384), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2104
{ "vaddfp",  VX(4,   10), VX_MASK, 	PPCVEC,		{ VD, VA, VB } },
2105
{ "vaddsbs", VX(4,  768), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2106
{ "vaddshs", VX(4,  832), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2107
{ "vaddsws", VX(4,  896), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2108
{ "vaddubm", VX(4,    0), VX_MASK, 	PPCVEC,		{ VD, VA, VB } },
2109
{ "vaddubs", VX(4,  512), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2110
{ "vadduhm", VX(4,   64), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2111
{ "vadduhs", VX(4,  576), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2112
{ "vadduwm", VX(4,  128), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2113
{ "vadduws", VX(4,  640), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2114
{ "vand",    VX(4, 1028), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2115
{ "vandc",   VX(4, 1092), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2116
{ "vavgsb",  VX(4, 1282), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2117
{ "vavgsh",  VX(4, 1346), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2118
{ "vavgsw",  VX(4, 1410), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2119
{ "vavgub",  VX(4, 1026), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2120
{ "vavguh",  VX(4, 1090), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2121
{ "vavguw",  VX(4, 1154), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2122
{ "vcfsx",   VX(4,  842), VX_MASK,	PPCVEC,		{ VD, VB, UIMM } },
2123
{ "vcfux",   VX(4,  778), VX_MASK,	PPCVEC,		{ VD, VB, UIMM } },
2124
{ "vcmpbfp",   VXR(4, 966, 0), VXR_MASK, PPCVEC,	{ VD, VA, VB } },
2125
{ "vcmpbfp.",  VXR(4, 966, 1), VXR_MASK, PPCVEC,	{ VD, VA, VB } },
2126
{ "vcmpeqfp",  VXR(4, 198, 0), VXR_MASK, PPCVEC,	{ VD, VA, VB } },
2127
{ "vcmpeqfp.", VXR(4, 198, 1), VXR_MASK, PPCVEC,	{ VD, VA, VB } },
2128
{ "vcmpequb",  VXR(4,   6, 0), VXR_MASK, PPCVEC,	{ VD, VA, VB } },
2129
{ "vcmpequb.", VXR(4,   6, 1), VXR_MASK, PPCVEC,	{ VD, VA, VB } },
2130
{ "vcmpequh",  VXR(4,  70, 0), VXR_MASK, PPCVEC,	{ VD, VA, VB } },
2131
{ "vcmpequh.", VXR(4,  70, 1), VXR_MASK, PPCVEC,	{ VD, VA, VB } },
2132
{ "vcmpequw",  VXR(4, 134, 0), VXR_MASK, PPCVEC,	{ VD, VA, VB } },
2133
{ "vcmpequw.", VXR(4, 134, 1), VXR_MASK, PPCVEC,	{ VD, VA, VB } },
2134
{ "vcmpgefp",  VXR(4, 454, 0), VXR_MASK, PPCVEC,	{ VD, VA, VB } },
2135
{ "vcmpgefp.", VXR(4, 454, 1), VXR_MASK, PPCVEC,	{ VD, VA, VB } },
2136
{ "vcmpgtfp",  VXR(4, 710, 0), VXR_MASK, PPCVEC,	{ VD, VA, VB } },
2137
{ "vcmpgtfp.", VXR(4, 710, 1), VXR_MASK, PPCVEC,	{ VD, VA, VB } },
2138
{ "vcmpgtsb",  VXR(4, 774, 0), VXR_MASK, PPCVEC,	{ VD, VA, VB } },
2139
{ "vcmpgtsb.", VXR(4, 774, 1), VXR_MASK, PPCVEC,	{ VD, VA, VB } },
2140
{ "vcmpgtsh",  VXR(4, 838, 0), VXR_MASK, PPCVEC,	{ VD, VA, VB } },
2141
{ "vcmpgtsh.", VXR(4, 838, 1), VXR_MASK, PPCVEC,	{ VD, VA, VB } },
2142
{ "vcmpgtsw",  VXR(4, 902, 0), VXR_MASK, PPCVEC,	{ VD, VA, VB } },
2143
{ "vcmpgtsw.", VXR(4, 902, 1), VXR_MASK, PPCVEC,	{ VD, VA, VB } },
2144
{ "vcmpgtub",  VXR(4, 518, 0), VXR_MASK, PPCVEC,	{ VD, VA, VB } },
2145
{ "vcmpgtub.", VXR(4, 518, 1), VXR_MASK, PPCVEC,	{ VD, VA, VB } },
2146
{ "vcmpgtuh",  VXR(4, 582, 0), VXR_MASK, PPCVEC,	{ VD, VA, VB } },
2147
{ "vcmpgtuh.", VXR(4, 582, 1), VXR_MASK, PPCVEC,	{ VD, VA, VB } },
2148
{ "vcmpgtuw",  VXR(4, 646, 0), VXR_MASK, PPCVEC,	{ VD, VA, VB } },
2149
{ "vcmpgtuw.", VXR(4, 646, 1), VXR_MASK, PPCVEC,	{ VD, VA, VB } },
2150
{ "vctsxs",    VX(4,  970), VX_MASK,	PPCVEC,		{ VD, VB, UIMM } },
2151
{ "vctuxs",    VX(4,  906), VX_MASK,	PPCVEC,		{ VD, VB, UIMM } },
2152
{ "vexptefp",  VX(4,  394), VX_MASK,	PPCVEC,		{ VD, VB } },
2153
{ "vlogefp",   VX(4,  458), VX_MASK,	PPCVEC,		{ VD, VB } },
2154
{ "vmaddfp",   VXA(4,  46), VXA_MASK,	PPCVEC,		{ VD, VA, VC, VB } },
2155
{ "vmaxfp",    VX(4, 1034), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2156
{ "vmaxsb",    VX(4,  258), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2157
{ "vmaxsh",    VX(4,  322), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2158
{ "vmaxsw",    VX(4,  386), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2159
{ "vmaxub",    VX(4,    2), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2160
{ "vmaxuh",    VX(4,   66), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2161
{ "vmaxuw",    VX(4,  130), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2162
{ "vmhaddshs", VXA(4,  32), VXA_MASK,	PPCVEC,		{ VD, VA, VB, VC } },
2163
{ "vmhraddshs", VXA(4, 33), VXA_MASK,	PPCVEC,		{ VD, VA, VB, VC } },
2164
{ "vminfp",    VX(4, 1098), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2165
{ "vminsb",    VX(4,  770), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2166
{ "vminsh",    VX(4,  834), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2167
{ "vminsw",    VX(4,  898), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2168
{ "vminub",    VX(4,  514), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2169
{ "vminuh",    VX(4,  578), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2170
{ "vminuw",    VX(4,  642), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2171
{ "vmladduhm", VXA(4,  34), VXA_MASK,	PPCVEC,		{ VD, VA, VB, VC } },
2172
{ "vmrghb",    VX(4,   12), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2173
{ "vmrghh",    VX(4,   76), VX_MASK,    PPCVEC,		{ VD, VA, VB } },
2174
{ "vmrghw",    VX(4,  140), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2175
{ "vmrglb",    VX(4,  268), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2176
{ "vmrglh",    VX(4,  332), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2177
{ "vmrglw",    VX(4,  396), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2178
{ "vmsummbm",  VXA(4,  37), VXA_MASK,	PPCVEC,		{ VD, VA, VB, VC } },
2179
{ "vmsumshm",  VXA(4,  40), VXA_MASK,	PPCVEC,		{ VD, VA, VB, VC } },
2180
{ "vmsumshs",  VXA(4,  41), VXA_MASK,	PPCVEC,		{ VD, VA, VB, VC } },
2181
{ "vmsumubm",  VXA(4,  36), VXA_MASK,   PPCVEC,		{ VD, VA, VB, VC } },
2182
{ "vmsumuhm",  VXA(4,  38), VXA_MASK,   PPCVEC,		{ VD, VA, VB, VC } },
2183
{ "vmsumuhs",  VXA(4,  39), VXA_MASK,   PPCVEC,		{ VD, VA, VB, VC } },
2184
{ "vmulesb",   VX(4,  776), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2185
{ "vmulesh",   VX(4,  840), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2186
{ "vmuleub",   VX(4,  520), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2187
{ "vmuleuh",   VX(4,  584), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2188
{ "vmulosb",   VX(4,  264), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2189
{ "vmulosh",   VX(4,  328), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2190
{ "vmuloub",   VX(4,    8), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2191
{ "vmulouh",   VX(4,   72), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2192
{ "vnmsubfp",  VXA(4,  47), VXA_MASK,	PPCVEC,		{ VD, VA, VC, VB } },
2193
{ "vnor",      VX(4, 1284), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2194
{ "vor",       VX(4, 1156), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2195
{ "vperm",     VXA(4,  43), VXA_MASK,	PPCVEC,		{ VD, VA, VB, VC } },
2196
{ "vpkpx",     VX(4,  782), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2197
{ "vpkshss",   VX(4,  398), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2198
{ "vpkshus",   VX(4,  270), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2199
{ "vpkswss",   VX(4,  462), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2200
{ "vpkswus",   VX(4,  334), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2201
{ "vpkuhum",   VX(4,   14), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2202
{ "vpkuhus",   VX(4,  142), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2203
{ "vpkuwum",   VX(4,   78), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2204
{ "vpkuwus",   VX(4,  206), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2205
{ "vrefp",     VX(4,  266), VX_MASK,	PPCVEC,		{ VD, VB } },
2206
{ "vrfim",     VX(4,  714), VX_MASK,	PPCVEC,		{ VD, VB } },
2207
{ "vrfin",     VX(4,  522), VX_MASK,	PPCVEC,		{ VD, VB } },
2208
{ "vrfip",     VX(4,  650), VX_MASK,	PPCVEC,		{ VD, VB } },
2209
{ "vrfiz",     VX(4,  586), VX_MASK,	PPCVEC,		{ VD, VB } },
2210
{ "vrlb",      VX(4,    4), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2211
{ "vrlh",      VX(4,   68), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2212
{ "vrlw",      VX(4,  132), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2213
{ "vrsqrtefp", VX(4,  330), VX_MASK,	PPCVEC,		{ VD, VB } },
2214
{ "vsel",      VXA(4,  42), VXA_MASK,	PPCVEC,		{ VD, VA, VB, VC } },
2215
{ "vsl",       VX(4,  452), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2216
{ "vslb",      VX(4,  260), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2217
{ "vsldoi",    VXA(4,  44), VXA_MASK,	PPCVEC,		{ VD, VA, VB, SHB } },
2218
{ "vslh",      VX(4,  324), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2219
{ "vslo",      VX(4, 1036), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2220
{ "vslw",      VX(4,  388), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2221
{ "vspltb",    VX(4,  524), VX_MASK,	PPCVEC,		{ VD, VB, UIMM } },
2222
{ "vsplth",    VX(4,  588), VX_MASK,	PPCVEC,		{ VD, VB, UIMM } },
2223
{ "vspltisb",  VX(4,  780), VX_MASK,	PPCVEC,		{ VD, SIMM } },
2224
{ "vspltish",  VX(4,  844), VX_MASK,	PPCVEC,		{ VD, SIMM } },
2225
{ "vspltisw",  VX(4,  908), VX_MASK,	PPCVEC,		{ VD, SIMM } },
2226
{ "vspltw",    VX(4,  652), VX_MASK,	PPCVEC,		{ VD, VB, UIMM } },
2227
{ "vsr",       VX(4,  708), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2228
{ "vsrab",     VX(4,  772), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2229
{ "vsrah",     VX(4,  836), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2230
{ "vsraw",     VX(4,  900), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2231
{ "vsrb",      VX(4,  516), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2232
{ "vsrh",      VX(4,  580), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2233
{ "vsro",      VX(4, 1100), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2234
{ "vsrw",      VX(4,  644), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2235
{ "vsubcuw",   VX(4, 1408), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2236
{ "vsubfp",    VX(4,   74), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2237
{ "vsubsbs",   VX(4, 1792), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2238
{ "vsubshs",   VX(4, 1856), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2239
{ "vsubsws",   VX(4, 1920), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2240
{ "vsububm",   VX(4, 1024), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2241
{ "vsububs",   VX(4, 1536), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2242
{ "vsubuhm",   VX(4, 1088), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2243
{ "vsubuhs",   VX(4, 1600), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2244
{ "vsubuwm",   VX(4, 1152), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2245
{ "vsubuws",   VX(4, 1664), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2246
{ "vsumsws",   VX(4, 1928), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2247
{ "vsum2sws",  VX(4, 1672), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2248
{ "vsum4sbs",  VX(4, 1800), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2249
{ "vsum4shs",  VX(4, 1608), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2250
{ "vsum4ubs",  VX(4, 1544), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2251
{ "vupkhpx",   VX(4,  846), VX_MASK,	PPCVEC,		{ VD, VB } },
2252
{ "vupkhsb",   VX(4,  526), VX_MASK,	PPCVEC,		{ VD, VB } },
2253
{ "vupkhsh",   VX(4,  590), VX_MASK,	PPCVEC,		{ VD, VB } },
2254
{ "vupklpx",   VX(4,  974), VX_MASK,	PPCVEC,		{ VD, VB } },
2255
{ "vupklsb",   VX(4,  654), VX_MASK,	PPCVEC,		{ VD, VB } },
2256
{ "vupklsh",   VX(4,  718), VX_MASK,	PPCVEC,		{ VD, VB } },
2257
{ "vxor",      VX(4, 1220), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2258

2259
{ "evaddw",    VX(4, 512), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2260
{ "evaddiw",   VX(4, 514), VX_MASK,	PPCSPE,		{ RS, RB, UIMM } },
2261
{ "evsubfw",   VX(4, 516), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2262
{ "evsubw",    VX(4, 516), VX_MASK,	PPCSPE,		{ RS, RB, RA } },
2263
{ "evsubifw",  VX(4, 518), VX_MASK,	PPCSPE,		{ RS, UIMM, RB } },
2264
{ "evsubiw",   VX(4, 518), VX_MASK,	PPCSPE,		{ RS, RB, UIMM } },
2265
{ "evabs",     VX(4, 520), VX_MASK,	PPCSPE,		{ RS, RA } },
2266
{ "evneg",     VX(4, 521), VX_MASK,	PPCSPE,		{ RS, RA } },
2267
{ "evextsb",   VX(4, 522), VX_MASK,	PPCSPE,		{ RS, RA } },
2268
{ "evextsh",   VX(4, 523), VX_MASK,	PPCSPE,		{ RS, RA } },
2269
{ "evrndw",    VX(4, 524), VX_MASK,	PPCSPE,		{ RS, RA } },
2270
{ "evcntlzw",  VX(4, 525), VX_MASK,	PPCSPE,		{ RS, RA } },
2271
{ "evcntlsw",  VX(4, 526), VX_MASK,	PPCSPE,		{ RS, RA } },
2272

2273
{ "brinc",     VX(4, 527), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2274

2275
{ "evand",     VX(4, 529), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2276
{ "evandc",    VX(4, 530), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2277
{ "evmr",      VX(4, 535), VX_MASK,	PPCSPE,		{ RS, RA, BBA } },
2278
{ "evor",      VX(4, 535), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2279
{ "evorc",     VX(4, 539), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2280
{ "evxor",     VX(4, 534), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2281
{ "eveqv",     VX(4, 537), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2282
{ "evnand",    VX(4, 542), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2283
{ "evnot",     VX(4, 536), VX_MASK,	PPCSPE,		{ RS, RA, BBA } },
2284
{ "evnor",     VX(4, 536), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2285

2286
{ "evrlw",     VX(4, 552), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2287
{ "evrlwi",    VX(4, 554), VX_MASK,	PPCSPE,		{ RS, RA, EVUIMM } },
2288
{ "evslw",     VX(4, 548), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2289
{ "evslwi",    VX(4, 550), VX_MASK,	PPCSPE,		{ RS, RA, EVUIMM } },
2290
{ "evsrws",    VX(4, 545), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2291
{ "evsrwu",    VX(4, 544), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2292
{ "evsrwis",   VX(4, 547), VX_MASK,	PPCSPE,		{ RS, RA, EVUIMM } },
2293
{ "evsrwiu",   VX(4, 546), VX_MASK,	PPCSPE,		{ RS, RA, EVUIMM } },
2294
{ "evsplati",  VX(4, 553), VX_MASK,	PPCSPE,		{ RS, SIMM } },
2295
{ "evsplatfi", VX(4, 555), VX_MASK,	PPCSPE,		{ RS, SIMM } },
2296
{ "evmergehi", VX(4, 556), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2297
{ "evmergelo", VX(4, 557), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2298
{ "evmergehilo",VX(4,558), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2299
{ "evmergelohi",VX(4,559), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2300

2301
{ "evcmpgts",  VX(4, 561), VX_MASK,	PPCSPE,		{ CRFD, RA, RB } },
2302
{ "evcmpgtu",  VX(4, 560), VX_MASK,	PPCSPE,		{ CRFD, RA, RB } },
2303
{ "evcmplts",  VX(4, 563), VX_MASK,	PPCSPE,		{ CRFD, RA, RB } },
2304
{ "evcmpltu",  VX(4, 562), VX_MASK,	PPCSPE,		{ CRFD, RA, RB } },
2305
{ "evcmpeq",   VX(4, 564), VX_MASK,	PPCSPE,		{ CRFD, RA, RB } },
2306
{ "evsel",     EVSEL(4,79),EVSEL_MASK,	PPCSPE,		{ RS, RA, RB, CRFS } },
2307

2308
{ "evldd",     VX(4, 769), VX_MASK,	PPCSPE,		{ RS, EVUIMM_8, RA } },
2309
{ "evlddx",    VX(4, 768), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2310
{ "evldw",     VX(4, 771), VX_MASK,	PPCSPE,		{ RS, EVUIMM_8, RA } },
2311
{ "evldwx",    VX(4, 770), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2312
{ "evldh",     VX(4, 773), VX_MASK,	PPCSPE,		{ RS, EVUIMM_8, RA } },
2313
{ "evldhx",    VX(4, 772), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2314
{ "evlwhe",    VX(4, 785), VX_MASK,	PPCSPE,		{ RS, EVUIMM_4, RA } },
2315
{ "evlwhex",   VX(4, 784), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2316
{ "evlwhou",   VX(4, 789), VX_MASK,	PPCSPE,		{ RS, EVUIMM_4, RA } },
2317
{ "evlwhoux",  VX(4, 788), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2318
{ "evlwhos",   VX(4, 791), VX_MASK,	PPCSPE,		{ RS, EVUIMM_4, RA } },
2319
{ "evlwhosx",  VX(4, 790), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2320
{ "evlwwsplat",VX(4, 793), VX_MASK,	PPCSPE,		{ RS, EVUIMM_4, RA } },
2321
{ "evlwwsplatx",VX(4, 792), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2322
{ "evlwhsplat",VX(4, 797), VX_MASK,	PPCSPE,		{ RS, EVUIMM_4, RA } },
2323
{ "evlwhsplatx",VX(4, 796), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2324
{ "evlhhesplat",VX(4, 777), VX_MASK,	PPCSPE,		{ RS, EVUIMM_2, RA } },
2325
{ "evlhhesplatx",VX(4, 776), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2326
{ "evlhhousplat",VX(4, 781), VX_MASK,	PPCSPE,		{ RS, EVUIMM_2, RA } },
2327
{ "evlhhousplatx",VX(4, 780), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2328
{ "evlhhossplat",VX(4, 783), VX_MASK,	PPCSPE,		{ RS, EVUIMM_2, RA } },
2329
{ "evlhhossplatx",VX(4, 782), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2330

2331
{ "evstdd",    VX(4, 801), VX_MASK,	PPCSPE,		{ RS, EVUIMM_8, RA } },
2332
{ "evstddx",   VX(4, 800), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2333
{ "evstdw",    VX(4, 803), VX_MASK,	PPCSPE,		{ RS, EVUIMM_8, RA } },
2334
{ "evstdwx",   VX(4, 802), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2335
{ "evstdh",    VX(4, 805), VX_MASK,	PPCSPE,		{ RS, EVUIMM_8, RA } },
2336
{ "evstdhx",   VX(4, 804), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2337
{ "evstwwe",   VX(4, 825), VX_MASK,	PPCSPE,		{ RS, EVUIMM_4, RA } },
2338
{ "evstwwex",  VX(4, 824), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2339
{ "evstwwo",   VX(4, 829), VX_MASK,	PPCSPE,		{ RS, EVUIMM_4, RA } },
2340
{ "evstwwox",  VX(4, 828), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2341
{ "evstwhe",   VX(4, 817), VX_MASK,	PPCSPE,		{ RS, EVUIMM_4, RA } },
2342
{ "evstwhex",  VX(4, 816), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2343
{ "evstwho",   VX(4, 821), VX_MASK,	PPCSPE,		{ RS, EVUIMM_4, RA } },
2344
{ "evstwhox",  VX(4, 820), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2345

2346
{ "evfsabs",   VX(4, 644), VX_MASK,	PPCSPE,		{ RS, RA } },
2347
{ "evfsnabs",  VX(4, 645), VX_MASK,	PPCSPE,		{ RS, RA } },
2348
{ "evfsneg",   VX(4, 646), VX_MASK,	PPCSPE,		{ RS, RA } },
2349
{ "evfsadd",   VX(4, 640), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2350
{ "evfssub",   VX(4, 641), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2351
{ "evfsmul",   VX(4, 648), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2352
{ "evfsdiv",   VX(4, 649), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2353
{ "evfscmpgt", VX(4, 652), VX_MASK,	PPCSPE,		{ CRFD, RA, RB } },
2354
{ "evfscmplt", VX(4, 653), VX_MASK,	PPCSPE,		{ CRFD, RA, RB } },
2355
{ "evfscmpeq", VX(4, 654), VX_MASK,	PPCSPE,		{ CRFD, RA, RB } },
2356
{ "evfststgt", VX(4, 668), VX_MASK,	PPCSPE,		{ CRFD, RA, RB } },
2357
{ "evfststlt", VX(4, 669), VX_MASK,	PPCSPE,		{ CRFD, RA, RB } },
2358
{ "evfststeq", VX(4, 670), VX_MASK,	PPCSPE,		{ CRFD, RA, RB } },
2359
{ "evfscfui",  VX(4, 656), VX_MASK,	PPCSPE,		{ RS, RB } },
2360
{ "evfsctuiz", VX(4, 664), VX_MASK,	PPCSPE,		{ RS, RB } },
2361
{ "evfscfsi",  VX(4, 657), VX_MASK,	PPCSPE,		{ RS, RB } },
2362
{ "evfscfuf",  VX(4, 658), VX_MASK,	PPCSPE,		{ RS, RB } },
2363
{ "evfscfsf",  VX(4, 659), VX_MASK,	PPCSPE,		{ RS, RB } },
2364
{ "evfsctui",  VX(4, 660), VX_MASK,	PPCSPE,		{ RS, RB } },
2365
{ "evfsctsi",  VX(4, 661), VX_MASK,	PPCSPE,		{ RS, RB } },
2366
{ "evfsctsiz", VX(4, 666), VX_MASK,	PPCSPE,		{ RS, RB } },
2367
{ "evfsctuf",  VX(4, 662), VX_MASK,	PPCSPE,		{ RS, RB } },
2368
{ "evfsctsf",  VX(4, 663), VX_MASK,	PPCSPE,		{ RS, RB } },
2369

2370
{ "efsabs",   VX(4, 708), VX_MASK,	PPCEFS,		{ RS, RA } },
2371
{ "efsnabs",  VX(4, 709), VX_MASK,	PPCEFS,		{ RS, RA } },
2372
{ "efsneg",   VX(4, 710), VX_MASK,	PPCEFS,		{ RS, RA } },
2373
{ "efsadd",   VX(4, 704), VX_MASK,	PPCEFS,		{ RS, RA, RB } },
2374
{ "efssub",   VX(4, 705), VX_MASK,	PPCEFS,		{ RS, RA, RB } },
2375
{ "efsmul",   VX(4, 712), VX_MASK,	PPCEFS,		{ RS, RA, RB } },
2376
{ "efsdiv",   VX(4, 713), VX_MASK,	PPCEFS,		{ RS, RA, RB } },
2377
{ "efscmpgt", VX(4, 716), VX_MASK,	PPCEFS,		{ CRFD, RA, RB } },
2378
{ "efscmplt", VX(4, 717), VX_MASK,	PPCEFS,		{ CRFD, RA, RB } },
2379
{ "efscmpeq", VX(4, 718), VX_MASK,	PPCEFS,		{ CRFD, RA, RB } },
2380
{ "efststgt", VX(4, 732), VX_MASK,	PPCEFS,		{ CRFD, RA, RB } },
2381
{ "efststlt", VX(4, 733), VX_MASK,	PPCEFS,		{ CRFD, RA, RB } },
2382
{ "efststeq", VX(4, 734), VX_MASK,	PPCEFS,		{ CRFD, RA, RB } },
2383
{ "efscfui",  VX(4, 720), VX_MASK,	PPCEFS,		{ RS, RB } },
2384
{ "efsctuiz", VX(4, 728), VX_MASK,	PPCEFS,		{ RS, RB } },
2385
{ "efscfsi",  VX(4, 721), VX_MASK,	PPCEFS,		{ RS, RB } },
2386
{ "efscfuf",  VX(4, 722), VX_MASK,	PPCEFS,		{ RS, RB } },
2387
{ "efscfsf",  VX(4, 723), VX_MASK,	PPCEFS,		{ RS, RB } },
2388
{ "efsctui",  VX(4, 724), VX_MASK,	PPCEFS,		{ RS, RB } },
2389
{ "efsctsi",  VX(4, 725), VX_MASK,	PPCEFS,		{ RS, RB } },
2390
{ "efsctsiz", VX(4, 730), VX_MASK,	PPCEFS,		{ RS, RB } },
2391
{ "efsctuf",  VX(4, 726), VX_MASK,	PPCEFS,		{ RS, RB } },
2392
{ "efsctsf",  VX(4, 727), VX_MASK,	PPCEFS,		{ RS, RB } },
2393

2394
{ "evmhossf",  VX(4, 1031), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2395
{ "evmhossfa", VX(4, 1063), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2396
{ "evmhosmf",  VX(4, 1039), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2397
{ "evmhosmfa", VX(4, 1071), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2398
{ "evmhosmi",  VX(4, 1037), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2399
{ "evmhosmia", VX(4, 1069), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2400
{ "evmhoumi",  VX(4, 1036), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2401
{ "evmhoumia", VX(4, 1068), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2402
{ "evmhessf",  VX(4, 1027), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2403
{ "evmhessfa", VX(4, 1059), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2404
{ "evmhesmf",  VX(4, 1035), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2405
{ "evmhesmfa", VX(4, 1067), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2406
{ "evmhesmi",  VX(4, 1033), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2407
{ "evmhesmia", VX(4, 1065), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2408
{ "evmheumi",  VX(4, 1032), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2409
{ "evmheumia", VX(4, 1064), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2410

2411
{ "evmhossfaaw",VX(4, 1287), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2412
{ "evmhossiaaw",VX(4, 1285), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2413
{ "evmhosmfaaw",VX(4, 1295), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2414
{ "evmhosmiaaw",VX(4, 1293), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2415
{ "evmhousiaaw",VX(4, 1284), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2416
{ "evmhoumiaaw",VX(4, 1292), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2417
{ "evmhessfaaw",VX(4, 1283), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2418
{ "evmhessiaaw",VX(4, 1281), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2419
{ "evmhesmfaaw",VX(4, 1291), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2420
{ "evmhesmiaaw",VX(4, 1289), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2421
{ "evmheusiaaw",VX(4, 1280), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2422
{ "evmheumiaaw",VX(4, 1288), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2423

2424
{ "evmhossfanw",VX(4, 1415), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2425
{ "evmhossianw",VX(4, 1413), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2426
{ "evmhosmfanw",VX(4, 1423), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2427
{ "evmhosmianw",VX(4, 1421), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2428
{ "evmhousianw",VX(4, 1412), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2429
{ "evmhoumianw",VX(4, 1420), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2430
{ "evmhessfanw",VX(4, 1411), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2431
{ "evmhessianw",VX(4, 1409), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2432
{ "evmhesmfanw",VX(4, 1419), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2433
{ "evmhesmianw",VX(4, 1417), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2434
{ "evmheusianw",VX(4, 1408), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2435
{ "evmheumianw",VX(4, 1416), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2436

2437
{ "evmhogsmfaa",VX(4, 1327), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2438
{ "evmhogsmiaa",VX(4, 1325), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2439
{ "evmhogumiaa",VX(4, 1324), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2440
{ "evmhegsmfaa",VX(4, 1323), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2441
{ "evmhegsmiaa",VX(4, 1321), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2442
{ "evmhegumiaa",VX(4, 1320), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2443

2444
{ "evmhogsmfan",VX(4, 1455), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2445
{ "evmhogsmian",VX(4, 1453), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2446
{ "evmhogumian",VX(4, 1452), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2447
{ "evmhegsmfan",VX(4, 1451), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2448
{ "evmhegsmian",VX(4, 1449), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2449
{ "evmhegumian",VX(4, 1448), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2450

2451
{ "evmwhssf",  VX(4, 1095), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2452
{ "evmwhssfa", VX(4, 1127), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2453
{ "evmwhsmf",  VX(4, 1103), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2454
{ "evmwhsmfa", VX(4, 1135), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2455
{ "evmwhsmi",  VX(4, 1101), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2456
{ "evmwhsmia", VX(4, 1133), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2457
{ "evmwhumi",  VX(4, 1100), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2458
{ "evmwhumia", VX(4, 1132), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2459

2460
{ "evmwlumi",  VX(4, 1096), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2461
{ "evmwlumia", VX(4, 1128), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2462

2463
{ "evmwlssiaaw",VX(4, 1345), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2464
{ "evmwlsmiaaw",VX(4, 1353), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2465
{ "evmwlusiaaw",VX(4, 1344), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2466
{ "evmwlumiaaw",VX(4, 1352), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2467

2468
{ "evmwlssianw",VX(4, 1473), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2469
{ "evmwlsmianw",VX(4, 1481), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2470
{ "evmwlusianw",VX(4, 1472), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2471
{ "evmwlumianw",VX(4, 1480), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2472

2473
{ "evmwssf",   VX(4, 1107), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2474
{ "evmwssfa",  VX(4, 1139), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2475
{ "evmwsmf",   VX(4, 1115), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2476
{ "evmwsmfa",  VX(4, 1147), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2477
{ "evmwsmi",   VX(4, 1113), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2478
{ "evmwsmia",  VX(4, 1145), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2479
{ "evmwumi",   VX(4, 1112), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2480
{ "evmwumia",  VX(4, 1144), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2481

2482
{ "evmwssfaa", VX(4, 1363), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2483
{ "evmwsmfaa", VX(4, 1371), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2484
{ "evmwsmiaa", VX(4, 1369), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2485
{ "evmwumiaa", VX(4, 1368), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2486

2487
{ "evmwssfan", VX(4, 1491), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2488
{ "evmwsmfan", VX(4, 1499), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2489
{ "evmwsmian", VX(4, 1497), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2490
{ "evmwumian", VX(4, 1496), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2491

2492
{ "evaddssiaaw",VX(4, 1217), VX_MASK,	PPCSPE,		{ RS, RA } },
2493
{ "evaddsmiaaw",VX(4, 1225), VX_MASK,	PPCSPE,		{ RS, RA } },
2494
{ "evaddusiaaw",VX(4, 1216), VX_MASK,	PPCSPE,		{ RS, RA } },
2495
{ "evaddumiaaw",VX(4, 1224), VX_MASK,	PPCSPE,		{ RS, RA } },
2496

2497
{ "evsubfssiaaw",VX(4, 1219), VX_MASK,	PPCSPE,		{ RS, RA } },
2498
{ "evsubfsmiaaw",VX(4, 1227), VX_MASK,	PPCSPE,		{ RS, RA } },
2499
{ "evsubfusiaaw",VX(4, 1218), VX_MASK,	PPCSPE,		{ RS, RA } },
2500
{ "evsubfumiaaw",VX(4, 1226), VX_MASK,	PPCSPE,		{ RS, RA } },
2501

2502
{ "evmra",    VX(4, 1220), VX_MASK,	PPCSPE,		{ RS, RA } },
2503

2504
{ "evdivws",  VX(4, 1222), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2505
{ "evdivwu",  VX(4, 1223), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2506

2507
{ "mulli",   OP(7),	OP_MASK,	PPCCOM,		{ RT, RA, SI } },
2508
{ "muli",    OP(7),	OP_MASK,	PWRCOM,		{ RT, RA, SI } },
2509

2510
{ "subfic",  OP(8),	OP_MASK,	PPCCOM,		{ RT, RA, SI } },
2511
{ "sfi",     OP(8),	OP_MASK,	PWRCOM,		{ RT, RA, SI } },
2512

2513
{ "dozi",    OP(9),	OP_MASK,	M601,		{ RT, RA, SI } },
2514

2515
{ "bce",     B(9,0,0),	B_MASK,		BOOKE64,	{ BO, BI, BD } },
2516
{ "bcel",    B(9,0,1),	B_MASK,		BOOKE64,	{ BO, BI, BD } },
2517
{ "bcea",    B(9,1,0),	B_MASK,		BOOKE64,	{ BO, BI, BDA } },
2518
{ "bcela",   B(9,1,1),	B_MASK,		BOOKE64,	{ BO, BI, BDA } },
2519

2520
{ "cmplwi",  OPL(10,0),	OPL_MASK,	PPCCOM,		{ OBF, RA, UI } },
2521
{ "cmpldi",  OPL(10,1), OPL_MASK,	PPC64,		{ OBF, RA, UI } },
2522
{ "cmpli",   OP(10),	OP_MASK,	PPC,		{ BF, L, RA, UI } },
2523
{ "cmpli",   OP(10),	OP_MASK,	PWRCOM,		{ BF, RA, UI } },
2524

2525
{ "cmpwi",   OPL(11,0),	OPL_MASK,	PPCCOM,		{ OBF, RA, SI } },
2526
{ "cmpdi",   OPL(11,1),	OPL_MASK,	PPC64,		{ OBF, RA, SI } },
2527
{ "cmpi",    OP(11),	OP_MASK,	PPC,		{ BF, L, RA, SI } },
2528
{ "cmpi",    OP(11),	OP_MASK,	PWRCOM,		{ BF, RA, SI } },
2529

2530
{ "addic",   OP(12),	OP_MASK,	PPCCOM,		{ RT, RA, SI } },
2531
{ "ai",	     OP(12),	OP_MASK,	PWRCOM,		{ RT, RA, SI } },
2532
{ "subic",   OP(12),	OP_MASK,	PPCCOM,		{ RT, RA, NSI } },
2533

2534
{ "addic.",  OP(13),	OP_MASK,	PPCCOM,		{ RT, RA, SI } },
2535
{ "ai.",     OP(13),	OP_MASK,	PWRCOM,		{ RT, RA, SI } },
2536
{ "subic.",  OP(13),	OP_MASK,	PPCCOM,		{ RT, RA, NSI } },
2537

2538
{ "li",	     OP(14),	DRA_MASK,	PPCCOM,		{ RT, SI } },
2539
{ "lil",     OP(14),	DRA_MASK,	PWRCOM,		{ RT, SI } },
2540
{ "addi",    OP(14),	OP_MASK,	PPCCOM,		{ RT, RA0, SI } },
2541
{ "cal",     OP(14),	OP_MASK,	PWRCOM,		{ RT, D, RA0 } },
2542
{ "subi",    OP(14),	OP_MASK,	PPCCOM,		{ RT, RA0, NSI } },
2543
{ "la",	     OP(14),	OP_MASK,	PPCCOM,		{ RT, D, RA0 } },
2544

2545
{ "lis",     OP(15),	DRA_MASK,	PPCCOM,		{ RT, SISIGNOPT } },
2546
{ "liu",     OP(15),	DRA_MASK,	PWRCOM,		{ RT, SISIGNOPT } },
2547
{ "addis",   OP(15),	OP_MASK,	PPCCOM,		{ RT,RA0,SISIGNOPT } },
2548
{ "cau",     OP(15),	OP_MASK,	PWRCOM,		{ RT,RA0,SISIGNOPT } },
2549
{ "subis",   OP(15),	OP_MASK,	PPCCOM,		{ RT, RA0, NSI } },
2550

2551
{ "bdnz-",   BBO(16,BODNZ,0,0),      BBOATBI_MASK, PPCCOM,	{ BDM } },
2552
{ "bdnz+",   BBO(16,BODNZ,0,0),      BBOATBI_MASK, PPCCOM,	{ BDP } },
2553
{ "bdnz",    BBO(16,BODNZ,0,0),      BBOATBI_MASK, PPCCOM,	{ BD } },
2554
{ "bdn",     BBO(16,BODNZ,0,0),      BBOATBI_MASK, PWRCOM,	{ BD } },
2555
{ "bdnzl-",  BBO(16,BODNZ,0,1),      BBOATBI_MASK, PPCCOM,	{ BDM } },
2556
{ "bdnzl+",  BBO(16,BODNZ,0,1),      BBOATBI_MASK, PPCCOM,	{ BDP } },
2557
{ "bdnzl",   BBO(16,BODNZ,0,1),      BBOATBI_MASK, PPCCOM,	{ BD } },
2558
{ "bdnl",    BBO(16,BODNZ,0,1),      BBOATBI_MASK, PWRCOM,	{ BD } },
2559
{ "bdnza-",  BBO(16,BODNZ,1,0),      BBOATBI_MASK, PPCCOM,	{ BDMA } },
2560
{ "bdnza+",  BBO(16,BODNZ,1,0),      BBOATBI_MASK, PPCCOM,	{ BDPA } },
2561
{ "bdnza",   BBO(16,BODNZ,1,0),      BBOATBI_MASK, PPCCOM,	{ BDA } },
2562
{ "bdna",    BBO(16,BODNZ,1,0),      BBOATBI_MASK, PWRCOM,	{ BDA } },
2563
{ "bdnzla-", BBO(16,BODNZ,1,1),      BBOATBI_MASK, PPCCOM,	{ BDMA } },
2564
{ "bdnzla+", BBO(16,BODNZ,1,1),      BBOATBI_MASK, PPCCOM,	{ BDPA } },
2565
{ "bdnzla",  BBO(16,BODNZ,1,1),      BBOATBI_MASK, PPCCOM,	{ BDA } },
2566
{ "bdnla",   BBO(16,BODNZ,1,1),      BBOATBI_MASK, PWRCOM,	{ BDA } },
2567
{ "bdz-",    BBO(16,BODZ,0,0),       BBOATBI_MASK, PPCCOM,	{ BDM } },
2568
{ "bdz+",    BBO(16,BODZ,0,0),       BBOATBI_MASK, PPCCOM,	{ BDP } },
2569
{ "bdz",     BBO(16,BODZ,0,0),       BBOATBI_MASK, COM,		{ BD } },
2570
{ "bdzl-",   BBO(16,BODZ,0,1),       BBOATBI_MASK, PPCCOM,	{ BDM } },
2571
{ "bdzl+",   BBO(16,BODZ,0,1),       BBOATBI_MASK, PPCCOM,	{ BDP } },
2572
{ "bdzl",    BBO(16,BODZ,0,1),       BBOATBI_MASK, COM,		{ BD } },
2573
{ "bdza-",   BBO(16,BODZ,1,0),       BBOATBI_MASK, PPCCOM,	{ BDMA } },
2574
{ "bdza+",   BBO(16,BODZ,1,0),       BBOATBI_MASK, PPCCOM,	{ BDPA } },
2575
{ "bdza",    BBO(16,BODZ,1,0),       BBOATBI_MASK, COM,		{ BDA } },
2576
{ "bdzla-",  BBO(16,BODZ,1,1),       BBOATBI_MASK, PPCCOM,	{ BDMA } },
2577
{ "bdzla+",  BBO(16,BODZ,1,1),       BBOATBI_MASK, PPCCOM,	{ BDPA } },
2578
{ "bdzla",   BBO(16,BODZ,1,1),       BBOATBI_MASK, COM,		{ BDA } },
2579
{ "blt-",    BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM,	{ CR, BDM } },
2580
{ "blt+",    BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM,	{ CR, BDP } },
2581
{ "blt",     BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, COM,		{ CR, BD } },
2582
{ "bltl-",   BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM,	{ CR, BDM } },
2583
{ "bltl+",   BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM,	{ CR, BDP } },
2584
{ "bltl",    BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, COM,		{ CR, BD } },
2585
{ "blta-",   BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM,	{ CR, BDMA } },
2586
{ "blta+",   BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM,	{ CR, BDPA } },
2587
{ "blta",    BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, COM,		{ CR, BDA } },
2588
{ "bltla-",  BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM,	{ CR, BDMA } },
2589
{ "bltla+",  BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM,	{ CR, BDPA } },
2590
{ "bltla",   BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, COM,		{ CR, BDA } },
2591
{ "bgt-",    BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM,	{ CR, BDM } },
2592
{ "bgt+",    BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM,	{ CR, BDP } },
2593
{ "bgt",     BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, COM,		{ CR, BD } },
2594
{ "bgtl-",   BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM,	{ CR, BDM } },
2595
{ "bgtl+",   BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM,	{ CR, BDP } },
2596
{ "bgtl",    BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, COM,		{ CR, BD } },
2597
{ "bgta-",   BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM,	{ CR, BDMA } },
2598
{ "bgta+",   BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM,	{ CR, BDPA } },
2599
{ "bgta",    BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, COM,		{ CR, BDA } },
2600
{ "bgtla-",  BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM,	{ CR, BDMA } },
2601
{ "bgtla+",  BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM,	{ CR, BDPA } },
2602
{ "bgtla",   BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, COM,		{ CR, BDA } },
2603
{ "beq-",    BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM,	{ CR, BDM } },
2604
{ "beq+",    BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM,	{ CR, BDP } },
2605
{ "beq",     BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, COM,		{ CR, BD } },
2606
{ "beql-",   BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM,	{ CR, BDM } },
2607
{ "beql+",   BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM,	{ CR, BDP } },
2608
{ "beql",    BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, COM,		{ CR, BD } },
2609
{ "beqa-",   BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM,	{ CR, BDMA } },
2610
{ "beqa+",   BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM,	{ CR, BDPA } },
2611
{ "beqa",    BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, COM,		{ CR, BDA } },
2612
{ "beqla-",  BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM,	{ CR, BDMA } },
2613
{ "beqla+",  BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM,	{ CR, BDPA } },
2614
{ "beqla",   BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, COM,		{ CR, BDA } },
2615
{ "bso-",    BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM,	{ CR, BDM } },
2616
{ "bso+",    BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM,	{ CR, BDP } },
2617
{ "bso",     BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, COM,		{ CR, BD } },
2618
{ "bsol-",   BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM,	{ CR, BDM } },
2619
{ "bsol+",   BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM,	{ CR, BDP } },
2620
{ "bsol",    BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, COM,		{ CR, BD } },
2621
{ "bsoa-",   BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM,	{ CR, BDMA } },
2622
{ "bsoa+",   BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM,	{ CR, BDPA } },
2623
{ "bsoa",    BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, COM,		{ CR, BDA } },
2624
{ "bsola-",  BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM,	{ CR, BDMA } },
2625
{ "bsola+",  BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM,	{ CR, BDPA } },
2626
{ "bsola",   BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, COM,		{ CR, BDA } },
2627
{ "bun-",    BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM,	{ CR, BDM } },
2628
{ "bun+",    BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM,	{ CR, BDP } },
2629
{ "bun",     BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM,	{ CR, BD } },
2630
{ "bunl-",   BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM,	{ CR, BDM } },
2631
{ "bunl+",   BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM,	{ CR, BDP } },
2632
{ "bunl",    BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM,	{ CR, BD } },
2633
{ "buna-",   BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM,	{ CR, BDMA } },
2634
{ "buna+",   BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM,	{ CR, BDPA } },
2635
{ "buna",    BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM,	{ CR, BDA } },
2636
{ "bunla-",  BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM,	{ CR, BDMA } },
2637
{ "bunla+",  BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM,	{ CR, BDPA } },
2638
{ "bunla",   BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM,	{ CR, BDA } },
2639
{ "bge-",    BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM,	{ CR, BDM } },
2640
{ "bge+",    BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM,	{ CR, BDP } },
2641
{ "bge",     BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM,		{ CR, BD } },
2642
{ "bgel-",   BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM,	{ CR, BDM } },
2643
{ "bgel+",   BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM,	{ CR, BDP } },
2644
{ "bgel",    BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM,		{ CR, BD } },
2645
{ "bgea-",   BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM,	{ CR, BDMA } },
2646
{ "bgea+",   BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM,	{ CR, BDPA } },
2647
{ "bgea",    BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM,		{ CR, BDA } },
2648
{ "bgela-",  BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM,	{ CR, BDMA } },
2649
{ "bgela+",  BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM,	{ CR, BDPA } },
2650
{ "bgela",   BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM,		{ CR, BDA } },
2651
{ "bnl-",    BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM,	{ CR, BDM } },
2652
{ "bnl+",    BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM,	{ CR, BDP } },
2653
{ "bnl",     BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM,		{ CR, BD } },
2654
{ "bnll-",   BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM,	{ CR, BDM } },
2655
{ "bnll+",   BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM,	{ CR, BDP } },
2656
{ "bnll",    BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM,		{ CR, BD } },
2657
{ "bnla-",   BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM,	{ CR, BDMA } },
2658
{ "bnla+",   BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM,	{ CR, BDPA } },
2659
{ "bnla",    BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM,		{ CR, BDA } },
2660
{ "bnlla-",  BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM,	{ CR, BDMA } },
2661
{ "bnlla+",  BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM,	{ CR, BDPA } },
2662
{ "bnlla",   BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM,		{ CR, BDA } },
2663
{ "ble-",    BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM,	{ CR, BDM } },
2664
{ "ble+",    BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM,	{ CR, BDP } },
2665
{ "ble",     BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM,		{ CR, BD } },
2666
{ "blel-",   BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM,	{ CR, BDM } },
2667
{ "blel+",   BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM,	{ CR, BDP } },
2668
{ "blel",    BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM,		{ CR, BD } },
2669
{ "blea-",   BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM,	{ CR, BDMA } },
2670
{ "blea+",   BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM,	{ CR, BDPA } },
2671
{ "blea",    BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM,		{ CR, BDA } },
2672
{ "blela-",  BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM,	{ CR, BDMA } },
2673
{ "blela+",  BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM,	{ CR, BDPA } },
2674
{ "blela",   BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM,		{ CR, BDA } },
2675
{ "bng-",    BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM,	{ CR, BDM } },
2676
{ "bng+",    BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM,	{ CR, BDP } },
2677
{ "bng",     BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM,		{ CR, BD } },
2678
{ "bngl-",   BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM,	{ CR, BDM } },
2679
{ "bngl+",   BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM,	{ CR, BDP } },
2680
{ "bngl",    BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM,		{ CR, BD } },
2681
{ "bnga-",   BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM,	{ CR, BDMA } },
2682
{ "bnga+",   BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM,	{ CR, BDPA } },
2683
{ "bnga",    BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM,		{ CR, BDA } },
2684
{ "bngla-",  BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM,	{ CR, BDMA } },
2685
{ "bngla+",  BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM,	{ CR, BDPA } },
2686
{ "bngla",   BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM,		{ CR, BDA } },
2687
{ "bne-",    BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM,	{ CR, BDM } },
2688
{ "bne+",    BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM,	{ CR, BDP } },
2689
{ "bne",     BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, COM,		{ CR, BD } },
2690
{ "bnel-",   BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM,	{ CR, BDM } },
2691
{ "bnel+",   BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM,	{ CR, BDP } },
2692
{ "bnel",    BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, COM,		{ CR, BD } },
2693
{ "bnea-",   BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM,	{ CR, BDMA } },
2694
{ "bnea+",   BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM,	{ CR, BDPA } },
2695
{ "bnea",    BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, COM,		{ CR, BDA } },
2696
{ "bnela-",  BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM,	{ CR, BDMA } },
2697
{ "bnela+",  BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM,	{ CR, BDPA } },
2698
{ "bnela",   BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, COM,		{ CR, BDA } },
2699
{ "bns-",    BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM,	{ CR, BDM } },
2700
{ "bns+",    BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM,	{ CR, BDP } },
2701
{ "bns",     BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, COM,		{ CR, BD } },
2702
{ "bnsl-",   BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM,	{ CR, BDM } },
2703
{ "bnsl+",   BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM,	{ CR, BDP } },
2704
{ "bnsl",    BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, COM,		{ CR, BD } },
2705
{ "bnsa-",   BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM,	{ CR, BDMA } },
2706
{ "bnsa+",   BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM,	{ CR, BDPA } },
2707
{ "bnsa",    BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, COM,		{ CR, BDA } },
2708
{ "bnsla-",  BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM,	{ CR, BDMA } },
2709
{ "bnsla+",  BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM,	{ CR, BDPA } },
2710
{ "bnsla",   BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, COM,		{ CR, BDA } },
2711
{ "bnu-",    BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM,	{ CR, BDM } },
2712
{ "bnu+",    BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM,	{ CR, BDP } },
2713
{ "bnu",     BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM,	{ CR, BD } },
2714
{ "bnul-",   BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM,	{ CR, BDM } },
2715
{ "bnul+",   BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM,	{ CR, BDP } },
2716
{ "bnul",    BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM,	{ CR, BD } },
2717
{ "bnua-",   BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM,	{ CR, BDMA } },
2718
{ "bnua+",   BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM,	{ CR, BDPA } },
2719
{ "bnua",    BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM,	{ CR, BDA } },
2720
{ "bnula-",  BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM,	{ CR, BDMA } },
2721
{ "bnula+",  BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM,	{ CR, BDPA } },
2722
{ "bnula",   BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM,	{ CR, BDA } },
2723
{ "bdnzt-",  BBO(16,BODNZT,0,0), BBOY_MASK, NOPOWER4,	{ BI, BDM } },
2724
{ "bdnzt+",  BBO(16,BODNZT,0,0), BBOY_MASK, NOPOWER4,	{ BI, BDP } },
2725
{ "bdnzt",   BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM,	{ BI, BD } },
2726
{ "bdnztl-", BBO(16,BODNZT,0,1), BBOY_MASK, NOPOWER4,	{ BI, BDM } },
2727
{ "bdnztl+", BBO(16,BODNZT,0,1), BBOY_MASK, NOPOWER4,	{ BI, BDP } },
2728
{ "bdnztl",  BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM,	{ BI, BD } },
2729
{ "bdnzta-", BBO(16,BODNZT,1,0), BBOY_MASK, NOPOWER4,	{ BI, BDMA } },
2730
{ "bdnzta+", BBO(16,BODNZT,1,0), BBOY_MASK, NOPOWER4,	{ BI, BDPA } },
2731
{ "bdnzta",  BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM,	{ BI, BDA } },
2732
{ "bdnztla-",BBO(16,BODNZT,1,1), BBOY_MASK, NOPOWER4,	{ BI, BDMA } },
2733
{ "bdnztla+",BBO(16,BODNZT,1,1), BBOY_MASK, NOPOWER4,	{ BI, BDPA } },
2734
{ "bdnztla", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM,	{ BI, BDA } },
2735
{ "bdnzf-",  BBO(16,BODNZF,0,0), BBOY_MASK, NOPOWER4,	{ BI, BDM } },
2736
{ "bdnzf+",  BBO(16,BODNZF,0,0), BBOY_MASK, NOPOWER4,	{ BI, BDP } },
2737
{ "bdnzf",   BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM,	{ BI, BD } },
2738
{ "bdnzfl-", BBO(16,BODNZF,0,1), BBOY_MASK, NOPOWER4,	{ BI, BDM } },
2739
{ "bdnzfl+", BBO(16,BODNZF,0,1), BBOY_MASK, NOPOWER4,	{ BI, BDP } },
2740
{ "bdnzfl",  BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM,	{ BI, BD } },
2741
{ "bdnzfa-", BBO(16,BODNZF,1,0), BBOY_MASK, NOPOWER4,	{ BI, BDMA } },
2742
{ "bdnzfa+", BBO(16,BODNZF,1,0), BBOY_MASK, NOPOWER4,	{ BI, BDPA } },
2743
{ "bdnzfa",  BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM,	{ BI, BDA } },
2744
{ "bdnzfla-",BBO(16,BODNZF,1,1), BBOY_MASK, NOPOWER4,	{ BI, BDMA } },
2745
{ "bdnzfla+",BBO(16,BODNZF,1,1), BBOY_MASK, NOPOWER4,	{ BI, BDPA } },
2746
{ "bdnzfla", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM,	{ BI, BDA } },
2747
{ "bt-",     BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM,	{ BI, BDM } },
2748
{ "bt+",     BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM,	{ BI, BDP } },
2749
{ "bt",	     BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM,	{ BI, BD } },
2750
{ "bbt",     BBO(16,BOT,0,0), BBOAT_MASK, PWRCOM,	{ BI, BD } },
2751
{ "btl-",    BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM,	{ BI, BDM } },
2752
{ "btl+",    BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM,	{ BI, BDP } },
2753
{ "btl",     BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM,	{ BI, BD } },
2754
{ "bbtl",    BBO(16,BOT,0,1), BBOAT_MASK, PWRCOM,	{ BI, BD } },
2755
{ "bta-",    BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM,	{ BI, BDMA } },
2756
{ "bta+",    BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM,	{ BI, BDPA } },
2757
{ "bta",     BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM,	{ BI, BDA } },
2758
{ "bbta",    BBO(16,BOT,1,0), BBOAT_MASK, PWRCOM,	{ BI, BDA } },
2759
{ "btla-",   BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM,	{ BI, BDMA } },
2760
{ "btla+",   BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM,	{ BI, BDPA } },
2761
{ "btla",    BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM,	{ BI, BDA } },
2762
{ "bbtla",   BBO(16,BOT,1,1), BBOAT_MASK, PWRCOM,	{ BI, BDA } },
2763
{ "bf-",     BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM,	{ BI, BDM } },
2764
{ "bf+",     BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM,	{ BI, BDP } },
2765
{ "bf",	     BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM,	{ BI, BD } },
2766
{ "bbf",     BBO(16,BOF,0,0), BBOAT_MASK, PWRCOM,	{ BI, BD } },
2767
{ "bfl-",    BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM,	{ BI, BDM } },
2768
{ "bfl+",    BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM,	{ BI, BDP } },
2769
{ "bfl",     BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM,	{ BI, BD } },
2770
{ "bbfl",    BBO(16,BOF,0,1), BBOAT_MASK, PWRCOM,	{ BI, BD } },
2771
{ "bfa-",    BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM,	{ BI, BDMA } },
2772
{ "bfa+",    BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM,	{ BI, BDPA } },
2773
{ "bfa",     BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM,	{ BI, BDA } },
2774
{ "bbfa",    BBO(16,BOF,1,0), BBOAT_MASK, PWRCOM,	{ BI, BDA } },
2775
{ "bfla-",   BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM,	{ BI, BDMA } },
2776
{ "bfla+",   BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM,	{ BI, BDPA } },
2777
{ "bfla",    BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM,	{ BI, BDA } },
2778
{ "bbfla",   BBO(16,BOF,1,1), BBOAT_MASK, PWRCOM,	{ BI, BDA } },
2779
{ "bdzt-",   BBO(16,BODZT,0,0), BBOY_MASK, NOPOWER4,	{ BI, BDM } },
2780
{ "bdzt+",   BBO(16,BODZT,0,0), BBOY_MASK, NOPOWER4,	{ BI, BDP } },
2781
{ "bdzt",    BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM,	{ BI, BD } },
2782
{ "bdztl-",  BBO(16,BODZT,0,1), BBOY_MASK, NOPOWER4,	{ BI, BDM } },
2783
{ "bdztl+",  BBO(16,BODZT,0,1), BBOY_MASK, NOPOWER4,	{ BI, BDP } },
2784
{ "bdztl",   BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM,	{ BI, BD } },
2785
{ "bdzta-",  BBO(16,BODZT,1,0), BBOY_MASK, NOPOWER4,	{ BI, BDMA } },
2786
{ "bdzta+",  BBO(16,BODZT,1,0), BBOY_MASK, NOPOWER4,	{ BI, BDPA } },
2787
{ "bdzta",   BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM,	{ BI, BDA } },
2788
{ "bdztla-", BBO(16,BODZT,1,1), BBOY_MASK, NOPOWER4,	{ BI, BDMA } },
2789
{ "bdztla+", BBO(16,BODZT,1,1), BBOY_MASK, NOPOWER4,	{ BI, BDPA } },
2790
{ "bdztla",  BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM,	{ BI, BDA } },
2791
{ "bdzf-",   BBO(16,BODZF,0,0), BBOY_MASK, NOPOWER4,	{ BI, BDM } },
2792
{ "bdzf+",   BBO(16,BODZF,0,0), BBOY_MASK, NOPOWER4,	{ BI, BDP } },
2793
{ "bdzf",    BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM,	{ BI, BD } },
2794
{ "bdzfl-",  BBO(16,BODZF,0,1), BBOY_MASK, NOPOWER4,	{ BI, BDM } },
2795
{ "bdzfl+",  BBO(16,BODZF,0,1), BBOY_MASK, NOPOWER4,	{ BI, BDP } },
2796
{ "bdzfl",   BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM,	{ BI, BD } },
2797
{ "bdzfa-",  BBO(16,BODZF,1,0), BBOY_MASK, NOPOWER4,	{ BI, BDMA } },
2798
{ "bdzfa+",  BBO(16,BODZF,1,0), BBOY_MASK, NOPOWER4,	{ BI, BDPA } },
2799
{ "bdzfa",   BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM,	{ BI, BDA } },
2800
{ "bdzfla-", BBO(16,BODZF,1,1), BBOY_MASK, NOPOWER4,	{ BI, BDMA } },
2801
{ "bdzfla+", BBO(16,BODZF,1,1), BBOY_MASK, NOPOWER4,	{ BI, BDPA } },
2802
{ "bdzfla",  BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM,	{ BI, BDA } },
2803
{ "bc-",     B(16,0,0),	B_MASK,		PPCCOM,		{ BOE, BI, BDM } },
2804
{ "bc+",     B(16,0,0),	B_MASK,		PPCCOM,		{ BOE, BI, BDP } },
2805
{ "bc",	     B(16,0,0),	B_MASK,		COM,		{ BO, BI, BD } },
2806
{ "bcl-",    B(16,0,1),	B_MASK,		PPCCOM,		{ BOE, BI, BDM } },
2807
{ "bcl+",    B(16,0,1),	B_MASK,		PPCCOM,		{ BOE, BI, BDP } },
2808
{ "bcl",     B(16,0,1),	B_MASK,		COM,		{ BO, BI, BD } },
2809
{ "bca-",    B(16,1,0),	B_MASK,		PPCCOM,		{ BOE, BI, BDMA } },
2810
{ "bca+",    B(16,1,0),	B_MASK,		PPCCOM,		{ BOE, BI, BDPA } },
2811
{ "bca",     B(16,1,0),	B_MASK,		COM,		{ BO, BI, BDA } },
2812
{ "bcla-",   B(16,1,1),	B_MASK,		PPCCOM,		{ BOE, BI, BDMA } },
2813
{ "bcla+",   B(16,1,1),	B_MASK,		PPCCOM,		{ BOE, BI, BDPA } },
2814
{ "bcla",    B(16,1,1),	B_MASK,		COM,		{ BO, BI, BDA } },
2815

2816
{ "sc",      SC(17,1,0), SC_MASK,	PPC,		{ LEV } },
2817
{ "svc",     SC(17,0,0), SC_MASK,	POWER,		{ SVC_LEV, FL1, FL2 } },
2818
{ "svcl",    SC(17,0,1), SC_MASK,	POWER,		{ SVC_LEV, FL1, FL2 } },
2819
{ "svca",    SC(17,1,0), SC_MASK,	PWRCOM,		{ SV } },
2820
{ "svcla",   SC(17,1,1), SC_MASK,	POWER,		{ SV } },
2821

2822
{ "b",	     B(18,0,0),	B_MASK,		COM,		{ LI } },
2823
{ "bl",      B(18,0,1),	B_MASK,		COM,		{ LI } },
2824
{ "ba",      B(18,1,0),	B_MASK,		COM,		{ LIA } },
2825
{ "bla",     B(18,1,1),	B_MASK,		COM,		{ LIA } },
2826

2827
{ "mcrf",    XL(19,0),	XLBB_MASK|(3 << 21)|(3 << 16), COM,	{ BF, BFA } },
2828

2829
{ "blr",     XLO(19,BOU,16,0), XLBOBIBB_MASK, PPCCOM,	{ 0 } },
2830
{ "br",      XLO(19,BOU,16,0), XLBOBIBB_MASK, PWRCOM,	{ 0 } },
2831
{ "blrl",    XLO(19,BOU,16,1), XLBOBIBB_MASK, PPCCOM,	{ 0 } },
2832
{ "brl",     XLO(19,BOU,16,1), XLBOBIBB_MASK, PWRCOM,	{ 0 } },
2833
{ "bdnzlr",  XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM,	{ 0 } },
2834
{ "bdnzlr-", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, NOPOWER4,	{ 0 } },
2835
{ "bdnzlr-", XLO(19,BODNZM4,16,0), XLBOBIBB_MASK, POWER4,	{ 0 } },
2836
{ "bdnzlr+", XLO(19,BODNZP,16,0), XLBOBIBB_MASK, NOPOWER4,	{ 0 } },
2837
{ "bdnzlr+", XLO(19,BODNZP4,16,0), XLBOBIBB_MASK, POWER4,	{ 0 } },
2838
{ "bdnzlrl", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM,	{ 0 } },
2839
{ "bdnzlrl-",XLO(19,BODNZ,16,1), XLBOBIBB_MASK, NOPOWER4,	{ 0 } },
2840
{ "bdnzlrl-",XLO(19,BODNZM4,16,1), XLBOBIBB_MASK, POWER4,	{ 0 } },
2841
{ "bdnzlrl+",XLO(19,BODNZP,16,1), XLBOBIBB_MASK, NOPOWER4,	{ 0 } },
2842
{ "bdnzlrl+",XLO(19,BODNZP4,16,1), XLBOBIBB_MASK, POWER4,	{ 0 } },
2843
{ "bdzlr",   XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM,	{ 0 } },
2844
{ "bdzlr-",  XLO(19,BODZ,16,0), XLBOBIBB_MASK, NOPOWER4,	{ 0 } },
2845
{ "bdzlr-",  XLO(19,BODZM4,16,0), XLBOBIBB_MASK, POWER4,	{ 0 } },
2846
{ "bdzlr+",  XLO(19,BODZP,16,0), XLBOBIBB_MASK, NOPOWER4,	{ 0 } },
2847
{ "bdzlr+",  XLO(19,BODZP4,16,0), XLBOBIBB_MASK, POWER4,	{ 0 } },
2848
{ "bdzlrl",  XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM,	{ 0 } },
2849
{ "bdzlrl-", XLO(19,BODZ,16,1), XLBOBIBB_MASK, NOPOWER4,	{ 0 } },
2850
{ "bdzlrl-", XLO(19,BODZM4,16,1), XLBOBIBB_MASK, POWER4,	{ 0 } },
2851
{ "bdzlrl+", XLO(19,BODZP,16,1), XLBOBIBB_MASK, NOPOWER4,	{ 0 } },
2852
{ "bdzlrl+", XLO(19,BODZP4,16,1), XLBOBIBB_MASK, POWER4,	{ 0 } },
2853
{ "bltlr",   XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2854
{ "bltlr-",  XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2855
{ "bltlr-",  XLOCB(19,BOTM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2856
{ "bltlr+",  XLOCB(19,BOTP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2857
{ "bltlr+",  XLOCB(19,BOTP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2858
{ "bltr",    XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2859
{ "bltlrl",  XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2860
{ "bltlrl-", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2861
{ "bltlrl-", XLOCB(19,BOTM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2862
{ "bltlrl+", XLOCB(19,BOTP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2863
{ "bltlrl+", XLOCB(19,BOTP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2864
{ "bltrl",   XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2865
{ "bgtlr",   XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2866
{ "bgtlr-",  XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2867
{ "bgtlr-",  XLOCB(19,BOTM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2868
{ "bgtlr+",  XLOCB(19,BOTP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2869
{ "bgtlr+",  XLOCB(19,BOTP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2870
{ "bgtr",    XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2871
{ "bgtlrl",  XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2872
{ "bgtlrl-", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2873
{ "bgtlrl-", XLOCB(19,BOTM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2874
{ "bgtlrl+", XLOCB(19,BOTP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2875
{ "bgtlrl+", XLOCB(19,BOTP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2876
{ "bgtrl",   XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2877
{ "beqlr",   XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2878
{ "beqlr-",  XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2879
{ "beqlr-",  XLOCB(19,BOTM4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2880
{ "beqlr+",  XLOCB(19,BOTP,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2881
{ "beqlr+",  XLOCB(19,BOTP4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2882
{ "beqr",    XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2883
{ "beqlrl",  XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2884
{ "beqlrl-", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2885
{ "beqlrl-", XLOCB(19,BOTM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2886
{ "beqlrl+", XLOCB(19,BOTP,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2887
{ "beqlrl+", XLOCB(19,BOTP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2888
{ "beqrl",   XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2889
{ "bsolr",   XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2890
{ "bsolr-",  XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2891
{ "bsolr-",  XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2892
{ "bsolr+",  XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2893
{ "bsolr+",  XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2894
{ "bsor",    XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2895
{ "bsolrl",  XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2896
{ "bsolrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2897
{ "bsolrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2898
{ "bsolrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2899
{ "bsolrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2900
{ "bsorl",   XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2901
{ "bunlr",   XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2902
{ "bunlr-",  XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2903
{ "bunlr-",  XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2904
{ "bunlr+",  XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2905
{ "bunlr+",  XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2906
{ "bunlrl",  XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2907
{ "bunlrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2908
{ "bunlrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2909
{ "bunlrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2910
{ "bunlrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2911
{ "bgelr",   XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2912
{ "bgelr-",  XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2913
{ "bgelr-",  XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2914
{ "bgelr+",  XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2915
{ "bgelr+",  XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2916
{ "bger",    XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2917
{ "bgelrl",  XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2918
{ "bgelrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2919
{ "bgelrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2920
{ "bgelrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2921
{ "bgelrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2922
{ "bgerl",   XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2923
{ "bnllr",   XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2924
{ "bnllr-",  XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2925
{ "bnllr-",  XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2926
{ "bnllr+",  XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2927
{ "bnllr+",  XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2928
{ "bnlr",    XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2929
{ "bnllrl",  XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2930
{ "bnllrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2931
{ "bnllrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2932
{ "bnllrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2933
{ "bnllrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2934
{ "bnlrl",   XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2935
{ "blelr",   XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2936
{ "blelr-",  XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2937
{ "blelr-",  XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2938
{ "blelr+",  XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2939
{ "blelr+",  XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2940
{ "bler",    XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2941
{ "blelrl",  XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2942
{ "blelrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2943
{ "blelrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2944
{ "blelrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2945
{ "blelrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2946
{ "blerl",   XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2947
{ "bnglr",   XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2948
{ "bnglr-",  XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2949
{ "bnglr-",  XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2950
{ "bnglr+",  XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2951
{ "bnglr+",  XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2952
{ "bngr",    XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2953
{ "bnglrl",  XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2954
{ "bnglrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2955
{ "bnglrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2956
{ "bnglrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2957
{ "bnglrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2958
{ "bngrl",   XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2959
{ "bnelr",   XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2960
{ "bnelr-",  XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2961
{ "bnelr-",  XLOCB(19,BOFM4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2962
{ "bnelr+",  XLOCB(19,BOFP,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2963
{ "bnelr+",  XLOCB(19,BOFP4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2964
{ "bner",    XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2965
{ "bnelrl",  XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2966
{ "bnelrl-", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2967
{ "bnelrl-", XLOCB(19,BOFM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2968
{ "bnelrl+", XLOCB(19,BOFP,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2969
{ "bnelrl+", XLOCB(19,BOFP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2970
{ "bnerl",   XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2971
{ "bnslr",   XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2972
{ "bnslr-",  XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2973
{ "bnslr-",  XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2974
{ "bnslr+",  XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2975
{ "bnslr+",  XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2976
{ "bnsr",    XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2977
{ "bnslrl",  XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2978
{ "bnslrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2979
{ "bnslrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2980
{ "bnslrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2981
{ "bnslrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2982
{ "bnsrl",   XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2983
{ "bnulr",   XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2984
{ "bnulr-",  XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2985
{ "bnulr-",  XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2986
{ "bnulr+",  XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2987
{ "bnulr+",  XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2988
{ "bnulrl",  XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2989
{ "bnulrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2990
{ "bnulrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2991
{ "bnulrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2992
{ "bnulrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2993
{ "btlr",    XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM,	{ BI } },
2994
{ "btlr-",   XLO(19,BOT,16,0), XLBOBB_MASK, NOPOWER4,	{ BI } },
2995
{ "btlr-",   XLO(19,BOTM4,16,0), XLBOBB_MASK, POWER4,	{ BI } },
2996
{ "btlr+",   XLO(19,BOTP,16,0), XLBOBB_MASK, NOPOWER4,	{ BI } },
2997
{ "btlr+",   XLO(19,BOTP4,16,0), XLBOBB_MASK, POWER4,	{ BI } },
2998
{ "bbtr",    XLO(19,BOT,16,0), XLBOBB_MASK, PWRCOM,	{ BI } },
2999
{ "btlrl",   XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM,	{ BI } },
3000
{ "btlrl-",  XLO(19,BOT,16,1), XLBOBB_MASK, NOPOWER4,	{ BI } },
3001
{ "btlrl-",  XLO(19,BOTM4,16,1), XLBOBB_MASK, POWER4,	{ BI } },
3002
{ "btlrl+",  XLO(19,BOTP,16,1), XLBOBB_MASK, NOPOWER4,	{ BI } },
3003
{ "btlrl+",  XLO(19,BOTP4,16,1), XLBOBB_MASK, POWER4,	{ BI } },
3004
{ "bbtrl",   XLO(19,BOT,16,1), XLBOBB_MASK, PWRCOM,	{ BI } },
3005
{ "bflr",    XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM,	{ BI } },
3006
{ "bflr-",   XLO(19,BOF,16,0), XLBOBB_MASK, NOPOWER4,	{ BI } },
3007
{ "bflr-",   XLO(19,BOFM4,16,0), XLBOBB_MASK, POWER4,	{ BI } },
3008
{ "bflr+",   XLO(19,BOFP,16,0), XLBOBB_MASK, NOPOWER4,	{ BI } },
3009
{ "bflr+",   XLO(19,BOFP4,16,0), XLBOBB_MASK, POWER4,	{ BI } },
3010
{ "bbfr",    XLO(19,BOF,16,0), XLBOBB_MASK, PWRCOM,	{ BI } },
3011
{ "bflrl",   XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM,	{ BI } },
3012
{ "bflrl-",  XLO(19,BOF,16,1), XLBOBB_MASK, NOPOWER4,	{ BI } },
3013
{ "bflrl-",  XLO(19,BOFM4,16,1), XLBOBB_MASK, POWER4,	{ BI } },
3014
{ "bflrl+",  XLO(19,BOFP,16,1), XLBOBB_MASK, NOPOWER4,	{ BI } },
3015
{ "bflrl+",  XLO(19,BOFP4,16,1), XLBOBB_MASK, POWER4,	{ BI } },
3016
{ "bbfrl",   XLO(19,BOF,16,1), XLBOBB_MASK, PWRCOM,	{ BI } },
3017
{ "bdnztlr", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM,	{ BI } },
3018
{ "bdnztlr-",XLO(19,BODNZT,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
3019
{ "bdnztlr+",XLO(19,BODNZTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
3020
{ "bdnztlrl",XLO(19,BODNZT,16,1), XLBOBB_MASK, PPCCOM,	{ BI } },
3021
{ "bdnztlrl-",XLO(19,BODNZT,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
3022
{ "bdnztlrl+",XLO(19,BODNZTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
3023
{ "bdnzflr", XLO(19,BODNZF,16,0), XLBOBB_MASK, PPCCOM,	{ BI } },
3024
{ "bdnzflr-",XLO(19,BODNZF,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
3025
{ "bdnzflr+",XLO(19,BODNZFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
3026
{ "bdnzflrl",XLO(19,BODNZF,16,1), XLBOBB_MASK, PPCCOM,	{ BI } },
3027
{ "bdnzflrl-",XLO(19,BODNZF,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
3028
{ "bdnzflrl+",XLO(19,BODNZFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
3029
{ "bdztlr",  XLO(19,BODZT,16,0), XLBOBB_MASK, PPCCOM,	{ BI } },
3030
{ "bdztlr-", XLO(19,BODZT,16,0), XLBOBB_MASK, NOPOWER4,	{ BI } },
3031
{ "bdztlr+", XLO(19,BODZTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
3032
{ "bdztlrl", XLO(19,BODZT,16,1), XLBOBB_MASK, PPCCOM,	{ BI } },
3033
{ "bdztlrl-",XLO(19,BODZT,16,1), XLBOBB_MASK, NOPOWER4,	{ BI } },
3034
{ "bdztlrl+",XLO(19,BODZTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
3035
{ "bdzflr",  XLO(19,BODZF,16,0), XLBOBB_MASK, PPCCOM,	{ BI } },
3036
{ "bdzflr-", XLO(19,BODZF,16,0), XLBOBB_MASK, NOPOWER4,	{ BI } },
3037
{ "bdzflr+", XLO(19,BODZFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
3038
{ "bdzflrl", XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM,	{ BI } },
3039
{ "bdzflrl-",XLO(19,BODZF,16,1), XLBOBB_MASK, NOPOWER4,	{ BI } },
3040
{ "bdzflrl+",XLO(19,BODZFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
3041
{ "bclr+",   XLYLK(19,16,1,0), XLYBB_MASK, PPCCOM,	{ BOE, BI } },
3042
{ "bclrl+",  XLYLK(19,16,1,1), XLYBB_MASK, PPCCOM,	{ BOE, BI } },
3043
{ "bclr-",   XLYLK(19,16,0,0), XLYBB_MASK, PPCCOM,	{ BOE, BI } },
3044
{ "bclrl-",  XLYLK(19,16,0,1), XLYBB_MASK, PPCCOM,	{ BOE, BI } },
3045
{ "bclr",    XLLK(19,16,0), XLBH_MASK,	PPCCOM,		{ BO, BI, BH } },
3046
{ "bclrl",   XLLK(19,16,1), XLBH_MASK,	PPCCOM,		{ BO, BI, BH } },
3047
{ "bcr",     XLLK(19,16,0), XLBB_MASK,	PWRCOM,		{ BO, BI } },
3048
{ "bcrl",    XLLK(19,16,1), XLBB_MASK,	PWRCOM,		{ BO, BI } },
3049
{ "bclre",   XLLK(19,17,0), XLBB_MASK,	BOOKE64,	{ BO, BI } },
3050
{ "bclrel",  XLLK(19,17,1), XLBB_MASK,	BOOKE64,	{ BO, BI } },
3051

3052
{ "rfid",    XL(19,18),	0xffffffff,	PPC64,		{ 0 } },
3053

3054
{ "crnot",   XL(19,33), XL_MASK,	PPCCOM,		{ BT, BA, BBA } },
3055
{ "crnor",   XL(19,33),	XL_MASK,	COM,		{ BT, BA, BB } },
3056
{ "rfmci",    X(19,38), 0xffffffff,	PPCRFMCI,	{ 0 } },
3057

3058
{ "rfi",     XL(19,50),	0xffffffff,	COM,		{ 0 } },
3059
{ "rfci",    XL(19,51),	0xffffffff,	PPC403 | BOOKE,	{ 0 } },
3060

3061
{ "rfsvc",   XL(19,82),	0xffffffff,	POWER,		{ 0 } },
3062

3063
{ "crandc",  XL(19,129), XL_MASK,	COM,		{ BT, BA, BB } },
3064

3065
{ "isync",   XL(19,150), 0xffffffff,	PPCCOM,		{ 0 } },
3066
{ "ics",     XL(19,150), 0xffffffff,	PWRCOM,		{ 0 } },
3067

3068
{ "crclr",   XL(19,193), XL_MASK,	PPCCOM,		{ BT, BAT, BBA } },
3069
{ "crxor",   XL(19,193), XL_MASK,	COM,		{ BT, BA, BB } },
3070

3071
{ "crnand",  XL(19,225), XL_MASK,	COM,		{ BT, BA, BB } },
3072

3073
{ "crand",   XL(19,257), XL_MASK,	COM,		{ BT, BA, BB } },
3074

3075
{ "hrfid",   XL(19,274), 0xffffffff,	POWER5 | CELL,	{ 0 } },
3076

3077
{ "crset",   XL(19,289), XL_MASK,	PPCCOM,		{ BT, BAT, BBA } },
3078
{ "creqv",   XL(19,289), XL_MASK,	COM,		{ BT, BA, BB } },
3079

3080
{ "doze",    XL(19,402), 0xffffffff,	POWER6,		{ 0 } },
3081

3082
{ "crorc",   XL(19,417), XL_MASK,	COM,		{ BT, BA, BB } },
3083

3084
{ "nap",     XL(19,434), 0xffffffff,	POWER6,		{ 0 } },
3085

3086
{ "crmove",  XL(19,449), XL_MASK,	PPCCOM,		{ BT, BA, BBA } },
3087
{ "cror",    XL(19,449), XL_MASK,	COM,		{ BT, BA, BB } },
3088

3089
{ "sleep",   XL(19,466), 0xffffffff,	POWER6,		{ 0 } },
3090
{ "rvwinkle", XL(19,498), 0xffffffff,	POWER6,		{ 0 } },
3091

3092
{ "bctr",    XLO(19,BOU,528,0), XLBOBIBB_MASK, COM,	{ 0 } },
3093
{ "bctrl",   XLO(19,BOU,528,1), XLBOBIBB_MASK, COM,	{ 0 } },
3094
{ "bltctr",  XLOCB(19,BOT,CBLT,528,0),  XLBOCBBB_MASK, PPCCOM,	{ CR } },
3095
{ "bltctr-", XLOCB(19,BOT,CBLT,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
3096
{ "bltctr-", XLOCB(19,BOTM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3097
{ "bltctr+", XLOCB(19,BOTP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3098
{ "bltctr+", XLOCB(19,BOTP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3099
{ "bltctrl", XLOCB(19,BOT,CBLT,528,1),  XLBOCBBB_MASK, PPCCOM,	{ CR } },
3100
{ "bltctrl-",XLOCB(19,BOT,CBLT,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
3101
{ "bltctrl-",XLOCB(19,BOTM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3102
{ "bltctrl+",XLOCB(19,BOTP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3103
{ "bltctrl+",XLOCB(19,BOTP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3104
{ "bgtctr",  XLOCB(19,BOT,CBGT,528,0),  XLBOCBBB_MASK, PPCCOM,	{ CR } },
3105
{ "bgtctr-", XLOCB(19,BOT,CBGT,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
3106
{ "bgtctr-", XLOCB(19,BOTM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3107
{ "bgtctr+", XLOCB(19,BOTP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3108
{ "bgtctr+", XLOCB(19,BOTP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3109
{ "bgtctrl", XLOCB(19,BOT,CBGT,528,1),  XLBOCBBB_MASK, PPCCOM,	{ CR } },
3110
{ "bgtctrl-",XLOCB(19,BOT,CBGT,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
3111
{ "bgtctrl-",XLOCB(19,BOTM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3112
{ "bgtctrl+",XLOCB(19,BOTP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3113
{ "bgtctrl+",XLOCB(19,BOTP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3114
{ "beqctr",  XLOCB(19,BOT,CBEQ,528,0),  XLBOCBBB_MASK, PPCCOM,	{ CR } },
3115
{ "beqctr-", XLOCB(19,BOT,CBEQ,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
3116
{ "beqctr-", XLOCB(19,BOTM4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3117
{ "beqctr+", XLOCB(19,BOTP,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3118
{ "beqctr+", XLOCB(19,BOTP4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3119
{ "beqctrl", XLOCB(19,BOT,CBEQ,528,1),  XLBOCBBB_MASK, PPCCOM,	{ CR } },
3120
{ "beqctrl-",XLOCB(19,BOT,CBEQ,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
3121
{ "beqctrl-",XLOCB(19,BOTM4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3122
{ "beqctrl+",XLOCB(19,BOTP,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3123
{ "beqctrl+",XLOCB(19,BOTP4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3124
{ "bsoctr",  XLOCB(19,BOT,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM,	{ CR } },
3125
{ "bsoctr-", XLOCB(19,BOT,CBSO,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
3126
{ "bsoctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3127
{ "bsoctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3128
{ "bsoctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3129
{ "bsoctrl", XLOCB(19,BOT,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,	{ CR } },
3130
{ "bsoctrl-",XLOCB(19,BOT,CBSO,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
3131
{ "bsoctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3132
{ "bsoctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3133
{ "bsoctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3134
{ "bunctr",  XLOCB(19,BOT,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM,	{ CR } },
3135
{ "bunctr-", XLOCB(19,BOT,CBSO,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
3136
{ "bunctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3137
{ "bunctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3138
{ "bunctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3139
{ "bunctrl", XLOCB(19,BOT,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,	{ CR } },
3140
{ "bunctrl-",XLOCB(19,BOT,CBSO,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
3141
{ "bunctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3142
{ "bunctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3143
{ "bunctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3144
{ "bgectr",  XLOCB(19,BOF,CBLT,528,0),  XLBOCBBB_MASK, PPCCOM,	{ CR } },
3145
{ "bgectr-", XLOCB(19,BOF,CBLT,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
3146
{ "bgectr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3147
{ "bgectr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3148
{ "bgectr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3149
{ "bgectrl", XLOCB(19,BOF,CBLT,528,1),  XLBOCBBB_MASK, PPCCOM,	{ CR } },
3150
{ "bgectrl-",XLOCB(19,BOF,CBLT,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
3151
{ "bgectrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3152
{ "bgectrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3153
{ "bgectrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3154
{ "bnlctr",  XLOCB(19,BOF,CBLT,528,0),  XLBOCBBB_MASK, PPCCOM,	{ CR } },
3155
{ "bnlctr-", XLOCB(19,BOF,CBLT,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
3156
{ "bnlctr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3157
{ "bnlctr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3158
{ "bnlctr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3159
{ "bnlctrl", XLOCB(19,BOF,CBLT,528,1),  XLBOCBBB_MASK, PPCCOM,	{ CR } },
3160
{ "bnlctrl-",XLOCB(19,BOF,CBLT,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
3161
{ "bnlctrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3162
{ "bnlctrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3163
{ "bnlctrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3164
{ "blectr",  XLOCB(19,BOF,CBGT,528,0),  XLBOCBBB_MASK, PPCCOM,	{ CR } },
3165
{ "blectr-", XLOCB(19,BOF,CBGT,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
3166
{ "blectr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3167
{ "blectr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3168
{ "blectr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3169
{ "blectrl", XLOCB(19,BOF,CBGT,528,1),  XLBOCBBB_MASK, PPCCOM,	{ CR } },
3170
{ "blectrl-",XLOCB(19,BOF,CBGT,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
3171
{ "blectrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3172
{ "blectrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3173
{ "blectrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3174
{ "bngctr",  XLOCB(19,BOF,CBGT,528,0),  XLBOCBBB_MASK, PPCCOM,	{ CR } },
3175
{ "bngctr-", XLOCB(19,BOF,CBGT,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
3176
{ "bngctr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3177
{ "bngctr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3178
{ "bngctr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3179
{ "bngctrl", XLOCB(19,BOF,CBGT,528,1),  XLBOCBBB_MASK, PPCCOM,	{ CR } },
3180
{ "bngctrl-",XLOCB(19,BOF,CBGT,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
3181
{ "bngctrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3182
{ "bngctrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3183
{ "bngctrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3184
{ "bnectr",  XLOCB(19,BOF,CBEQ,528,0),  XLBOCBBB_MASK, PPCCOM,	{ CR } },
3185
{ "bnectr-", XLOCB(19,BOF,CBEQ,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
3186
{ "bnectr-", XLOCB(19,BOFM4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3187
{ "bnectr+", XLOCB(19,BOFP,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3188
{ "bnectr+", XLOCB(19,BOFP4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3189
{ "bnectrl", XLOCB(19,BOF,CBEQ,528,1),  XLBOCBBB_MASK, PPCCOM,	{ CR } },
3190
{ "bnectrl-",XLOCB(19,BOF,CBEQ,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
3191
{ "bnectrl-",XLOCB(19,BOFM4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3192
{ "bnectrl+",XLOCB(19,BOFP,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3193
{ "bnectrl+",XLOCB(19,BOFP4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3194
{ "bnsctr",  XLOCB(19,BOF,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM,	{ CR } },
3195
{ "bnsctr-", XLOCB(19,BOF,CBSO,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
3196
{ "bnsctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3197
{ "bnsctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3198
{ "bnsctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3199
{ "bnsctrl", XLOCB(19,BOF,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,	{ CR } },
3200
{ "bnsctrl-",XLOCB(19,BOF,CBSO,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
3201
{ "bnsctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3202
{ "bnsctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3203
{ "bnsctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3204
{ "bnuctr",  XLOCB(19,BOF,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM,	{ CR } },
3205
{ "bnuctr-", XLOCB(19,BOF,CBSO,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
3206
{ "bnuctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3207
{ "bnuctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3208
{ "bnuctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3209
{ "bnuctrl", XLOCB(19,BOF,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,	{ CR } },
3210
{ "bnuctrl-",XLOCB(19,BOF,CBSO,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
3211
{ "bnuctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3212
{ "bnuctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3213
{ "bnuctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3214
{ "btctr",   XLO(19,BOT,528,0),  XLBOBB_MASK, PPCCOM,	{ BI } },
3215
{ "btctr-",  XLO(19,BOT,528,0),  XLBOBB_MASK, NOPOWER4,	{ BI } },
3216
{ "btctr-",  XLO(19,BOTM4,528,0), XLBOBB_MASK, POWER4, { BI } },
3217
{ "btctr+",  XLO(19,BOTP,528,0), XLBOBB_MASK, NOPOWER4,	{ BI } },
3218
{ "btctr+",  XLO(19,BOTP4,528,0), XLBOBB_MASK, POWER4, { BI } },
3219
{ "btctrl",  XLO(19,BOT,528,1),  XLBOBB_MASK, PPCCOM,	{ BI } },
3220
{ "btctrl-", XLO(19,BOT,528,1),  XLBOBB_MASK, NOPOWER4,	{ BI } },
3221
{ "btctrl-", XLO(19,BOTM4,528,1), XLBOBB_MASK, POWER4, { BI } },
3222
{ "btctrl+", XLO(19,BOTP,528,1), XLBOBB_MASK, NOPOWER4,	{ BI } },
3223
{ "btctrl+", XLO(19,BOTP4,528,1), XLBOBB_MASK, POWER4, { BI } },
3224
{ "bfctr",   XLO(19,BOF,528,0),  XLBOBB_MASK, PPCCOM,	{ BI } },
3225
{ "bfctr-",  XLO(19,BOF,528,0),  XLBOBB_MASK, NOPOWER4, { BI } },
3226
{ "bfctr-",  XLO(19,BOFM4,528,0), XLBOBB_MASK, POWER4, { BI } },
3227
{ "bfctr+",  XLO(19,BOFP,528,0), XLBOBB_MASK, NOPOWER4, { BI } },
3228
{ "bfctr+",  XLO(19,BOFP4,528,0), XLBOBB_MASK, POWER4, { BI } },
3229
{ "bfctrl",  XLO(19,BOF,528,1),  XLBOBB_MASK, PPCCOM,	{ BI } },
3230
{ "bfctrl-", XLO(19,BOF,528,1),  XLBOBB_MASK, NOPOWER4, { BI } },
3231
{ "bfctrl-", XLO(19,BOFM4,528,1), XLBOBB_MASK, POWER4, { BI } },
3232
{ "bfctrl+", XLO(19,BOFP,528,1), XLBOBB_MASK, NOPOWER4, { BI } },
3233
{ "bfctrl+", XLO(19,BOFP4,528,1), XLBOBB_MASK, POWER4, { BI } },
3234
{ "bcctr-",  XLYLK(19,528,0,0),  XLYBB_MASK,  PPCCOM,	{ BOE, BI } },
3235
{ "bcctr+",  XLYLK(19,528,1,0),  XLYBB_MASK,  PPCCOM,	{ BOE, BI } },
3236
{ "bcctrl-", XLYLK(19,528,0,1),  XLYBB_MASK,  PPCCOM,	{ BOE, BI } },
3237
{ "bcctrl+", XLYLK(19,528,1,1),  XLYBB_MASK,  PPCCOM,	{ BOE, BI } },
3238
{ "bcctr",   XLLK(19,528,0),     XLBH_MASK,   PPCCOM,	{ BO, BI, BH } },
3239
{ "bcctrl",  XLLK(19,528,1),     XLBH_MASK,   PPCCOM,	{ BO, BI, BH } },
3240
{ "bcc",     XLLK(19,528,0),     XLBB_MASK,   PWRCOM,	{ BO, BI } },
3241
{ "bccl",    XLLK(19,528,1),     XLBB_MASK,   PWRCOM,	{ BO, BI } },
3242
{ "bcctre",  XLLK(19,529,0),     XLYBB_MASK,  BOOKE64,	{ BO, BI } },
3243
{ "bcctrel", XLLK(19,529,1),     XLYBB_MASK,  BOOKE64,	{ BO, BI } },
3244

3245
{ "rlwimi",  M(20,0),	M_MASK,		PPCCOM,		{ RA,RS,SH,MBE,ME } },
3246
{ "rlimi",   M(20,0),	M_MASK,		PWRCOM,		{ RA,RS,SH,MBE,ME } },
3247

3248
{ "rlwimi.", M(20,1),	M_MASK,		PPCCOM,		{ RA,RS,SH,MBE,ME } },
3249
{ "rlimi.",  M(20,1),	M_MASK,		PWRCOM,		{ RA,RS,SH,MBE,ME } },
3250

3251
{ "rotlwi",  MME(21,31,0), MMBME_MASK,	PPCCOM,		{ RA, RS, SH } },
3252
{ "clrlwi",  MME(21,31,0), MSHME_MASK,	PPCCOM,		{ RA, RS, MB } },
3253
{ "rlwinm",  M(21,0),	M_MASK,		PPCCOM,		{ RA,RS,SH,MBE,ME } },
3254
{ "rlinm",   M(21,0),	M_MASK,		PWRCOM,		{ RA,RS,SH,MBE,ME } },
3255
{ "rotlwi.", MME(21,31,1), MMBME_MASK,	PPCCOM,		{ RA,RS,SH } },
3256
{ "clrlwi.", MME(21,31,1), MSHME_MASK,	PPCCOM,		{ RA, RS, MB } },
3257
{ "rlwinm.", M(21,1),	M_MASK,		PPCCOM,		{ RA,RS,SH,MBE,ME } },
3258
{ "rlinm.",  M(21,1),	M_MASK,		PWRCOM,		{ RA,RS,SH,MBE,ME } },
3259

3260
{ "rlmi",    M(22,0),	M_MASK,		M601,		{ RA,RS,RB,MBE,ME } },
3261
{ "rlmi.",   M(22,1),	M_MASK,		M601,		{ RA,RS,RB,MBE,ME } },
3262

3263
{ "be",	     B(22,0,0),	B_MASK,		BOOKE64,	{ LI } },
3264
{ "bel",     B(22,0,1),	B_MASK,		BOOKE64,	{ LI } },
3265
{ "bea",     B(22,1,0),	B_MASK,		BOOKE64,	{ LIA } },
3266
{ "bela",    B(22,1,1),	B_MASK,		BOOKE64,	{ LIA } },
3267

3268
{ "rotlw",   MME(23,31,0), MMBME_MASK,	PPCCOM,		{ RA, RS, RB } },
3269
{ "rlwnm",   M(23,0),	M_MASK,		PPCCOM,		{ RA,RS,RB,MBE,ME } },
3270
{ "rlnm",    M(23,0),	M_MASK,		PWRCOM,		{ RA,RS,RB,MBE,ME } },
3271
{ "rotlw.",  MME(23,31,1), MMBME_MASK,	PPCCOM,		{ RA, RS, RB } },
3272
{ "rlwnm.",  M(23,1),	M_MASK,		PPCCOM,		{ RA,RS,RB,MBE,ME } },
3273
{ "rlnm.",   M(23,1),	M_MASK,		PWRCOM,		{ RA,RS,RB,MBE,ME } },
3274

3275
{ "nop",     OP(24),	0xffffffff,	PPCCOM,		{ 0 } },
3276
{ "ori",     OP(24),	OP_MASK,	PPCCOM,		{ RA, RS, UI } },
3277
{ "oril",    OP(24),	OP_MASK,	PWRCOM,		{ RA, RS, UI } },
3278

3279
{ "oris",    OP(25),	OP_MASK,	PPCCOM,		{ RA, RS, UI } },
3280
{ "oriu",    OP(25),	OP_MASK,	PWRCOM,		{ RA, RS, UI } },
3281

3282
{ "xori",    OP(26),	OP_MASK,	PPCCOM,		{ RA, RS, UI } },
3283
{ "xoril",   OP(26),	OP_MASK,	PWRCOM,		{ RA, RS, UI } },
3284

3285
{ "xoris",   OP(27),	OP_MASK,	PPCCOM,		{ RA, RS, UI } },
3286
{ "xoriu",   OP(27),	OP_MASK,	PWRCOM,		{ RA, RS, UI } },
3287

3288
{ "andi.",   OP(28),	OP_MASK,	PPCCOM,		{ RA, RS, UI } },
3289
{ "andil.",  OP(28),	OP_MASK,	PWRCOM,		{ RA, RS, UI } },
3290

3291
{ "andis.",  OP(29),	OP_MASK,	PPCCOM,		{ RA, RS, UI } },
3292
{ "andiu.",  OP(29),	OP_MASK,	PWRCOM,		{ RA, RS, UI } },
3293

3294
{ "rotldi",  MD(30,0,0), MDMB_MASK,	PPC64,		{ RA, RS, SH6 } },
3295
{ "clrldi",  MD(30,0,0), MDSH_MASK,	PPC64,		{ RA, RS, MB6 } },
3296
{ "rldicl",  MD(30,0,0), MD_MASK,	PPC64,		{ RA, RS, SH6, MB6 } },
3297
{ "rotldi.", MD(30,0,1), MDMB_MASK,	PPC64,		{ RA, RS, SH6 } },
3298
{ "clrldi.", MD(30,0,1), MDSH_MASK,	PPC64,		{ RA, RS, MB6 } },
3299
{ "rldicl.", MD(30,0,1), MD_MASK,	PPC64,		{ RA, RS, SH6, MB6 } },
3300

3301
{ "rldicr",  MD(30,1,0), MD_MASK,	PPC64,		{ RA, RS, SH6, ME6 } },
3302
{ "rldicr.", MD(30,1,1), MD_MASK,	PPC64,		{ RA, RS, SH6, ME6 } },
3303

3304
{ "rldic",   MD(30,2,0), MD_MASK,	PPC64,		{ RA, RS, SH6, MB6 } },
3305
{ "rldic.",  MD(30,2,1), MD_MASK,	PPC64,		{ RA, RS, SH6, MB6 } },
3306

3307
{ "rldimi",  MD(30,3,0), MD_MASK,	PPC64,		{ RA, RS, SH6, MB6 } },
3308
{ "rldimi.", MD(30,3,1), MD_MASK,	PPC64,		{ RA, RS, SH6, MB6 } },
3309

3310
{ "rotld",   MDS(30,8,0), MDSMB_MASK,	PPC64,		{ RA, RS, RB } },
3311
{ "rldcl",   MDS(30,8,0), MDS_MASK,	PPC64,		{ RA, RS, RB, MB6 } },
3312
{ "rotld.",  MDS(30,8,1), MDSMB_MASK,	PPC64,		{ RA, RS, RB } },
3313
{ "rldcl.",  MDS(30,8,1), MDS_MASK,	PPC64,		{ RA, RS, RB, MB6 } },
3314

3315
{ "rldcr",   MDS(30,9,0), MDS_MASK,	PPC64,		{ RA, RS, RB, ME6 } },
3316
{ "rldcr.",  MDS(30,9,1), MDS_MASK,	PPC64,		{ RA, RS, RB, ME6 } },
3317

3318
{ "cmpw",    XOPL(31,0,0), XCMPL_MASK, PPCCOM,		{ OBF, RA, RB } },
3319
{ "cmpd",    XOPL(31,0,1), XCMPL_MASK, PPC64,		{ OBF, RA, RB } },
3320
{ "cmp",     X(31,0),	XCMP_MASK,	PPC,		{ BF, L, RA, RB } },
3321
{ "cmp",     X(31,0),	XCMPL_MASK,	PWRCOM,		{ BF, RA, RB } },
3322

3323
{ "twlgt",   XTO(31,4,TOLGT), XTO_MASK, PPCCOM,		{ RA, RB } },
3324
{ "tlgt",    XTO(31,4,TOLGT), XTO_MASK, PWRCOM,		{ RA, RB } },
3325
{ "twllt",   XTO(31,4,TOLLT), XTO_MASK, PPCCOM,		{ RA, RB } },
3326
{ "tllt",    XTO(31,4,TOLLT), XTO_MASK, PWRCOM,		{ RA, RB } },
3327
{ "tweq",    XTO(31,4,TOEQ), XTO_MASK,	PPCCOM,		{ RA, RB } },
3328
{ "teq",     XTO(31,4,TOEQ), XTO_MASK,	PWRCOM,		{ RA, RB } },
3329
{ "twlge",   XTO(31,4,TOLGE), XTO_MASK, PPCCOM,		{ RA, RB } },
3330
{ "tlge",    XTO(31,4,TOLGE), XTO_MASK, PWRCOM,		{ RA, RB } },
3331
{ "twlnl",   XTO(31,4,TOLNL), XTO_MASK, PPCCOM,		{ RA, RB } },
3332
{ "tlnl",    XTO(31,4,TOLNL), XTO_MASK, PWRCOM,		{ RA, RB } },
3333
{ "twlle",   XTO(31,4,TOLLE), XTO_MASK, PPCCOM,		{ RA, RB } },
3334
{ "tlle",    XTO(31,4,TOLLE), XTO_MASK, PWRCOM,		{ RA, RB } },
3335
{ "twlng",   XTO(31,4,TOLNG), XTO_MASK, PPCCOM,		{ RA, RB } },
3336
{ "tlng",    XTO(31,4,TOLNG), XTO_MASK, PWRCOM,		{ RA, RB } },
3337
{ "twgt",    XTO(31,4,TOGT), XTO_MASK,	PPCCOM,		{ RA, RB } },
3338
{ "tgt",     XTO(31,4,TOGT), XTO_MASK,	PWRCOM,		{ RA, RB } },
3339
{ "twge",    XTO(31,4,TOGE), XTO_MASK,	PPCCOM,		{ RA, RB } },
3340
{ "tge",     XTO(31,4,TOGE), XTO_MASK,	PWRCOM,		{ RA, RB } },
3341
{ "twnl",    XTO(31,4,TONL), XTO_MASK,	PPCCOM,		{ RA, RB } },
3342
{ "tnl",     XTO(31,4,TONL), XTO_MASK,	PWRCOM,		{ RA, RB } },
3343
{ "twlt",    XTO(31,4,TOLT), XTO_MASK,	PPCCOM,		{ RA, RB } },
3344
{ "tlt",     XTO(31,4,TOLT), XTO_MASK,	PWRCOM,		{ RA, RB } },
3345
{ "twle",    XTO(31,4,TOLE), XTO_MASK,	PPCCOM,		{ RA, RB } },
3346
{ "tle",     XTO(31,4,TOLE), XTO_MASK,	PWRCOM,		{ RA, RB } },
3347
{ "twng",    XTO(31,4,TONG), XTO_MASK,	PPCCOM,		{ RA, RB } },
3348
{ "tng",     XTO(31,4,TONG), XTO_MASK,	PWRCOM,		{ RA, RB } },
3349
{ "twne",    XTO(31,4,TONE), XTO_MASK,	PPCCOM,		{ RA, RB } },
3350
{ "tne",     XTO(31,4,TONE), XTO_MASK,	PWRCOM,		{ RA, RB } },
3351
{ "trap",    XTO(31,4,TOU), 0xffffffff,	PPCCOM,		{ 0 } },
3352
{ "tw",      X(31,4),	X_MASK,		PPCCOM,		{ TO, RA, RB } },
3353
{ "t",       X(31,4),	X_MASK,		PWRCOM,		{ TO, RA, RB } },
3354

3355
{ "subfc",   XO(31,8,0,0), XO_MASK,	PPCCOM,		{ RT, RA, RB } },
3356
{ "sf",      XO(31,8,0,0), XO_MASK,	PWRCOM,		{ RT, RA, RB } },
3357
{ "subc",    XO(31,8,0,0), XO_MASK,	PPC,		{ RT, RB, RA } },
3358
{ "subfc.",  XO(31,8,0,1), XO_MASK,	PPCCOM,		{ RT, RA, RB } },
3359
{ "sf.",     XO(31,8,0,1), XO_MASK,	PWRCOM,		{ RT, RA, RB } },
3360
{ "subc.",   XO(31,8,0,1), XO_MASK,	PPCCOM,		{ RT, RB, RA } },
3361
{ "subfco",  XO(31,8,1,0), XO_MASK,	PPCCOM,		{ RT, RA, RB } },
3362
{ "sfo",     XO(31,8,1,0), XO_MASK,	PWRCOM,		{ RT, RA, RB } },
3363
{ "subco",   XO(31,8,1,0), XO_MASK,	PPC,		{ RT, RB, RA } },
3364
{ "subfco.", XO(31,8,1,1), XO_MASK,	PPCCOM,		{ RT, RA, RB } },
3365
{ "sfo.",    XO(31,8,1,1), XO_MASK,	PWRCOM,		{ RT, RA, RB } },
3366
{ "subco.",  XO(31,8,1,1), XO_MASK,	PPC,		{ RT, RB, RA } },
3367

3368
{ "mulhdu",  XO(31,9,0,0), XO_MASK,	PPC64,		{ RT, RA, RB } },
3369
{ "mulhdu.", XO(31,9,0,1), XO_MASK,	PPC64,		{ RT, RA, RB } },
3370

3371
{ "addc",    XO(31,10,0,0), XO_MASK,	PPCCOM,		{ RT, RA, RB } },
3372
{ "a",       XO(31,10,0,0), XO_MASK,	PWRCOM,		{ RT, RA, RB } },
3373
{ "addc.",   XO(31,10,0,1), XO_MASK,	PPCCOM,		{ RT, RA, RB } },
3374
{ "a.",      XO(31,10,0,1), XO_MASK,	PWRCOM,		{ RT, RA, RB } },
3375
{ "addco",   XO(31,10,1,0), XO_MASK,	PPCCOM,		{ RT, RA, RB } },
3376
{ "ao",      XO(31,10,1,0), XO_MASK,	PWRCOM,		{ RT, RA, RB } },
3377
{ "addco.",  XO(31,10,1,1), XO_MASK,	PPCCOM,		{ RT, RA, RB } },
3378
{ "ao.",     XO(31,10,1,1), XO_MASK,	PWRCOM,		{ RT, RA, RB } },
3379

3380
{ "mulhwu",  XO(31,11,0,0), XO_MASK,	PPC,		{ RT, RA, RB } },
3381
{ "mulhwu.", XO(31,11,0,1), XO_MASK,	PPC,		{ RT, RA, RB } },
3382

3383
{ "isellt",  X(31,15),      X_MASK,	PPCISEL,	{ RT, RA, RB } },
3384
{ "iselgt",  X(31,47),      X_MASK,	PPCISEL,	{ RT, RA, RB } },
3385
{ "iseleq",  X(31,79),      X_MASK,	PPCISEL,	{ RT, RA, RB } },
3386
{ "isel",    XISEL(31,15),  XISEL_MASK,	PPCISEL,	{ RT, RA, RB, CRB } },
3387

3388
{ "mfocrf",  XFXM(31,19,0,1), XFXFXM_MASK, COM,		{ RT, FXM } },
3389
{ "mfcr",    X(31,19),	XRARB_MASK,	NOPOWER4 | COM,	{ RT } },
3390
{ "mfcr",    X(31,19),	XFXFXM_MASK,	POWER4,		{ RT, FXM4 } },
3391

3392
{ "lwarx",   X(31,20),	XEH_MASK,	PPC,		{ RT, RA0, RB, EH } },
3393

3394
{ "ldx",     X(31,21),	X_MASK,		PPC64,		{ RT, RA0, RB } },
3395

3396
{ "icbt",    X(31,22),	X_MASK,		BOOKE|PPCE300,	{ CT, RA, RB } },
3397
{ "icbt",    X(31,262),	XRT_MASK,	PPC403,		{ RA, RB } },
3398

3399
{ "lwzx",    X(31,23),	X_MASK,		PPCCOM,		{ RT, RA0, RB } },
3400
{ "lx",      X(31,23),	X_MASK,		PWRCOM,		{ RT, RA, RB } },
3401

3402
{ "slw",     XRC(31,24,0), X_MASK,	PPCCOM,		{ RA, RS, RB } },
3403
{ "sl",      XRC(31,24,0), X_MASK,	PWRCOM,		{ RA, RS, RB } },
3404
{ "slw.",    XRC(31,24,1), X_MASK,	PPCCOM,		{ RA, RS, RB } },
3405
{ "sl.",     XRC(31,24,1), X_MASK,	PWRCOM,		{ RA, RS, RB } },
3406

3407
{ "cntlzw",  XRC(31,26,0), XRB_MASK,	PPCCOM,		{ RA, RS } },
3408
{ "cntlz",   XRC(31,26,0), XRB_MASK,	PWRCOM,		{ RA, RS } },
3409
{ "cntlzw.", XRC(31,26,1), XRB_MASK,	PPCCOM,		{ RA, RS } },
3410
{ "cntlz.",  XRC(31,26,1), XRB_MASK, 	PWRCOM,		{ RA, RS } },
3411

3412
{ "sld",     XRC(31,27,0), X_MASK,	PPC64,		{ RA, RS, RB } },
3413
{ "sld.",    XRC(31,27,1), X_MASK,	PPC64,		{ RA, RS, RB } },
3414

3415
{ "and",     XRC(31,28,0), X_MASK,	COM,		{ RA, RS, RB } },
3416
{ "and.",    XRC(31,28,1), X_MASK,	COM,		{ RA, RS, RB } },
3417

3418
{ "maskg",   XRC(31,29,0), X_MASK,	M601,		{ RA, RS, RB } },
3419
{ "maskg.",  XRC(31,29,1), X_MASK,	M601,		{ RA, RS, RB } },
3420

3421
{ "icbte",   X(31,30),	X_MASK,		BOOKE64,	{ CT, RA, RB } },
3422

3423
{ "lwzxe",   X(31,31),	X_MASK,		BOOKE64,	{ RT, RA0, RB } },
3424

3425
{ "cmplw",   XOPL(31,32,0), XCMPL_MASK, PPCCOM,	{ OBF, RA, RB } },
3426
{ "cmpld",   XOPL(31,32,1), XCMPL_MASK, PPC64,		{ OBF, RA, RB } },
3427
{ "cmpl",    X(31,32),	XCMP_MASK,	 PPC,		{ BF, L, RA, RB } },
3428
{ "cmpl",    X(31,32),	XCMPL_MASK,	 PWRCOM,	{ BF, RA, RB } },
3429

3430
{ "subf",    XO(31,40,0,0), XO_MASK,	PPC,		{ RT, RA, RB } },
3431
{ "sub",     XO(31,40,0,0), XO_MASK,	PPC,		{ RT, RB, RA } },
3432
{ "subf.",   XO(31,40,0,1), XO_MASK,	PPC,		{ RT, RA, RB } },
3433
{ "sub.",    XO(31,40,0,1), XO_MASK,	PPC,		{ RT, RB, RA } },
3434
{ "subfo",   XO(31,40,1,0), XO_MASK,	PPC,		{ RT, RA, RB } },
3435
{ "subo",    XO(31,40,1,0), XO_MASK,	PPC,		{ RT, RB, RA } },
3436
{ "subfo.",  XO(31,40,1,1), XO_MASK,	PPC,		{ RT, RA, RB } },
3437
{ "subo.",   XO(31,40,1,1), XO_MASK,	PPC,		{ RT, RB, RA } },
3438

3439
{ "ldux",    X(31,53),	X_MASK,		PPC64,		{ RT, RAL, RB } },
3440

3441
{ "dcbst",   X(31,54),	XRT_MASK,	PPC,		{ RA, RB } },
3442

3443
{ "lwzux",   X(31,55),	X_MASK,		PPCCOM,		{ RT, RAL, RB } },
3444
{ "lux",     X(31,55),	X_MASK,		PWRCOM,		{ RT, RA, RB } },
3445

3446
{ "dcbste",  X(31,62),	XRT_MASK,	BOOKE64,	{ RA, RB } },
3447

3448
{ "lwzuxe",  X(31,63),	X_MASK,		BOOKE64,	{ RT, RAL, RB } },
3449

3450
{ "cntlzd",  XRC(31,58,0), XRB_MASK,	PPC64,		{ RA, RS } },
3451
{ "cntlzd.", XRC(31,58,1), XRB_MASK,	PPC64,		{ RA, RS } },
3452

3453
{ "andc",    XRC(31,60,0), X_MASK,	COM,		{ RA, RS, RB } },
3454
{ "andc.",   XRC(31,60,1), X_MASK,	COM,		{ RA, RS, RB } },
3455

3456
{ "tdlgt",   XTO(31,68,TOLGT), XTO_MASK, PPC64,		{ RA, RB } },
3457
{ "tdllt",   XTO(31,68,TOLLT), XTO_MASK, PPC64,		{ RA, RB } },
3458
{ "tdeq",    XTO(31,68,TOEQ), XTO_MASK,  PPC64,		{ RA, RB } },
3459
{ "tdlge",   XTO(31,68,TOLGE), XTO_MASK, PPC64,		{ RA, RB } },
3460
{ "tdlnl",   XTO(31,68,TOLNL), XTO_MASK, PPC64,		{ RA, RB } },
3461
{ "tdlle",   XTO(31,68,TOLLE), XTO_MASK, PPC64,		{ RA, RB } },
3462
{ "tdlng",   XTO(31,68,TOLNG), XTO_MASK, PPC64,		{ RA, RB } },
3463
{ "tdgt",    XTO(31,68,TOGT), XTO_MASK,  PPC64,		{ RA, RB } },
3464
{ "tdge",    XTO(31,68,TOGE), XTO_MASK,  PPC64,		{ RA, RB } },
3465
{ "tdnl",    XTO(31,68,TONL), XTO_MASK,  PPC64,		{ RA, RB } },
3466
{ "tdlt",    XTO(31,68,TOLT), XTO_MASK,  PPC64,		{ RA, RB } },
3467
{ "tdle",    XTO(31,68,TOLE), XTO_MASK,  PPC64,		{ RA, RB } },
3468
{ "tdng",    XTO(31,68,TONG), XTO_MASK,  PPC64,		{ RA, RB } },
3469
{ "tdne",    XTO(31,68,TONE), XTO_MASK,  PPC64,		{ RA, RB } },
3470
{ "td",	     X(31,68),	X_MASK,		 PPC64,		{ TO, RA, RB } },
3471

3472
{ "mulhd",   XO(31,73,0,0), XO_MASK,	 PPC64,		{ RT, RA, RB } },
3473
{ "mulhd.",  XO(31,73,0,1), XO_MASK,	 PPC64,		{ RT, RA, RB } },
3474

3475
{ "mulhw",   XO(31,75,0,0), XO_MASK,	PPC,		{ RT, RA, RB } },
3476
{ "mulhw.",  XO(31,75,0,1), XO_MASK,	PPC,		{ RT, RA, RB } },
3477

3478
{ "dlmzb",   XRC(31,78,0),  X_MASK,	PPC403|PPC440,	{ RA, RS, RB } },
3479
{ "dlmzb.",  XRC(31,78,1),  X_MASK,	PPC403|PPC440,	{ RA, RS, RB } },
3480

3481
{ "mtsrd",   X(31,82),	XRB_MASK|(1<<20), PPC64,	{ SR, RS } },
3482

3483
{ "mfmsr",   X(31,83),	XRARB_MASK,	COM,		{ RT } },
3484

3485
{ "ldarx",   X(31,84),	XEH_MASK,	PPC64,		{ RT, RA0, RB, EH } },
3486

3487
{ "dcbfl",   XOPL(31,86,1), XRT_MASK,	POWER5,		{ RA, RB } },
3488
{ "dcbf",    X(31,86),	XLRT_MASK,	PPC,		{ RA, RB, XRT_L } },
3489

3490
{ "lbzx",    X(31,87),	X_MASK,		COM,		{ RT, RA0, RB } },
3491

3492
{ "dcbfe",   X(31,94),	XRT_MASK,	BOOKE64,	{ RA, RB } },
3493

3494
{ "lbzxe",   X(31,95),	X_MASK,		BOOKE64,	{ RT, RA0, RB } },
3495

3496
{ "neg",     XO(31,104,0,0), XORB_MASK,	COM,		{ RT, RA } },
3497
{ "neg.",    XO(31,104,0,1), XORB_MASK,	COM,		{ RT, RA } },
3498
{ "nego",    XO(31,104,1,0), XORB_MASK,	COM,		{ RT, RA } },
3499
{ "nego.",   XO(31,104,1,1), XORB_MASK,	COM,		{ RT, RA } },
3500

3501
{ "mul",     XO(31,107,0,0), XO_MASK,	M601,		{ RT, RA, RB } },
3502
{ "mul.",    XO(31,107,0,1), XO_MASK,	M601,		{ RT, RA, RB } },
3503
{ "mulo",    XO(31,107,1,0), XO_MASK,	M601,		{ RT, RA, RB } },
3504
{ "mulo.",   XO(31,107,1,1), XO_MASK,	M601,		{ RT, RA, RB } },
3505

3506
{ "mtsrdin", X(31,114),	XRA_MASK,	PPC64,		{ RS, RB } },
3507

3508
{ "clf",     X(31,118), XTO_MASK,	POWER,		{ RA, RB } },
3509

3510
{ "lbzux",   X(31,119),	X_MASK,		COM,		{ RT, RAL, RB } },
3511

3512
{ "popcntb", X(31,122), XRB_MASK,	POWER5,		{ RA, RS } },
3513

3514
{ "not",     XRC(31,124,0), X_MASK,	COM,		{ RA, RS, RBS } },
3515
{ "nor",     XRC(31,124,0), X_MASK,	COM,		{ RA, RS, RB } },
3516
{ "not.",    XRC(31,124,1), X_MASK,	COM,		{ RA, RS, RBS } },
3517
{ "nor.",    XRC(31,124,1), X_MASK,	COM,		{ RA, RS, RB } },
3518

3519
{ "lwarxe",  X(31,126),	X_MASK,		BOOKE64,	{ RT, RA0, RB } },
3520

3521
{ "lbzuxe",  X(31,127),	X_MASK,		BOOKE64,	{ RT, RAL, RB } },
3522

3523
{ "wrtee",   X(31,131),	XRARB_MASK,	PPC403 | BOOKE,	{ RS } },
3524

3525
{ "dcbtstls",X(31,134),	X_MASK,		PPCCHLK,	{ CT, RA, RB }},
3526

3527
{ "subfe",   XO(31,136,0,0), XO_MASK,	PPCCOM,		{ RT, RA, RB } },
3528
{ "sfe",     XO(31,136,0,0), XO_MASK,	PWRCOM,		{ RT, RA, RB } },
3529
{ "subfe.",  XO(31,136,0,1), XO_MASK,	PPCCOM,		{ RT, RA, RB } },
3530
{ "sfe.",    XO(31,136,0,1), XO_MASK,	PWRCOM,		{ RT, RA, RB } },
3531
{ "subfeo",  XO(31,136,1,0), XO_MASK,	PPCCOM,		{ RT, RA, RB } },
3532
{ "sfeo",    XO(31,136,1,0), XO_MASK,	PWRCOM,		{ RT, RA, RB } },
3533
{ "subfeo.", XO(31,136,1,1), XO_MASK,	PPCCOM,		{ RT, RA, RB } },
3534
{ "sfeo.",   XO(31,136,1,1), XO_MASK,	PWRCOM,		{ RT, RA, RB } },
3535

3536
{ "adde",    XO(31,138,0,0), XO_MASK,	PPCCOM,		{ RT, RA, RB } },
3537
{ "ae",      XO(31,138,0,0), XO_MASK,	PWRCOM,		{ RT, RA, RB } },
3538
{ "adde.",   XO(31,138,0,1), XO_MASK,	PPCCOM,		{ RT, RA, RB } },
3539
{ "ae.",     XO(31,138,0,1), XO_MASK,	PWRCOM,		{ RT, RA, RB } },
3540
{ "addeo",   XO(31,138,1,0), XO_MASK,	PPCCOM,		{ RT, RA, RB } },
3541
{ "aeo",     XO(31,138,1,0), XO_MASK,	PWRCOM,		{ RT, RA, RB } },
3542
{ "addeo.",  XO(31,138,1,1), XO_MASK,	PPCCOM,		{ RT, RA, RB } },
3543
{ "aeo.",    XO(31,138,1,1), XO_MASK,	PWRCOM,		{ RT, RA, RB } },
3544

3545
{ "dcbtstlse",X(31,142),X_MASK,		PPCCHLK64,	{ CT, RA, RB }},
3546

3547
{ "mtocrf",  XFXM(31,144,0,1), XFXFXM_MASK, COM,	{ FXM, RS } },
3548
{ "mtcr",    XFXM(31,144,0xff,0), XRARB_MASK, COM,	{ RS }},
3549
{ "mtcrf",   X(31,144),	XFXFXM_MASK,	COM,		{ FXM, RS } },
3550

3551
{ "mtmsr",   X(31,146),	XRARB_MASK,	COM,		{ RS } },
3552

3553
{ "stdx",    X(31,149), X_MASK,		PPC64,		{ RS, RA0, RB } },
3554

3555
{ "stwcx.",  XRC(31,150,1), X_MASK,	PPC,		{ RS, RA0, RB } },
3556

3557
{ "stwx",    X(31,151), X_MASK,		PPCCOM,		{ RS, RA0, RB } },
3558
{ "stx",     X(31,151), X_MASK,		PWRCOM,		{ RS, RA, RB } },
3559

3560
{ "stwcxe.", XRC(31,158,1), X_MASK,	BOOKE64,	{ RS, RA0, RB } },
3561

3562
{ "stwxe",   X(31,159), X_MASK,		BOOKE64,	{ RS, RA0, RB } },
3563

3564
{ "slq",     XRC(31,152,0), X_MASK,	M601,		{ RA, RS, RB } },
3565
{ "slq.",    XRC(31,152,1), X_MASK,	M601,		{ RA, RS, RB } },
3566

3567
{ "sle",     XRC(31,153,0), X_MASK,	M601,		{ RA, RS, RB } },
3568
{ "sle.",    XRC(31,153,1), X_MASK,	M601,		{ RA, RS, RB } },
3569

3570
{ "prtyw",   X(31,154),	XRB_MASK,	POWER6,		{ RA, RS } },
3571

3572
{ "wrteei",  X(31,163),	XE_MASK,	PPC403 | BOOKE,	{ E } },
3573

3574
{ "dcbtls",  X(31,166),	X_MASK,		PPCCHLK,	{ CT, RA, RB }},
3575
{ "dcbtlse", X(31,174),	X_MASK,		PPCCHLK64,	{ CT, RA, RB }},
3576

3577
{ "mtmsrd",  X(31,178),	XRLARB_MASK,	PPC64,		{ RS, MTMSRD_L } },
3578

3579
{ "stdux",   X(31,181),	X_MASK,		PPC64,		{ RS, RAS, RB } },
3580

3581
{ "stwux",   X(31,183),	X_MASK,		PPCCOM,		{ RS, RAS, RB } },
3582
{ "stux",    X(31,183),	X_MASK,		PWRCOM,		{ RS, RA0, RB } },
3583

3584
{ "sliq",    XRC(31,184,0), X_MASK,	M601,		{ RA, RS, SH } },
3585
{ "sliq.",   XRC(31,184,1), X_MASK,	M601,		{ RA, RS, SH } },
3586

3587
{ "prtyd",   X(31,186),	XRB_MASK,	POWER6,		{ RA, RS } },
3588

3589
{ "stwuxe",  X(31,191),	X_MASK,		BOOKE64,	{ RS, RAS, RB } },
3590

3591
{ "subfze",  XO(31,200,0,0), XORB_MASK, PPCCOM,		{ RT, RA } },
3592
{ "sfze",    XO(31,200,0,0), XORB_MASK, PWRCOM,		{ RT, RA } },
3593
{ "subfze.", XO(31,200,0,1), XORB_MASK, PPCCOM,		{ RT, RA } },
3594
{ "sfze.",   XO(31,200,0,1), XORB_MASK, PWRCOM,		{ RT, RA } },
3595
{ "subfzeo", XO(31,200,1,0), XORB_MASK, PPCCOM,		{ RT, RA } },
3596
{ "sfzeo",   XO(31,200,1,0), XORB_MASK, PWRCOM,		{ RT, RA } },
3597
{ "subfzeo.",XO(31,200,1,1), XORB_MASK, PPCCOM,		{ RT, RA } },
3598
{ "sfzeo.",  XO(31,200,1,1), XORB_MASK, PWRCOM,		{ RT, RA } },
3599

3600
{ "addze",   XO(31,202,0,0), XORB_MASK, PPCCOM,		{ RT, RA } },
3601
{ "aze",     XO(31,202,0,0), XORB_MASK, PWRCOM,		{ RT, RA } },
3602
{ "addze.",  XO(31,202,0,1), XORB_MASK, PPCCOM,		{ RT, RA } },
3603
{ "aze.",    XO(31,202,0,1), XORB_MASK, PWRCOM,		{ RT, RA } },
3604
{ "addzeo",  XO(31,202,1,0), XORB_MASK, PPCCOM,		{ RT, RA } },
3605
{ "azeo",    XO(31,202,1,0), XORB_MASK, PWRCOM,		{ RT, RA } },
3606
{ "addzeo.", XO(31,202,1,1), XORB_MASK, PPCCOM,		{ RT, RA } },
3607
{ "azeo.",   XO(31,202,1,1), XORB_MASK, PWRCOM,		{ RT, RA } },
3608

3609
{ "mtsr",    X(31,210),	XRB_MASK|(1<<20), COM32,	{ SR, RS } },
3610

3611
{ "stdcx.",  XRC(31,214,1), X_MASK,	PPC64,		{ RS, RA0, RB } },
3612

3613
{ "stbx",    X(31,215),	X_MASK,		COM,		{ RS, RA0, RB } },
3614

3615
{ "sllq",    XRC(31,216,0), X_MASK,	M601,		{ RA, RS, RB } },
3616
{ "sllq.",   XRC(31,216,1), X_MASK,	M601,		{ RA, RS, RB } },
3617

3618
{ "sleq",    XRC(31,217,0), X_MASK,	M601,		{ RA, RS, RB } },
3619
{ "sleq.",   XRC(31,217,1), X_MASK,	M601,		{ RA, RS, RB } },
3620

3621
{ "stbxe",   X(31,223),	X_MASK,		BOOKE64,	{ RS, RA0, RB } },
3622

3623
{ "icblc",   X(31,230),	X_MASK,		PPCCHLK,	{ CT, RA, RB }},
3624

3625
{ "subfme",  XO(31,232,0,0), XORB_MASK, PPCCOM,		{ RT, RA } },
3626
{ "sfme",    XO(31,232,0,0), XORB_MASK, PWRCOM,		{ RT, RA } },
3627
{ "subfme.", XO(31,232,0,1), XORB_MASK, PPCCOM,		{ RT, RA } },
3628
{ "sfme.",   XO(31,232,0,1), XORB_MASK, PWRCOM,		{ RT, RA } },
3629
{ "subfmeo", XO(31,232,1,0), XORB_MASK, PPCCOM,		{ RT, RA } },
3630
{ "sfmeo",   XO(31,232,1,0), XORB_MASK, PWRCOM,		{ RT, RA } },
3631
{ "subfmeo.",XO(31,232,1,1), XORB_MASK, PPCCOM,		{ RT, RA } },
3632
{ "sfmeo.",  XO(31,232,1,1), XORB_MASK, PWRCOM,		{ RT, RA } },
3633

3634
{ "mulld",   XO(31,233,0,0), XO_MASK,	PPC64,		{ RT, RA, RB } },
3635
{ "mulld.",  XO(31,233,0,1), XO_MASK,	PPC64,		{ RT, RA, RB } },
3636
{ "mulldo",  XO(31,233,1,0), XO_MASK,	PPC64,		{ RT, RA, RB } },
3637
{ "mulldo.", XO(31,233,1,1), XO_MASK,	PPC64,		{ RT, RA, RB } },
3638

3639
{ "addme",   XO(31,234,0,0), XORB_MASK, PPCCOM,		{ RT, RA } },
3640
{ "ame",     XO(31,234,0,0), XORB_MASK, PWRCOM,		{ RT, RA } },
3641
{ "addme.",  XO(31,234,0,1), XORB_MASK, PPCCOM,		{ RT, RA } },
3642
{ "ame.",    XO(31,234,0,1), XORB_MASK, PWRCOM,		{ RT, RA } },
3643
{ "addmeo",  XO(31,234,1,0), XORB_MASK, PPCCOM,		{ RT, RA } },
3644
{ "ameo",    XO(31,234,1,0), XORB_MASK, PWRCOM,		{ RT, RA } },
3645
{ "addmeo.", XO(31,234,1,1), XORB_MASK, PPCCOM,		{ RT, RA } },
3646
{ "ameo.",   XO(31,234,1,1), XORB_MASK, PWRCOM,		{ RT, RA } },
3647

3648
{ "mullw",   XO(31,235,0,0), XO_MASK,	PPCCOM,		{ RT, RA, RB } },
3649
{ "muls",    XO(31,235,0,0), XO_MASK,	PWRCOM,		{ RT, RA, RB } },
3650
{ "mullw.",  XO(31,235,0,1), XO_MASK,	PPCCOM,		{ RT, RA, RB } },
3651
{ "muls.",   XO(31,235,0,1), XO_MASK,	PWRCOM,		{ RT, RA, RB } },
3652
{ "mullwo",  XO(31,235,1,0), XO_MASK,	PPCCOM,		{ RT, RA, RB } },
3653
{ "mulso",   XO(31,235,1,0), XO_MASK,	PWRCOM,		{ RT, RA, RB } },
3654
{ "mullwo.", XO(31,235,1,1), XO_MASK,	PPCCOM,		{ RT, RA, RB } },
3655
{ "mulso.",  XO(31,235,1,1), XO_MASK,	PWRCOM,		{ RT, RA, RB } },
3656

3657
{ "icblce",  X(31,238),	X_MASK,		PPCCHLK64,	{ CT, RA, RB }},
3658
{ "mtsrin",  X(31,242),	XRA_MASK,	PPC32,		{ RS, RB } },
3659
{ "mtsri",   X(31,242),	XRA_MASK,	POWER32,	{ RS, RB } },
3660

3661
{ "dcbtst",  X(31,246),	X_MASK,	PPC,			{ CT, RA, RB } },
3662

3663
{ "stbux",   X(31,247),	X_MASK,		COM,		{ RS, RAS, RB } },
3664

3665
{ "slliq",   XRC(31,248,0), X_MASK,	M601,		{ RA, RS, SH } },
3666
{ "slliq.",  XRC(31,248,1), X_MASK,	M601,		{ RA, RS, SH } },
3667

3668
{ "dcbtste", X(31,253),	X_MASK,		BOOKE64,	{ CT, RA, RB } },
3669

3670
{ "stbuxe",  X(31,255),	X_MASK,		BOOKE64,	{ RS, RAS, RB } },
3671

3672
{ "mfdcrx",  X(31,259),	X_MASK,		BOOKE,		{ RS, RA } },
3673

3674
{ "doz",     XO(31,264,0,0), XO_MASK,	M601,		{ RT, RA, RB } },
3675
{ "doz.",    XO(31,264,0,1), XO_MASK,	M601,		{ RT, RA, RB } },
3676
{ "dozo",    XO(31,264,1,0), XO_MASK,	M601,		{ RT, RA, RB } },
3677
{ "dozo.",   XO(31,264,1,1), XO_MASK,	M601,		{ RT, RA, RB } },
3678

3679
{ "add",     XO(31,266,0,0), XO_MASK,	PPCCOM,		{ RT, RA, RB } },
3680
{ "cax",     XO(31,266,0,0), XO_MASK,	PWRCOM,		{ RT, RA, RB } },
3681
{ "add.",    XO(31,266,0,1), XO_MASK,	PPCCOM,		{ RT, RA, RB } },
3682
{ "cax.",    XO(31,266,0,1), XO_MASK,	PWRCOM,		{ RT, RA, RB } },
3683
{ "addo",    XO(31,266,1,0), XO_MASK,	PPCCOM,		{ RT, RA, RB } },
3684
{ "caxo",    XO(31,266,1,0), XO_MASK,	PWRCOM,		{ RT, RA, RB } },
3685
{ "addo.",   XO(31,266,1,1), XO_MASK,	PPCCOM,		{ RT, RA, RB } },
3686
{ "caxo.",   XO(31,266,1,1), XO_MASK,	PWRCOM,		{ RT, RA, RB } },
3687

3688
{ "tlbiel",  X(31,274), XRTLRA_MASK,	POWER4,		{ RB, L } },
3689

3690
{ "mfapidi", X(31,275), X_MASK,		BOOKE,		{ RT, RA } },
3691

3692
{ "lscbx",   XRC(31,277,0), X_MASK,	M601,		{ RT, RA, RB } },
3693
{ "lscbx.",  XRC(31,277,1), X_MASK,	M601,		{ RT, RA, RB } },
3694

3695
{ "dcbt",    X(31,278),	X_MASK,		PPC,		{ CT, RA, RB } },
3696

3697
{ "lhzx",    X(31,279),	X_MASK,		COM,		{ RT, RA0, RB } },
3698

3699
{ "eqv",     XRC(31,284,0), X_MASK,	COM,		{ RA, RS, RB } },
3700
{ "eqv.",    XRC(31,284,1), X_MASK,	COM,		{ RA, RS, RB } },
3701

3702
{ "dcbte",   X(31,286),	X_MASK,		BOOKE64,	{ CT, RA, RB } },
3703

3704
{ "lhzxe",   X(31,287),	X_MASK,		BOOKE64,	{ RT, RA0, RB } },
3705

3706
{ "tlbie",   X(31,306),	XRTLRA_MASK,	PPC,		{ RB, L } },
3707
{ "tlbi",    X(31,306),	XRT_MASK,	POWER,		{ RA0, RB } },
3708

3709
{ "eciwx",   X(31,310), X_MASK,		PPC,		{ RT, RA, RB } },
3710

3711
{ "lhzux",   X(31,311),	X_MASK,		COM,		{ RT, RAL, RB } },
3712

3713
{ "xor",     XRC(31,316,0), X_MASK,	COM,		{ RA, RS, RB } },
3714
{ "xor.",    XRC(31,316,1), X_MASK,	COM,		{ RA, RS, RB } },
3715

3716
{ "lhzuxe",  X(31,319),	X_MASK,		BOOKE64,	{ RT, RAL, RB } },
3717

3718
{ "mfexisr",  XSPR(31,323,64),  XSPR_MASK, PPC403,	{ RT } },
3719
{ "mfexier",  XSPR(31,323,66),  XSPR_MASK, PPC403,	{ RT } },
3720
{ "mfbr0",    XSPR(31,323,128), XSPR_MASK, PPC403,	{ RT } },
3721
{ "mfbr1",    XSPR(31,323,129), XSPR_MASK, PPC403,	{ RT } },
3722
{ "mfbr2",    XSPR(31,323,130), XSPR_MASK, PPC403,	{ RT } },
3723
{ "mfbr3",    XSPR(31,323,131), XSPR_MASK, PPC403,	{ RT } },
3724
{ "mfbr4",    XSPR(31,323,132), XSPR_MASK, PPC403,	{ RT } },
3725
{ "mfbr5",    XSPR(31,323,133), XSPR_MASK, PPC403,	{ RT } },
3726
{ "mfbr6",    XSPR(31,323,134), XSPR_MASK, PPC403,	{ RT } },
3727
{ "mfbr7",    XSPR(31,323,135), XSPR_MASK, PPC403,	{ RT } },
3728
{ "mfbear",   XSPR(31,323,144), XSPR_MASK, PPC403,	{ RT } },
3729
{ "mfbesr",   XSPR(31,323,145), XSPR_MASK, PPC403,	{ RT } },
3730
{ "mfiocr",   XSPR(31,323,160), XSPR_MASK, PPC403,	{ RT } },
3731
{ "mfdmacr0", XSPR(31,323,192), XSPR_MASK, PPC403,	{ RT } },
3732
{ "mfdmact0", XSPR(31,323,193), XSPR_MASK, PPC403,	{ RT } },
3733
{ "mfdmada0", XSPR(31,323,194), XSPR_MASK, PPC403,	{ RT } },
3734
{ "mfdmasa0", XSPR(31,323,195), XSPR_MASK, PPC403,	{ RT } },
3735
{ "mfdmacc0", XSPR(31,323,196), XSPR_MASK, PPC403,	{ RT } },
3736
{ "mfdmacr1", XSPR(31,323,200), XSPR_MASK, PPC403,	{ RT } },
3737
{ "mfdmact1", XSPR(31,323,201), XSPR_MASK, PPC403,	{ RT } },
3738
{ "mfdmada1", XSPR(31,323,202), XSPR_MASK, PPC403,	{ RT } },
3739
{ "mfdmasa1", XSPR(31,323,203), XSPR_MASK, PPC403,	{ RT } },
3740
{ "mfdmacc1", XSPR(31,323,204), XSPR_MASK, PPC403,	{ RT } },
3741
{ "mfdmacr2", XSPR(31,323,208), XSPR_MASK, PPC403,	{ RT } },
3742
{ "mfdmact2", XSPR(31,323,209), XSPR_MASK, PPC403,	{ RT } },
3743
{ "mfdmada2", XSPR(31,323,210), XSPR_MASK, PPC403,	{ RT } },
3744
{ "mfdmasa2", XSPR(31,323,211), XSPR_MASK, PPC403,	{ RT } },
3745
{ "mfdmacc2", XSPR(31,323,212), XSPR_MASK, PPC403,	{ RT } },
3746
{ "mfdmacr3", XSPR(31,323,216), XSPR_MASK, PPC403,	{ RT } },
3747
{ "mfdmact3", XSPR(31,323,217), XSPR_MASK, PPC403,	{ RT } },
3748
{ "mfdmada3", XSPR(31,323,218), XSPR_MASK, PPC403,	{ RT } },
3749
{ "mfdmasa3", XSPR(31,323,219), XSPR_MASK, PPC403,	{ RT } },
3750
{ "mfdmacc3", XSPR(31,323,220), XSPR_MASK, PPC403,	{ RT } },
3751
{ "mfdmasr",  XSPR(31,323,224), XSPR_MASK, PPC403,	{ RT } },
3752
{ "mfdcr",    X(31,323),	X_MASK,	PPC403 | BOOKE,	{ RT, SPR } },
3753

3754
{ "div",     XO(31,331,0,0), XO_MASK,	M601,		{ RT, RA, RB } },
3755
{ "div.",    XO(31,331,0,1), XO_MASK,	M601,		{ RT, RA, RB } },
3756
{ "divo",    XO(31,331,1,0), XO_MASK,	M601,		{ RT, RA, RB } },
3757
{ "divo.",   XO(31,331,1,1), XO_MASK,	M601,		{ RT, RA, RB } },
3758

3759
{ "mfpmr",   X(31,334),	X_MASK,		PPCPMR,		{ RT, PMR }},
3760

3761
{ "mfmq",       XSPR(31,339,0),    XSPR_MASK, M601,	{ RT } },
3762
{ "mfxer",      XSPR(31,339,1),    XSPR_MASK, COM,	{ RT } },
3763
{ "mfrtcu",     XSPR(31,339,4),    XSPR_MASK, COM,	{ RT } },
3764
{ "mfrtcl",     XSPR(31,339,5),    XSPR_MASK, COM,	{ RT } },
3765
{ "mfdec",      XSPR(31,339,6),    XSPR_MASK, MFDEC1,	{ RT } },
3766
{ "mfdec",      XSPR(31,339,22),   XSPR_MASK, MFDEC2,	{ RT } },
3767
{ "mflr",       XSPR(31,339,8),    XSPR_MASK, COM,	{ RT } },
3768
{ "mfctr",      XSPR(31,339,9),    XSPR_MASK, COM,	{ RT } },
3769
{ "mftid",      XSPR(31,339,17),   XSPR_MASK, POWER,	{ RT } },
3770
{ "mfdsisr",    XSPR(31,339,18),   XSPR_MASK, COM,	{ RT } },
3771
{ "mfdar",      XSPR(31,339,19),   XSPR_MASK, COM,	{ RT } },
3772
{ "mfsdr0",     XSPR(31,339,24),   XSPR_MASK, POWER,	{ RT } },
3773
{ "mfsdr1",     XSPR(31,339,25),   XSPR_MASK, COM,	{ RT } },
3774
{ "mfsrr0",     XSPR(31,339,26),   XSPR_MASK, COM,	{ RT } },
3775
{ "mfsrr1",     XSPR(31,339,27),   XSPR_MASK, COM,	{ RT } },
3776
{ "mfcfar",     XSPR(31,339,28),   XSPR_MASK, POWER6,	{ RT } },
3777
{ "mfpid",      XSPR(31,339,48),   XSPR_MASK, BOOKE,    { RT } },
3778
{ "mfpid",      XSPR(31,339,945),  XSPR_MASK, PPC403,	{ RT } },
3779
{ "mfcsrr0",    XSPR(31,339,58),   XSPR_MASK, BOOKE,    { RT } },
3780
{ "mfcsrr1",    XSPR(31,339,59),   XSPR_MASK, BOOKE,    { RT } },
3781
{ "mfdear",     XSPR(31,339,61),   XSPR_MASK, BOOKE,    { RT } },
3782
{ "mfdear",     XSPR(31,339,981),  XSPR_MASK, PPC403,	{ RT } },
3783
{ "mfesr",      XSPR(31,339,62),   XSPR_MASK, BOOKE,    { RT } },
3784
{ "mfesr",      XSPR(31,339,980),  XSPR_MASK, PPC403,	{ RT } },
3785
{ "mfivpr",     XSPR(31,339,63),   XSPR_MASK, BOOKE,    { RT } },
3786
{ "mfcmpa",     XSPR(31,339,144),  XSPR_MASK, PPC860,	{ RT } },
3787
{ "mfcmpb",     XSPR(31,339,145),  XSPR_MASK, PPC860,	{ RT } },
3788
{ "mfcmpc",     XSPR(31,339,146),  XSPR_MASK, PPC860,	{ RT } },
3789
{ "mfcmpd",     XSPR(31,339,147),  XSPR_MASK, PPC860,	{ RT } },
3790
{ "mficr",      XSPR(31,339,148),  XSPR_MASK, PPC860,	{ RT } },
3791
{ "mfder",      XSPR(31,339,149),  XSPR_MASK, PPC860,	{ RT } },
3792
{ "mfcounta",   XSPR(31,339,150),  XSPR_MASK, PPC860,	{ RT } },
3793
{ "mfcountb",   XSPR(31,339,151),  XSPR_MASK, PPC860,	{ RT } },
3794
{ "mfcmpe",     XSPR(31,339,152),  XSPR_MASK, PPC860,	{ RT } },
3795
{ "mfcmpf",     XSPR(31,339,153),  XSPR_MASK, PPC860,	{ RT } },
3796
{ "mfcmpg",     XSPR(31,339,154),  XSPR_MASK, PPC860,	{ RT } },
3797
{ "mfcmph",     XSPR(31,339,155),  XSPR_MASK, PPC860,	{ RT } },
3798
{ "mflctrl1",   XSPR(31,339,156),  XSPR_MASK, PPC860,	{ RT } },
3799
{ "mflctrl2",   XSPR(31,339,157),  XSPR_MASK, PPC860,	{ RT } },
3800
{ "mfictrl",    XSPR(31,339,158),  XSPR_MASK, PPC860,	{ RT } },
3801
{ "mfbar",      XSPR(31,339,159),  XSPR_MASK, PPC860,	{ RT } },
3802
{ "mfvrsave",   XSPR(31,339,256),  XSPR_MASK, PPCVEC,	{ RT } },
3803
{ "mfusprg0",   XSPR(31,339,256),  XSPR_MASK, BOOKE,    { RT } },
3804
{ "mftb",       X(31,371),	   X_MASK,    CLASSIC,	{ RT, TBR } },
3805
{ "mftb",       XSPR(31,339,268),  XSPR_MASK, BOOKE,    { RT } },
3806
{ "mftbl",      XSPR(31,371,268),  XSPR_MASK, CLASSIC,	{ RT } },
3807
{ "mftbl",      XSPR(31,339,268),  XSPR_MASK, BOOKE,    { RT } },
3808
{ "mftbu",      XSPR(31,371,269),  XSPR_MASK, CLASSIC,	{ RT } },
3809
{ "mftbu",      XSPR(31,339,269),  XSPR_MASK, BOOKE,    { RT } },
3810
{ "mfsprg",     XSPR(31,339,256),  XSPRG_MASK, PPC,	{ RT, SPRG } },
3811
{ "mfsprg0",    XSPR(31,339,272),  XSPR_MASK, PPC,	{ RT } },
3812
{ "mfsprg1",    XSPR(31,339,273),  XSPR_MASK, PPC,	{ RT } },
3813
{ "mfsprg2",    XSPR(31,339,274),  XSPR_MASK, PPC,	{ RT } },
3814
{ "mfsprg3",    XSPR(31,339,275),  XSPR_MASK, PPC,	{ RT } },
3815
{ "mfsprg4",    XSPR(31,339,260),  XSPR_MASK, PPC405 | BOOKE,	{ RT } },
3816
{ "mfsprg5",    XSPR(31,339,261),  XSPR_MASK, PPC405 | BOOKE,	{ RT } },
3817
{ "mfsprg6",    XSPR(31,339,262),  XSPR_MASK, PPC405 | BOOKE,	{ RT } },
3818
{ "mfsprg7",    XSPR(31,339,263),  XSPR_MASK, PPC405 | BOOKE,	{ RT } },
3819
{ "mfasr",      XSPR(31,339,280),  XSPR_MASK, PPC64,	{ RT } },
3820
{ "mfear",      XSPR(31,339,282),  XSPR_MASK, PPC,	{ RT } },
3821
{ "mfpir",      XSPR(31,339,286),  XSPR_MASK, BOOKE,    { RT } },
3822
{ "mfpvr",      XSPR(31,339,287),  XSPR_MASK, PPC,	{ RT } },
3823
{ "mfdbsr",     XSPR(31,339,304),  XSPR_MASK, BOOKE,    { RT } },
3824
{ "mfdbsr",     XSPR(31,339,1008), XSPR_MASK, PPC403,	{ RT } },
3825
{ "mfdbcr0",    XSPR(31,339,308),  XSPR_MASK, BOOKE,    { RT } },
3826
{ "mfdbcr0",    XSPR(31,339,1010), XSPR_MASK, PPC405,	{ RT } },
3827
{ "mfdbcr1",    XSPR(31,339,309),  XSPR_MASK, BOOKE,    { RT } },
3828
{ "mfdbcr1",    XSPR(31,339,957),  XSPR_MASK, PPC405,	{ RT } },
3829
{ "mfdbcr2",    XSPR(31,339,310),  XSPR_MASK, BOOKE,    { RT } },
3830
{ "mfiac1",     XSPR(31,339,312),  XSPR_MASK, BOOKE,    { RT } },
3831
{ "mfiac1",     XSPR(31,339,1012), XSPR_MASK, PPC403,	{ RT } },
3832
{ "mfiac2",     XSPR(31,339,313),  XSPR_MASK, BOOKE,    { RT } },
3833
{ "mfiac2",     XSPR(31,339,1013), XSPR_MASK, PPC403,	{ RT } },
3834
{ "mfiac3",     XSPR(31,339,314),  XSPR_MASK, BOOKE,    { RT } },
3835
{ "mfiac3",     XSPR(31,339,948),  XSPR_MASK, PPC405,	{ RT } },
3836
{ "mfiac4",     XSPR(31,339,315),  XSPR_MASK, BOOKE,    { RT } },
3837
{ "mfiac4",     XSPR(31,339,949),  XSPR_MASK, PPC405,	{ RT } },
3838
{ "mfdac1",     XSPR(31,339,316),  XSPR_MASK, BOOKE,    { RT } },
3839
{ "mfdac1",     XSPR(31,339,1014), XSPR_MASK, PPC403,	{ RT } },
3840
{ "mfdac2",     XSPR(31,339,317),  XSPR_MASK, BOOKE,    { RT } },
3841
{ "mfdac2",     XSPR(31,339,1015), XSPR_MASK, PPC403,	{ RT } },
3842
{ "mfdvc1",     XSPR(31,339,318),  XSPR_MASK, BOOKE,    { RT } },
3843
{ "mfdvc1",     XSPR(31,339,950),  XSPR_MASK, PPC405,	{ RT } },
3844
{ "mfdvc2",     XSPR(31,339,319),  XSPR_MASK, BOOKE,    { RT } },
3845
{ "mfdvc2",     XSPR(31,339,951),  XSPR_MASK, PPC405,	{ RT } },
3846
{ "mftsr",      XSPR(31,339,336),  XSPR_MASK, BOOKE,    { RT } },
3847
{ "mftsr",      XSPR(31,339,984),  XSPR_MASK, PPC403,	{ RT } },
3848
{ "mftcr",      XSPR(31,339,340),  XSPR_MASK, BOOKE,    { RT } },
3849
{ "mftcr",      XSPR(31,339,986),  XSPR_MASK, PPC403,	{ RT } },
3850
{ "mfivor0",    XSPR(31,339,400),  XSPR_MASK, BOOKE,    { RT } },
3851
{ "mfivor1",    XSPR(31,339,401),  XSPR_MASK, BOOKE,    { RT } },
3852
{ "mfivor2",    XSPR(31,339,402),  XSPR_MASK, BOOKE,    { RT } },
3853
{ "mfivor3",    XSPR(31,339,403),  XSPR_MASK, BOOKE,    { RT } },
3854
{ "mfivor4",    XSPR(31,339,404),  XSPR_MASK, BOOKE,    { RT } },
3855
{ "mfivor5",    XSPR(31,339,405),  XSPR_MASK, BOOKE,    { RT } },
3856
{ "mfivor6",    XSPR(31,339,406),  XSPR_MASK, BOOKE,    { RT } },
3857
{ "mfivor7",    XSPR(31,339,407),  XSPR_MASK, BOOKE,    { RT } },
3858
{ "mfivor8",    XSPR(31,339,408),  XSPR_MASK, BOOKE,    { RT } },
3859
{ "mfivor9",    XSPR(31,339,409),  XSPR_MASK, BOOKE,    { RT } },
3860
{ "mfivor10",   XSPR(31,339,410),  XSPR_MASK, BOOKE,    { RT } },
3861
{ "mfivor11",   XSPR(31,339,411),  XSPR_MASK, BOOKE,    { RT } },
3862
{ "mfivor12",   XSPR(31,339,412),  XSPR_MASK, BOOKE,    { RT } },
3863
{ "mfivor13",   XSPR(31,339,413),  XSPR_MASK, BOOKE,    { RT } },
3864
{ "mfivor14",   XSPR(31,339,414),  XSPR_MASK, BOOKE,    { RT } },
3865
{ "mfivor15",   XSPR(31,339,415),  XSPR_MASK, BOOKE,    { RT } },
3866
{ "mfspefscr",  XSPR(31,339,512),  XSPR_MASK, PPCSPE,	{ RT } },
3867
{ "mfbbear",    XSPR(31,339,513),  XSPR_MASK, PPCBRLK,  { RT } },
3868
{ "mfbbtar",    XSPR(31,339,514),  XSPR_MASK, PPCBRLK,  { RT } },
3869
{ "mfivor32",   XSPR(31,339,528),  XSPR_MASK, PPCSPE,	{ RT } },
3870
{ "mfivor33",   XSPR(31,339,529),  XSPR_MASK, PPCSPE,	{ RT } },
3871
{ "mfivor34",   XSPR(31,339,530),  XSPR_MASK, PPCSPE,	{ RT } },
3872
{ "mfivor35",   XSPR(31,339,531),  XSPR_MASK, PPCPMR,	{ RT } },
3873
{ "mfibatu",    XSPR(31,339,528),  XSPRBAT_MASK, PPC,	{ RT, SPRBAT } },
3874
{ "mfibatl",    XSPR(31,339,529),  XSPRBAT_MASK, PPC,	{ RT, SPRBAT } },
3875
{ "mfdbatu",    XSPR(31,339,536),  XSPRBAT_MASK, PPC,	{ RT, SPRBAT } },
3876
{ "mfdbatl",    XSPR(31,339,537),  XSPRBAT_MASK, PPC,	{ RT, SPRBAT } },
3877
{ "mfic_cst",   XSPR(31,339,560),  XSPR_MASK, PPC860,	{ RT } },
3878
{ "mfic_adr",   XSPR(31,339,561),  XSPR_MASK, PPC860,	{ RT } },
3879
{ "mfic_dat",   XSPR(31,339,562),  XSPR_MASK, PPC860,	{ RT } },
3880
{ "mfdc_cst",   XSPR(31,339,568),  XSPR_MASK, PPC860,	{ RT } },
3881
{ "mfdc_adr",   XSPR(31,339,569),  XSPR_MASK, PPC860,	{ RT } },
3882
{ "mfmcsrr0",   XSPR(31,339,570),  XSPR_MASK, PPCRFMCI, { RT } },
3883
{ "mfdc_dat",   XSPR(31,339,570),  XSPR_MASK, PPC860,	{ RT } },
3884
{ "mfmcsrr1",   XSPR(31,339,571),  XSPR_MASK, PPCRFMCI, { RT } },
3885
{ "mfmcsr",     XSPR(31,339,572),  XSPR_MASK, PPCRFMCI, { RT } },
3886
{ "mfmcar",     XSPR(31,339,573),  XSPR_MASK, PPCRFMCI, { RT } },
3887
{ "mfdpdr",     XSPR(31,339,630),  XSPR_MASK, PPC860,	{ RT } },
3888
{ "mfdpir",     XSPR(31,339,631),  XSPR_MASK, PPC860,	{ RT } },
3889
{ "mfimmr",     XSPR(31,339,638),  XSPR_MASK, PPC860,	{ RT } },
3890
{ "mfmi_ctr",   XSPR(31,339,784),  XSPR_MASK, PPC860,	{ RT } },
3891
{ "mfmi_ap",    XSPR(31,339,786),  XSPR_MASK, PPC860,	{ RT } },
3892
{ "mfmi_epn",   XSPR(31,339,787),  XSPR_MASK, PPC860,	{ RT } },
3893
{ "mfmi_twc",   XSPR(31,339,789),  XSPR_MASK, PPC860,	{ RT } },
3894
{ "mfmi_rpn",   XSPR(31,339,790),  XSPR_MASK, PPC860,	{ RT } },
3895
{ "mfmd_ctr",   XSPR(31,339,792),  XSPR_MASK, PPC860,	{ RT } },
3896
{ "mfm_casid",  XSPR(31,339,793),  XSPR_MASK, PPC860,	{ RT } },
3897
{ "mfmd_ap",    XSPR(31,339,794),  XSPR_MASK, PPC860,	{ RT } },
3898
{ "mfmd_epn",   XSPR(31,339,795),  XSPR_MASK, PPC860,	{ RT } },
3899
{ "mfmd_twb",   XSPR(31,339,796),  XSPR_MASK, PPC860,	{ RT } },
3900
{ "mfmd_twc",   XSPR(31,339,797),  XSPR_MASK, PPC860,	{ RT } },
3901
{ "mfmd_rpn",   XSPR(31,339,798),  XSPR_MASK, PPC860,	{ RT } },
3902
{ "mfm_tw",     XSPR(31,339,799),  XSPR_MASK, PPC860,	{ RT } },
3903
{ "mfmi_dbcam", XSPR(31,339,816),  XSPR_MASK, PPC860,	{ RT } },
3904
{ "mfmi_dbram0",XSPR(31,339,817),  XSPR_MASK, PPC860,	{ RT } },
3905
{ "mfmi_dbram1",XSPR(31,339,818),  XSPR_MASK, PPC860,	{ RT } },
3906
{ "mfmd_dbcam", XSPR(31,339,824),  XSPR_MASK, PPC860,	{ RT } },
3907
{ "mfmd_dbram0",XSPR(31,339,825),  XSPR_MASK, PPC860,	{ RT } },
3908
{ "mfmd_dbram1",XSPR(31,339,826),  XSPR_MASK, PPC860,	{ RT } },
3909
{ "mfummcr0",   XSPR(31,339,936),  XSPR_MASK, PPC750,   { RT } },
3910
{ "mfupmc1",    XSPR(31,339,937),  XSPR_MASK, PPC750,   { RT } },
3911
{ "mfupmc2",    XSPR(31,339,938),  XSPR_MASK, PPC750,   { RT } },
3912
{ "mfusia",     XSPR(31,339,939),  XSPR_MASK, PPC750,   { RT } },
3913
{ "mfummcr1",   XSPR(31,339,940),  XSPR_MASK, PPC750,   { RT } },
3914
{ "mfupmc3",    XSPR(31,339,941),  XSPR_MASK, PPC750,   { RT } },
3915
{ "mfupmc4",    XSPR(31,339,942),  XSPR_MASK, PPC750,   { RT } },
3916
{ "mfzpr",   	XSPR(31,339,944),  XSPR_MASK, PPC403,	{ RT } },
3917
{ "mfccr0",  	XSPR(31,339,947),  XSPR_MASK, PPC405,	{ RT } },
3918
{ "mfmmcr0",	XSPR(31,339,952),  XSPR_MASK, PPC750,	{ RT } },
3919
{ "mfpmc1",	XSPR(31,339,953),  XSPR_MASK, PPC750,	{ RT } },
3920
{ "mfsgr",	XSPR(31,339,953),  XSPR_MASK, PPC403,	{ RT } },
3921
{ "mfpmc2",	XSPR(31,339,954),  XSPR_MASK, PPC750,	{ RT } },
3922
{ "mfdcwr", 	XSPR(31,339,954),  XSPR_MASK, PPC403,	{ RT } },
3923
{ "mfsia",	XSPR(31,339,955),  XSPR_MASK, PPC750,	{ RT } },
3924
{ "mfsler",	XSPR(31,339,955),  XSPR_MASK, PPC405,	{ RT } },
3925
{ "mfmmcr1",	XSPR(31,339,956),  XSPR_MASK, PPC750,	{ RT } },
3926
{ "mfsu0r",	XSPR(31,339,956),  XSPR_MASK, PPC405,	{ RT } },
3927
{ "mfpmc3",	XSPR(31,339,957),  XSPR_MASK, PPC750,	{ RT } },
3928
{ "mfpmc4",	XSPR(31,339,958),  XSPR_MASK, PPC750,	{ RT } },
3929
{ "mficdbdr",   XSPR(31,339,979),  XSPR_MASK, PPC403,   { RT } },
3930
{ "mfevpr",     XSPR(31,339,982),  XSPR_MASK, PPC403,	{ RT } },
3931
{ "mfcdbcr",    XSPR(31,339,983),  XSPR_MASK, PPC403,	{ RT } },
3932
{ "mfpit",      XSPR(31,339,987),  XSPR_MASK, PPC403,	{ RT } },
3933
{ "mftbhi",     XSPR(31,339,988),  XSPR_MASK, PPC403,	{ RT } },
3934
{ "mftblo",     XSPR(31,339,989),  XSPR_MASK, PPC403,	{ RT } },
3935
{ "mfsrr2",     XSPR(31,339,990),  XSPR_MASK, PPC403,	{ RT } },
3936
{ "mfsrr3",     XSPR(31,339,991),  XSPR_MASK, PPC403,	{ RT } },
3937
{ "mfl2cr",     XSPR(31,339,1017), XSPR_MASK, PPC750,   { RT } },
3938
{ "mfdccr",     XSPR(31,339,1018), XSPR_MASK, PPC403,	{ RT } },
3939
{ "mficcr",     XSPR(31,339,1019), XSPR_MASK, PPC403,	{ RT } },
3940
{ "mfictc",     XSPR(31,339,1019), XSPR_MASK, PPC750,   { RT } },
3941
{ "mfpbl1",     XSPR(31,339,1020), XSPR_MASK, PPC403,	{ RT } },
3942
{ "mfthrm1",    XSPR(31,339,1020), XSPR_MASK, PPC750,   { RT } },
3943
{ "mfpbu1",     XSPR(31,339,1021), XSPR_MASK, PPC403,	{ RT } },
3944
{ "mfthrm2",    XSPR(31,339,1021), XSPR_MASK, PPC750,   { RT } },
3945
{ "mfpbl2",     XSPR(31,339,1022), XSPR_MASK, PPC403,	{ RT } },
3946
{ "mfthrm3",    XSPR(31,339,1022), XSPR_MASK, PPC750,   { RT } },
3947
{ "mfpbu2",     XSPR(31,339,1023), XSPR_MASK, PPC403,	{ RT } },
3948
{ "mfspr",      X(31,339),	   X_MASK,    COM,	{ RT, SPR } },
3949

3950
{ "lwax",    X(31,341),	X_MASK,		PPC64,		{ RT, RA0, RB } },
3951

3952
{ "dst",     XDSS(31,342,0), XDSS_MASK,	PPCVEC,		{ RA, RB, STRM } },
3953
{ "dstt",    XDSS(31,342,1), XDSS_MASK,	PPCVEC,		{ RA, RB, STRM } },
3954

3955
{ "lhax",    X(31,343),	X_MASK,		COM,		{ RT, RA0, RB } },
3956

3957
{ "lhaxe",   X(31,351),	X_MASK,		BOOKE64,	{ RT, RA0, RB } },
3958

3959
{ "dstst",   XDSS(31,374,0), XDSS_MASK,	PPCVEC,		{ RA, RB, STRM } },
3960
{ "dststt",  XDSS(31,374,1), XDSS_MASK,	PPCVEC,		{ RA, RB, STRM } },
3961

3962
{ "dccci",   X(31,454),	XRT_MASK,	PPC403|PPC440,	{ RA, RB } },
3963

3964
{ "abs",     XO(31,360,0,0), XORB_MASK, M601,		{ RT, RA } },
3965
{ "abs.",    XO(31,360,0,1), XORB_MASK, M601,		{ RT, RA } },
3966
{ "abso",    XO(31,360,1,0), XORB_MASK, M601,		{ RT, RA } },
3967
{ "abso.",   XO(31,360,1,1), XORB_MASK, M601,		{ RT, RA } },
3968

3969
{ "divs",    XO(31,363,0,0), XO_MASK,	M601,		{ RT, RA, RB } },
3970
{ "divs.",   XO(31,363,0,1), XO_MASK,	M601,		{ RT, RA, RB } },
3971
{ "divso",   XO(31,363,1,0), XO_MASK,	M601,		{ RT, RA, RB } },
3972
{ "divso.",  XO(31,363,1,1), XO_MASK,	M601,		{ RT, RA, RB } },
3973

3974
{ "tlbia",   X(31,370),	0xffffffff,	PPC,		{ 0 } },
3975

3976
{ "lwaux",   X(31,373),	X_MASK,		PPC64,		{ RT, RAL, RB } },
3977

3978
{ "lhaux",   X(31,375),	X_MASK,		COM,		{ RT, RAL, RB } },
3979

3980
{ "lhauxe",  X(31,383),	X_MASK,		BOOKE64,	{ RT, RAL, RB } },
3981

3982
{ "mtdcrx",  X(31,387),	X_MASK,		BOOKE,		{ RA, RS } },
3983

3984
{ "dcblc",   X(31,390),	X_MASK,		PPCCHLK,	{ CT, RA, RB }},
3985

3986
{ "subfe64", XO(31,392,0,0), XO_MASK,	BOOKE64,	{ RT, RA, RB } },
3987
{ "subfe64o",XO(31,392,1,0), XO_MASK,	BOOKE64,	{ RT, RA, RB } },
3988

3989
{ "adde64",  XO(31,394,0,0), XO_MASK,	BOOKE64,	{ RT, RA, RB } },
3990
{ "adde64o", XO(31,394,1,0), XO_MASK,	BOOKE64,	{ RT, RA, RB } },
3991

3992
{ "dcblce",  X(31,398),	X_MASK,		PPCCHLK64,	{ CT, RA, RB }},
3993

3994
{ "slbmte",  X(31,402), XRA_MASK,	PPC64,		{ RS, RB } },
3995

3996
{ "sthx",    X(31,407),	X_MASK,		COM,		{ RS, RA0, RB } },
3997

3998
{ "cmpb",    X(31,508),	X_MASK,		POWER6,		{ RA, RS, RB } },
3999

4000
{ "lfqx",    X(31,791),	X_MASK,		POWER2,		{ FRT, RA, RB } },
4001

4002
{ "lfdpx",   X(31,791),	X_MASK,		POWER6,		{ FRT, RA, RB } },
4003

4004
{ "lfqux",   X(31,823),	X_MASK,		POWER2,		{ FRT, RA, RB } },
4005

4006
{ "stfqx",   X(31,919),	X_MASK,		POWER2,		{ FRS, RA, RB } },
4007

4008
{ "stfdpx",  X(31,919),	X_MASK,		POWER6,		{ FRS, RA, RB } },
4009

4010
{ "stfqux",  X(31,951),	X_MASK,		POWER2,		{ FRS, RA, RB } },
4011

4012
{ "orc",     XRC(31,412,0), X_MASK,	COM,		{ RA, RS, RB } },
4013
{ "orc.",    XRC(31,412,1), X_MASK,	COM,		{ RA, RS, RB } },
4014

4015
{ "sradi",   XS(31,413,0), XS_MASK,	PPC64,		{ RA, RS, SH6 } },
4016
{ "sradi.",  XS(31,413,1), XS_MASK,	PPC64,		{ RA, RS, SH6 } },
4017

4018
{ "sthxe",   X(31,415),	X_MASK,		BOOKE64,	{ RS, RA0, RB } },
4019

4020
{ "slbie",   X(31,434),	XRTRA_MASK,	PPC64,		{ RB } },
4021

4022
{ "ecowx",   X(31,438),	X_MASK,		PPC,		{ RT, RA, RB } },
4023

4024
{ "sthux",   X(31,439),	X_MASK,		COM,		{ RS, RAS, RB } },
4025

4026
{ "sthuxe",  X(31,447),	X_MASK,		BOOKE64,	{ RS, RAS, RB } },
4027

4028
{ "mr",	     XRC(31,444,0), X_MASK,	COM,		{ RA, RS, RBS } },
4029
{ "or",      XRC(31,444,0), X_MASK,	COM,		{ RA, RS, RB } },
4030
{ "mr.",     XRC(31,444,1), X_MASK,	COM,		{ RA, RS, RBS } },
4031
{ "or.",     XRC(31,444,1), X_MASK,	COM,		{ RA, RS, RB } },
4032

4033
{ "mtexisr",  XSPR(31,451,64),  XSPR_MASK, PPC403,	{ RS } },
4034
{ "mtexier",  XSPR(31,451,66),  XSPR_MASK, PPC403,	{ RS } },
4035
{ "mtbr0",    XSPR(31,451,128), XSPR_MASK, PPC403,	{ RS } },
4036
{ "mtbr1",    XSPR(31,451,129), XSPR_MASK, PPC403,	{ RS } },
4037
{ "mtbr2",    XSPR(31,451,130), XSPR_MASK, PPC403,	{ RS } },
4038
{ "mtbr3",    XSPR(31,451,131), XSPR_MASK, PPC403,	{ RS } },
4039
{ "mtbr4",    XSPR(31,451,132), XSPR_MASK, PPC403,	{ RS } },
4040
{ "mtbr5",    XSPR(31,451,133), XSPR_MASK, PPC403,	{ RS } },
4041
{ "mtbr6",    XSPR(31,451,134), XSPR_MASK, PPC403,	{ RS } },
4042
{ "mtbr7",    XSPR(31,451,135), XSPR_MASK, PPC403,	{ RS } },
4043
{ "mtbear",   XSPR(31,451,144), XSPR_MASK, PPC403,	{ RS } },
4044
{ "mtbesr",   XSPR(31,451,145), XSPR_MASK, PPC403,	{ RS } },
4045
{ "mtiocr",   XSPR(31,451,160), XSPR_MASK, PPC403,	{ RS } },
4046
{ "mtdmacr0", XSPR(31,451,192), XSPR_MASK, PPC403,	{ RS } },
4047
{ "mtdmact0", XSPR(31,451,193), XSPR_MASK, PPC403,	{ RS } },
4048
{ "mtdmada0", XSPR(31,451,194), XSPR_MASK, PPC403,	{ RS } },
4049
{ "mtdmasa0", XSPR(31,451,195), XSPR_MASK, PPC403,	{ RS } },
4050
{ "mtdmacc0", XSPR(31,451,196), XSPR_MASK, PPC403,	{ RS } },
4051
{ "mtdmacr1", XSPR(31,451,200), XSPR_MASK, PPC403,	{ RS } },
4052
{ "mtdmact1", XSPR(31,451,201), XSPR_MASK, PPC403,	{ RS } },
4053
{ "mtdmada1", XSPR(31,451,202), XSPR_MASK, PPC403,	{ RS } },
4054
{ "mtdmasa1", XSPR(31,451,203), XSPR_MASK, PPC403,	{ RS } },
4055
{ "mtdmacc1", XSPR(31,451,204), XSPR_MASK, PPC403,	{ RS } },
4056
{ "mtdmacr2", XSPR(31,451,208), XSPR_MASK, PPC403,	{ RS } },
4057
{ "mtdmact2", XSPR(31,451,209), XSPR_MASK, PPC403,	{ RS } },
4058
{ "mtdmada2", XSPR(31,451,210), XSPR_MASK, PPC403,	{ RS } },
4059
{ "mtdmasa2", XSPR(31,451,211), XSPR_MASK, PPC403,	{ RS } },
4060
{ "mtdmacc2", XSPR(31,451,212), XSPR_MASK, PPC403,	{ RS } },
4061
{ "mtdmacr3", XSPR(31,451,216), XSPR_MASK, PPC403,	{ RS } },
4062
{ "mtdmact3", XSPR(31,451,217), XSPR_MASK, PPC403,	{ RS } },
4063
{ "mtdmada3", XSPR(31,451,218), XSPR_MASK, PPC403,	{ RS } },
4064
{ "mtdmasa3", XSPR(31,451,219), XSPR_MASK, PPC403,	{ RS } },
4065
{ "mtdmacc3", XSPR(31,451,220), XSPR_MASK, PPC403,	{ RS } },
4066
{ "mtdmasr",  XSPR(31,451,224), XSPR_MASK, PPC403,	{ RS } },
4067
{ "mtdcr",    X(31,451),	X_MASK,	PPC403 | BOOKE,	{ SPR, RS } },
4068

4069
{ "subfze64",XO(31,456,0,0), XORB_MASK, BOOKE64,	{ RT, RA } },
4070
{ "subfze64o",XO(31,456,1,0), XORB_MASK, BOOKE64,	{ RT, RA } },
4071

4072
{ "divdu",   XO(31,457,0,0), XO_MASK,	PPC64,		{ RT, RA, RB } },
4073
{ "divdu.",  XO(31,457,0,1), XO_MASK,	PPC64,		{ RT, RA, RB } },
4074
{ "divduo",  XO(31,457,1,0), XO_MASK,	PPC64,		{ RT, RA, RB } },
4075
{ "divduo.", XO(31,457,1,1), XO_MASK,	PPC64,		{ RT, RA, RB } },
4076

4077
{ "addze64", XO(31,458,0,0), XORB_MASK, BOOKE64,	{ RT, RA } },
4078
{ "addze64o",XO(31,458,1,0), XORB_MASK, BOOKE64,	{ RT, RA } },
4079

4080
{ "divwu",   XO(31,459,0,0), XO_MASK,	PPC,		{ RT, RA, RB } },
4081
{ "divwu.",  XO(31,459,0,1), XO_MASK,	PPC,		{ RT, RA, RB } },
4082
{ "divwuo",  XO(31,459,1,0), XO_MASK,	PPC,		{ RT, RA, RB } },
4083
{ "divwuo.", XO(31,459,1,1), XO_MASK,	PPC,		{ RT, RA, RB } },
4084

4085
{ "mtmq",      XSPR(31,467,0),    XSPR_MASK, M601,	{ RS } },
4086
{ "mtxer",     XSPR(31,467,1),    XSPR_MASK, COM,	{ RS } },
4087
{ "mtlr",      XSPR(31,467,8),    XSPR_MASK, COM,	{ RS } },
4088
{ "mtctr",     XSPR(31,467,9),    XSPR_MASK, COM,	{ RS } },
4089
{ "mttid",     XSPR(31,467,17),   XSPR_MASK, POWER,	{ RS } },
4090
{ "mtdsisr",   XSPR(31,467,18),   XSPR_MASK, COM,	{ RS } },
4091
{ "mtdar",     XSPR(31,467,19),   XSPR_MASK, COM,	{ RS } },
4092
{ "mtrtcu",    XSPR(31,467,20),   XSPR_MASK, COM,	{ RS } },
4093
{ "mtrtcl",    XSPR(31,467,21),   XSPR_MASK, COM,	{ RS } },
4094
{ "mtdec",     XSPR(31,467,22),   XSPR_MASK, COM,	{ RS } },
4095
{ "mtsdr0",    XSPR(31,467,24),   XSPR_MASK, POWER,	{ RS } },
4096
{ "mtsdr1",    XSPR(31,467,25),   XSPR_MASK, COM,	{ RS } },
4097
{ "mtsrr0",    XSPR(31,467,26),   XSPR_MASK, COM,	{ RS } },
4098
{ "mtsrr1",    XSPR(31,467,27),   XSPR_MASK, COM,	{ RS } },
4099
{ "mtcfar",    XSPR(31,467,28),   XSPR_MASK, POWER6,	{ RS } },
4100
{ "mtpid",     XSPR(31,467,48),   XSPR_MASK, BOOKE,     { RS } },
4101
{ "mtpid",     XSPR(31,467,945),  XSPR_MASK, PPC403,	{ RS } },
4102
{ "mtdecar",   XSPR(31,467,54),   XSPR_MASK, BOOKE,     { RS } },
4103
{ "mtcsrr0",   XSPR(31,467,58),   XSPR_MASK, BOOKE,     { RS } },
4104
{ "mtcsrr1",   XSPR(31,467,59),   XSPR_MASK, BOOKE,     { RS } },
4105
{ "mtdear",    XSPR(31,467,61),   XSPR_MASK, BOOKE,     { RS } },
4106
{ "mtdear",    XSPR(31,467,981),  XSPR_MASK, PPC403,	{ RS } },
4107
{ "mtesr",     XSPR(31,467,62),   XSPR_MASK, BOOKE,     { RS } },
4108
{ "mtesr",     XSPR(31,467,980),  XSPR_MASK, PPC403,	{ RS } },
4109
{ "mtivpr",    XSPR(31,467,63),   XSPR_MASK, BOOKE,     { RS } },
4110
{ "mtcmpa",    XSPR(31,467,144),  XSPR_MASK, PPC860,	{ RS } },
4111
{ "mtcmpb",    XSPR(31,467,145),  XSPR_MASK, PPC860,	{ RS } },
4112
{ "mtcmpc",    XSPR(31,467,146),  XSPR_MASK, PPC860,	{ RS } },
4113
{ "mtcmpd",    XSPR(31,467,147),  XSPR_MASK, PPC860,	{ RS } },
4114
{ "mticr",     XSPR(31,467,148),  XSPR_MASK, PPC860,	{ RS } },
4115
{ "mtder",     XSPR(31,467,149),  XSPR_MASK, PPC860,	{ RS } },
4116
{ "mtcounta",  XSPR(31,467,150),  XSPR_MASK, PPC860,	{ RS } },
4117
{ "mtcountb",  XSPR(31,467,151),  XSPR_MASK, PPC860,	{ RS } },
4118
{ "mtcmpe",    XSPR(31,467,152),  XSPR_MASK, PPC860,	{ RS } },
4119
{ "mtcmpf",    XSPR(31,467,153),  XSPR_MASK, PPC860,	{ RS } },
4120
{ "mtcmpg",    XSPR(31,467,154),  XSPR_MASK, PPC860,	{ RS } },
4121
{ "mtcmph",    XSPR(31,467,155),  XSPR_MASK, PPC860,	{ RS } },
4122
{ "mtlctrl1",  XSPR(31,467,156),  XSPR_MASK, PPC860,	{ RS } },
4123
{ "mtlctrl2",  XSPR(31,467,157),  XSPR_MASK, PPC860,	{ RS } },
4124
{ "mtictrl",   XSPR(31,467,158),  XSPR_MASK, PPC860,	{ RS } },
4125
{ "mtbar",     XSPR(31,467,159),  XSPR_MASK, PPC860,	{ RS } },
4126
{ "mtvrsave",  XSPR(31,467,256),  XSPR_MASK, PPCVEC,	{ RS } },
4127
{ "mtusprg0",  XSPR(31,467,256),  XSPR_MASK, BOOKE,     { RS } },
4128
{ "mtsprg",    XSPR(31,467,256),  XSPRG_MASK,PPC,	{ SPRG, RS } },
4129
{ "mtsprg0",   XSPR(31,467,272),  XSPR_MASK, PPC,	{ RS } },
4130
{ "mtsprg1",   XSPR(31,467,273),  XSPR_MASK, PPC,	{ RS } },
4131
{ "mtsprg2",   XSPR(31,467,274),  XSPR_MASK, PPC,	{ RS } },
4132
{ "mtsprg3",   XSPR(31,467,275),  XSPR_MASK, PPC,	{ RS } },
4133
{ "mtsprg4",   XSPR(31,467,276),  XSPR_MASK, PPC405 | BOOKE, { RS } },
4134
{ "mtsprg5",   XSPR(31,467,277),  XSPR_MASK, PPC405 | BOOKE, { RS } },
4135
{ "mtsprg6",   XSPR(31,467,278),  XSPR_MASK, PPC405 | BOOKE, { RS } },
4136
{ "mtsprg7",   XSPR(31,467,279),  XSPR_MASK, PPC405 | BOOKE, { RS } },
4137
{ "mtasr",     XSPR(31,467,280),  XSPR_MASK, PPC64,	{ RS } },
4138
{ "mtear",     XSPR(31,467,282),  XSPR_MASK, PPC,	{ RS } },
4139
{ "mttbl",     XSPR(31,467,284),  XSPR_MASK, PPC,	{ RS } },
4140
{ "mttbu",     XSPR(31,467,285),  XSPR_MASK, PPC,	{ RS } },
4141
{ "mtdbsr",    XSPR(31,467,304),  XSPR_MASK, BOOKE,     { RS } },
4142
{ "mtdbsr",    XSPR(31,467,1008), XSPR_MASK, PPC403,	{ RS } },
4143
{ "mtdbcr0",   XSPR(31,467,308),  XSPR_MASK, BOOKE,     { RS } },
4144
{ "mtdbcr0",   XSPR(31,467,1010), XSPR_MASK, PPC405,	{ RS } },
4145
{ "mtdbcr1",   XSPR(31,467,309),  XSPR_MASK, BOOKE,     { RS } },
4146
{ "mtdbcr1",   XSPR(31,467,957),  XSPR_MASK, PPC405,	{ RS } },
4147
{ "mtdbcr2",   XSPR(31,467,310),  XSPR_MASK, BOOKE,     { RS } },
4148
{ "mtiac1",    XSPR(31,467,312),  XSPR_MASK, BOOKE,     { RS } },
4149
{ "mtiac1",    XSPR(31,467,1012), XSPR_MASK, PPC403,	{ RS } },
4150
{ "mtiac2",    XSPR(31,467,313),  XSPR_MASK, BOOKE,     { RS } },
4151
{ "mtiac2",    XSPR(31,467,1013), XSPR_MASK, PPC403,	{ RS } },
4152
{ "mtiac3",    XSPR(31,467,314),  XSPR_MASK, BOOKE,     { RS } },
4153
{ "mtiac3",    XSPR(31,467,948),  XSPR_MASK, PPC405,	{ RS } },
4154
{ "mtiac4",    XSPR(31,467,315),  XSPR_MASK, BOOKE,     { RS } },
4155
{ "mtiac4",    XSPR(31,467,949),  XSPR_MASK, PPC405,	{ RS } },
4156
{ "mtdac1",    XSPR(31,467,316),  XSPR_MASK, BOOKE,     { RS } },
4157
{ "mtdac1",    XSPR(31,467,1014), XSPR_MASK, PPC403,	{ RS } },
4158
{ "mtdac2",    XSPR(31,467,317),  XSPR_MASK, BOOKE,     { RS } },
4159
{ "mtdac2",    XSPR(31,467,1015), XSPR_MASK, PPC403,	{ RS } },
4160
{ "mtdvc1",    XSPR(31,467,318),  XSPR_MASK, BOOKE,     { RS } },
4161
{ "mtdvc1",    XSPR(31,467,950),  XSPR_MASK, PPC405,	{ RS } },
4162
{ "mtdvc2",    XSPR(31,467,319),  XSPR_MASK, BOOKE,     { RS } },
4163
{ "mtdvc2",    XSPR(31,467,951),  XSPR_MASK, PPC405,	{ RS } },
4164
{ "mttsr",     XSPR(31,467,336),  XSPR_MASK, BOOKE,     { RS } },
4165
{ "mttsr",     XSPR(31,467,984),  XSPR_MASK, PPC403,	{ RS } },
4166
{ "mttcr",     XSPR(31,467,340),  XSPR_MASK, BOOKE,     { RS } },
4167
{ "mttcr",     XSPR(31,467,986),  XSPR_MASK, PPC403,	{ RS } },
4168
{ "mtivor0",   XSPR(31,467,400),  XSPR_MASK, BOOKE,     { RS } },
4169
{ "mtivor1",   XSPR(31,467,401),  XSPR_MASK, BOOKE,     { RS } },
4170
{ "mtivor2",   XSPR(31,467,402),  XSPR_MASK, BOOKE,     { RS } },
4171
{ "mtivor3",   XSPR(31,467,403),  XSPR_MASK, BOOKE,     { RS } },
4172
{ "mtivor4",   XSPR(31,467,404),  XSPR_MASK, BOOKE,     { RS } },
4173
{ "mtivor5",   XSPR(31,467,405),  XSPR_MASK, BOOKE,     { RS } },
4174
{ "mtivor6",   XSPR(31,467,406),  XSPR_MASK, BOOKE,     { RS } },
4175
{ "mtivor7",   XSPR(31,467,407),  XSPR_MASK, BOOKE,     { RS } },
4176
{ "mtivor8",   XSPR(31,467,408),  XSPR_MASK, BOOKE,     { RS } },
4177
{ "mtivor9",   XSPR(31,467,409),  XSPR_MASK, BOOKE,     { RS } },
4178
{ "mtivor10",  XSPR(31,467,410),  XSPR_MASK, BOOKE,     { RS } },
4179
{ "mtivor11",  XSPR(31,467,411),  XSPR_MASK, BOOKE,     { RS } },
4180
{ "mtivor12",  XSPR(31,467,412),  XSPR_MASK, BOOKE,     { RS } },
4181
{ "mtivor13",  XSPR(31,467,413),  XSPR_MASK, BOOKE,     { RS } },
4182
{ "mtivor14",  XSPR(31,467,414),  XSPR_MASK, BOOKE,     { RS } },
4183
{ "mtivor15",  XSPR(31,467,415),  XSPR_MASK, BOOKE,     { RS } },
4184
{ "mtspefscr",  XSPR(31,467,512),  XSPR_MASK, PPCSPE,   { RS } },
4185
{ "mtbbear",   XSPR(31,467,513),  XSPR_MASK, PPCBRLK,   { RS } },
4186
{ "mtbbtar",   XSPR(31,467,514),  XSPR_MASK, PPCBRLK,  { RS } },
4187
{ "mtivor32",  XSPR(31,467,528),  XSPR_MASK, PPCSPE,	{ RS } },
4188
{ "mtivor33",  XSPR(31,467,529),  XSPR_MASK, PPCSPE,	{ RS } },
4189
{ "mtivor34",  XSPR(31,467,530),  XSPR_MASK, PPCSPE,	{ RS } },
4190
{ "mtivor35",  XSPR(31,467,531),  XSPR_MASK, PPCPMR,	{ RS } },
4191
{ "mtibatu",   XSPR(31,467,528),  XSPRBAT_MASK, PPC,	{ SPRBAT, RS } },
4192
{ "mtibatl",   XSPR(31,467,529),  XSPRBAT_MASK, PPC,	{ SPRBAT, RS } },
4193
{ "mtdbatu",   XSPR(31,467,536),  XSPRBAT_MASK, PPC,	{ SPRBAT, RS } },
4194
{ "mtdbatl",   XSPR(31,467,537),  XSPRBAT_MASK, PPC,	{ SPRBAT, RS } },
4195
{ "mtmcsrr0",  XSPR(31,467,570),  XSPR_MASK, PPCRFMCI,  { RS } },
4196
{ "mtmcsrr1",  XSPR(31,467,571),  XSPR_MASK, PPCRFMCI,  { RS } },
4197
{ "mtmcsr",    XSPR(31,467,572),  XSPR_MASK, PPCRFMCI,  { RS } },
4198
{ "mtummcr0",  XSPR(31,467,936),  XSPR_MASK, PPC750,    { RS } },
4199
{ "mtupmc1",   XSPR(31,467,937),  XSPR_MASK, PPC750,    { RS } },
4200
{ "mtupmc2",   XSPR(31,467,938),  XSPR_MASK, PPC750,    { RS } },
4201
{ "mtusia",    XSPR(31,467,939),  XSPR_MASK, PPC750,    { RS } },
4202
{ "mtummcr1",  XSPR(31,467,940),  XSPR_MASK, PPC750,    { RS } },
4203
{ "mtupmc3",   XSPR(31,467,941),  XSPR_MASK, PPC750,    { RS } },
4204
{ "mtupmc4",   XSPR(31,467,942),  XSPR_MASK, PPC750,    { RS } },
4205
{ "mtzpr",     XSPR(31,467,944),  XSPR_MASK, PPC403,	{ RS } },
4206
{ "mtccr0",    XSPR(31,467,947),  XSPR_MASK, PPC405,	{ RS } },
4207
{ "mtmmcr0",   XSPR(31,467,952),  XSPR_MASK, PPC750,    { RS } },
4208
{ "mtsgr",     XSPR(31,467,953),  XSPR_MASK, PPC403,	{ RS } },
4209
{ "mtpmc1",    XSPR(31,467,953),  XSPR_MASK, PPC750,    { RS } },
4210
{ "mtdcwr",    XSPR(31,467,954),  XSPR_MASK, PPC403,	{ RS } },
4211
{ "mtpmc2",    XSPR(31,467,954),  XSPR_MASK, PPC750,    { RS } },
4212
{ "mtsler",    XSPR(31,467,955),  XSPR_MASK, PPC405,	{ RS } },
4213
{ "mtsia",     XSPR(31,467,955),  XSPR_MASK, PPC750,    { RS } },
4214
{ "mtsu0r",    XSPR(31,467,956),  XSPR_MASK, PPC405,	{ RS } },
4215
{ "mtmmcr1",   XSPR(31,467,956),  XSPR_MASK, PPC750,    { RS } },
4216
{ "mtpmc3",    XSPR(31,467,957),  XSPR_MASK, PPC750,    { RS } },
4217
{ "mtpmc4",    XSPR(31,467,958),  XSPR_MASK, PPC750,    { RS } },
4218
{ "mticdbdr",  XSPR(31,467,979),  XSPR_MASK, PPC403,	{ RS } },
4219
{ "mtevpr",    XSPR(31,467,982),  XSPR_MASK, PPC403,	{ RS } },
4220
{ "mtcdbcr",   XSPR(31,467,983),  XSPR_MASK, PPC403,	{ RS } },
4221
{ "mtpit",     XSPR(31,467,987),  XSPR_MASK, PPC403,	{ RS } },
4222
{ "mttbhi",    XSPR(31,467,988),  XSPR_MASK, PPC403,	{ RS } },
4223
{ "mttblo",    XSPR(31,467,989),  XSPR_MASK, PPC403,	{ RS } },
4224
{ "mtsrr2",    XSPR(31,467,990),  XSPR_MASK, PPC403,	{ RS } },
4225
{ "mtsrr3",    XSPR(31,467,991),  XSPR_MASK, PPC403,	{ RS } },
4226
{ "mtl2cr",    XSPR(31,467,1017), XSPR_MASK, PPC750,    { RS } },
4227
{ "mtdccr",    XSPR(31,467,1018), XSPR_MASK, PPC403,	{ RS } },
4228
{ "mticcr",    XSPR(31,467,1019), XSPR_MASK, PPC403,	{ RS } },
4229
{ "mtictc",    XSPR(31,467,1019), XSPR_MASK, PPC750,    { RS } },
4230
{ "mtpbl1",    XSPR(31,467,1020), XSPR_MASK, PPC403,	{ RS } },
4231
{ "mtthrm1",   XSPR(31,467,1020), XSPR_MASK, PPC750,    { RS } },
4232
{ "mtpbu1",    XSPR(31,467,1021), XSPR_MASK, PPC403,	{ RS } },
4233
{ "mtthrm2",   XSPR(31,467,1021), XSPR_MASK, PPC750,    { RS } },
4234
{ "mtpbl2",    XSPR(31,467,1022), XSPR_MASK, PPC403,	{ RS } },
4235
{ "mtthrm3",   XSPR(31,467,1022), XSPR_MASK, PPC750,    { RS } },
4236
{ "mtpbu2",    XSPR(31,467,1023), XSPR_MASK, PPC403,	{ RS } },
4237
{ "mtspr",     X(31,467),	  X_MASK,    COM,	{ SPR, RS } },
4238

4239
{ "dcbi",    X(31,470),	XRT_MASK,	PPC,		{ RA, RB } },
4240

4241
{ "nand",    XRC(31,476,0), X_MASK,	COM,		{ RA, RS, RB } },
4242
{ "nand.",   XRC(31,476,1), X_MASK,	COM,		{ RA, RS, RB } },
4243

4244
{ "dcbie",   X(31,478),	XRT_MASK,	BOOKE64,	{ RA, RB } },
4245

4246
{ "dcread",  X(31,486),	X_MASK,		PPC403|PPC440,	{ RT, RA, RB }},
4247

4248
{ "mtpmr",   X(31,462),	X_MASK,		PPCPMR,		{ PMR, RS }},
4249

4250
{ "icbtls",  X(31,486),	X_MASK,		PPCCHLK,	{ CT, RA, RB }},
4251

4252
{ "nabs",    XO(31,488,0,0), XORB_MASK, M601,		{ RT, RA } },
4253
{ "subfme64",XO(31,488,0,0), XORB_MASK, BOOKE64,	{ RT, RA } },
4254
{ "nabs.",   XO(31,488,0,1), XORB_MASK, M601,		{ RT, RA } },
4255
{ "nabso",   XO(31,488,1,0), XORB_MASK, M601,		{ RT, RA } },
4256
{ "subfme64o",XO(31,488,1,0), XORB_MASK, BOOKE64,	{ RT, RA } },
4257
{ "nabso.",  XO(31,488,1,1), XORB_MASK, M601,		{ RT, RA } },
4258

4259
{ "divd",    XO(31,489,0,0), XO_MASK,	PPC64,		{ RT, RA, RB } },
4260
{ "divd.",   XO(31,489,0,1), XO_MASK,	PPC64,		{ RT, RA, RB } },
4261
{ "divdo",   XO(31,489,1,0), XO_MASK,	PPC64,		{ RT, RA, RB } },
4262
{ "divdo.",  XO(31,489,1,1), XO_MASK,	PPC64,		{ RT, RA, RB } },
4263

4264
{ "addme64", XO(31,490,0,0), XORB_MASK, BOOKE64,	{ RT, RA } },
4265
{ "addme64o",XO(31,490,1,0), XORB_MASK, BOOKE64,	{ RT, RA } },
4266

4267
{ "divw",    XO(31,491,0,0), XO_MASK,	PPC,		{ RT, RA, RB } },
4268
{ "divw.",   XO(31,491,0,1), XO_MASK,	PPC,		{ RT, RA, RB } },
4269
{ "divwo",   XO(31,491,1,0), XO_MASK,	PPC,		{ RT, RA, RB } },
4270
{ "divwo.",  XO(31,491,1,1), XO_MASK,	PPC,		{ RT, RA, RB } },
4271

4272
{ "icbtlse", X(31,494),	X_MASK,		PPCCHLK64,	{ CT, RA, RB }},
4273

4274
{ "slbia",   X(31,498),	0xffffffff,	PPC64,		{ 0 } },
4275

4276
{ "cli",     X(31,502), XRB_MASK,	POWER,		{ RT, RA } },
4277

4278
{ "stdcxe.", XRC(31,511,1), X_MASK,	BOOKE64,	{ RS, RA, RB } },
4279

4280
{ "mcrxr",   X(31,512),	XRARB_MASK|(3<<21), COM,	{ BF } },
4281

4282
{ "bblels",  X(31,518),	X_MASK,		PPCBRLK,	{ 0 }},
4283
{ "mcrxr64", X(31,544),	XRARB_MASK|(3<<21), BOOKE64,	{ BF } },
4284

4285
{ "clcs",    X(31,531), XRB_MASK,	M601,		{ RT, RA } },
4286

4287
{ "ldbrx",   X(31,532),	X_MASK,		CELL,		{ RT, RA0, RB } },
4288

4289
{ "lswx",    X(31,533),	X_MASK,		PPCCOM,		{ RT, RA0, RB } },
4290
{ "lsx",     X(31,533),	X_MASK,		PWRCOM,		{ RT, RA, RB } },
4291

4292
{ "lwbrx",   X(31,534),	X_MASK,		PPCCOM,		{ RT, RA0, RB } },
4293
{ "lbrx",    X(31,534),	X_MASK,		PWRCOM,		{ RT, RA, RB } },
4294

4295
{ "lfsx",    X(31,535),	X_MASK,		COM,		{ FRT, RA0, RB } },
4296

4297
{ "srw",     XRC(31,536,0), X_MASK,	PPCCOM,		{ RA, RS, RB } },
4298
{ "sr",      XRC(31,536,0), X_MASK,	PWRCOM,		{ RA, RS, RB } },
4299
{ "srw.",    XRC(31,536,1), X_MASK,	PPCCOM,		{ RA, RS, RB } },
4300
{ "sr.",     XRC(31,536,1), X_MASK,	PWRCOM,		{ RA, RS, RB } },
4301

4302
{ "rrib",    XRC(31,537,0), X_MASK,	M601,		{ RA, RS, RB } },
4303
{ "rrib.",   XRC(31,537,1), X_MASK,	M601,		{ RA, RS, RB } },
4304

4305
{ "srd",     XRC(31,539,0), X_MASK,	PPC64,		{ RA, RS, RB } },
4306
{ "srd.",    XRC(31,539,1), X_MASK,	PPC64,		{ RA, RS, RB } },
4307

4308
{ "maskir",  XRC(31,541,0), X_MASK,	M601,		{ RA, RS, RB } },
4309
{ "maskir.", XRC(31,541,1), X_MASK,	M601,		{ RA, RS, RB } },
4310

4311
{ "lwbrxe",  X(31,542),	X_MASK,		BOOKE64,	{ RT, RA0, RB } },
4312

4313
{ "lfsxe",   X(31,543),	X_MASK,		BOOKE64,	{ FRT, RA0, RB } },
4314

4315
{ "bbelr",   X(31,550),	X_MASK,		PPCBRLK,	{ 0 }},
4316

4317
{ "tlbsync", X(31,566),	0xffffffff,	PPC,		{ 0 } },
4318

4319
{ "lfsux",   X(31,567),	X_MASK,		COM,		{ FRT, RAS, RB } },
4320

4321
{ "lfsuxe",  X(31,575),	X_MASK,		BOOKE64,	{ FRT, RAS, RB } },
4322

4323
{ "mfsr",    X(31,595),	XRB_MASK|(1<<20), COM32,	{ RT, SR } },
4324

4325
{ "lswi",    X(31,597),	X_MASK,		PPCCOM,		{ RT, RA0, NB } },
4326
{ "lsi",     X(31,597),	X_MASK,		PWRCOM,		{ RT, RA0, NB } },
4327

4328
{ "lwsync",  XSYNC(31,598,1), 0xffffffff, PPC,		{ 0 } },
4329
{ "ptesync", XSYNC(31,598,2), 0xffffffff, PPC64,	{ 0 } },
4330
{ "msync",   X(31,598), 0xffffffff,	BOOKE,		{ 0 } },
4331
{ "sync",    X(31,598), XSYNC_MASK,	PPCCOM,		{ LS } },
4332
{ "dcs",     X(31,598), 0xffffffff,	PWRCOM,		{ 0 } },
4333

4334
{ "lfdx",    X(31,599), X_MASK,		COM,		{ FRT, RA0, RB } },
4335

4336
{ "lfdxe",   X(31,607), X_MASK,		BOOKE64,	{ FRT, RA0, RB } },
4337

4338
{ "mffgpr",  XRC(31,607,0), XRA_MASK,	POWER6,		{ FRT, RB } },
4339

4340
{ "mfsri",   X(31,627), X_MASK,		PWRCOM,		{ RT, RA, RB } },
4341

4342
{ "dclst",   X(31,630), XRB_MASK,	PWRCOM,		{ RS, RA } },
4343

4344
{ "lfdux",   X(31,631), X_MASK,		COM,		{ FRT, RAS, RB } },
4345

4346
{ "lfduxe",  X(31,639), X_MASK,		BOOKE64,	{ FRT, RAS, RB } },
4347

4348
{ "mfsrin",  X(31,659), XRA_MASK,	PPC32,		{ RT, RB } },
4349

4350
{ "stdbrx",  X(31,660), X_MASK,		CELL,		{ RS, RA0, RB } },
4351

4352
{ "stswx",   X(31,661), X_MASK,		PPCCOM,		{ RS, RA0, RB } },
4353
{ "stsx",    X(31,661), X_MASK,		PWRCOM,		{ RS, RA0, RB } },
4354

4355
{ "stwbrx",  X(31,662), X_MASK,		PPCCOM,		{ RS, RA0, RB } },
4356
{ "stbrx",   X(31,662), X_MASK,		PWRCOM,		{ RS, RA0, RB } },
4357

4358
{ "stfsx",   X(31,663), X_MASK,		COM,		{ FRS, RA0, RB } },
4359

4360
{ "srq",     XRC(31,664,0), X_MASK,	M601,		{ RA, RS, RB } },
4361
{ "srq.",    XRC(31,664,1), X_MASK,	M601,		{ RA, RS, RB } },
4362

4363
{ "sre",     XRC(31,665,0), X_MASK,	M601,		{ RA, RS, RB } },
4364
{ "sre.",    XRC(31,665,1), X_MASK,	M601,		{ RA, RS, RB } },
4365

4366
{ "stwbrxe", X(31,670), X_MASK,		BOOKE64,	{ RS, RA0, RB } },
4367

4368
{ "stfsxe",  X(31,671), X_MASK,		BOOKE64,	{ FRS, RA0, RB } },
4369

4370
{ "stfsux",  X(31,695),	X_MASK,		COM,		{ FRS, RAS, RB } },
4371

4372
{ "sriq",    XRC(31,696,0), X_MASK,	M601,		{ RA, RS, SH } },
4373
{ "sriq.",   XRC(31,696,1), X_MASK,	M601,		{ RA, RS, SH } },
4374

4375
{ "stfsuxe", X(31,703),	X_MASK,		BOOKE64,	{ FRS, RAS, RB } },
4376

4377
{ "stswi",   X(31,725),	X_MASK,		PPCCOM,		{ RS, RA0, NB } },
4378
{ "stsi",    X(31,725),	X_MASK,		PWRCOM,		{ RS, RA0, NB } },
4379

4380
{ "stfdx",   X(31,727),	X_MASK,		COM,		{ FRS, RA0, RB } },
4381

4382
{ "srlq",    XRC(31,728,0), X_MASK,	M601,		{ RA, RS, RB } },
4383
{ "srlq.",   XRC(31,728,1), X_MASK,	M601,		{ RA, RS, RB } },
4384

4385
{ "sreq",    XRC(31,729,0), X_MASK,	M601,		{ RA, RS, RB } },
4386
{ "sreq.",   XRC(31,729,1), X_MASK,	M601,		{ RA, RS, RB } },
4387

4388
{ "stfdxe",  X(31,735),	X_MASK,		BOOKE64,	{ FRS, RA0, RB } },
4389

4390
{ "mftgpr",  XRC(31,735,0), XRA_MASK,	POWER6,		{ RT, FRB } },
4391

4392
{ "dcba",    X(31,758),	XRT_MASK,	PPC405 | BOOKE,	{ RA, RB } },
4393

4394
{ "stfdux",  X(31,759),	X_MASK,		COM,		{ FRS, RAS, RB } },
4395

4396
{ "srliq",   XRC(31,760,0), X_MASK,	M601,		{ RA, RS, SH } },
4397
{ "srliq.",  XRC(31,760,1), X_MASK,	M601,		{ RA, RS, SH } },
4398

4399
{ "dcbae",   X(31,766),	XRT_MASK,	BOOKE64,	{ RA, RB } },
4400

4401
{ "stfduxe", X(31,767),	X_MASK,		BOOKE64,	{ FRS, RAS, RB } },
4402

4403
{ "tlbivax", X(31,786),	XRT_MASK,	BOOKE,		{ RA, RB } },
4404
{ "tlbivaxe",X(31,787),	XRT_MASK,	BOOKE64,	{ RA, RB } },
4405

4406
{ "lwzcix",  X(31,789),	X_MASK,		POWER6,		{ RT, RA0, RB } },
4407

4408
{ "lhbrx",   X(31,790),	X_MASK,		COM,		{ RT, RA0, RB } },
4409

4410
{ "sraw",    XRC(31,792,0), X_MASK,	PPCCOM,		{ RA, RS, RB } },
4411
{ "sra",     XRC(31,792,0), X_MASK,	PWRCOM,		{ RA, RS, RB } },
4412
{ "sraw.",   XRC(31,792,1), X_MASK,	PPCCOM,		{ RA, RS, RB } },
4413
{ "sra.",    XRC(31,792,1), X_MASK,	PWRCOM,		{ RA, RS, RB } },
4414

4415
{ "srad",    XRC(31,794,0), X_MASK,	PPC64,		{ RA, RS, RB } },
4416
{ "srad.",   XRC(31,794,1), X_MASK,	PPC64,		{ RA, RS, RB } },
4417

4418
{ "lhbrxe",  X(31,798),	X_MASK,		BOOKE64,	{ RT, RA0, RB } },
4419

4420
{ "ldxe",    X(31,799),	X_MASK,		BOOKE64,	{ RT, RA0, RB } },
4421
{ "lduxe",   X(31,831),	X_MASK,		BOOKE64,	{ RT, RA0, RB } },
4422

4423
{ "rac",     X(31,818),	X_MASK,		PWRCOM,		{ RT, RA, RB } },
4424

4425
{ "lhzcix",  X(31,821),	X_MASK,		POWER6,		{ RT, RA0, RB } },
4426

4427
{ "dss",     XDSS(31,822,0), XDSS_MASK,	PPCVEC,		{ STRM } },
4428
{ "dssall",  XDSS(31,822,1), XDSS_MASK,	PPCVEC,		{ 0 } },
4429

4430
{ "srawi",   XRC(31,824,0), X_MASK,	PPCCOM,		{ RA, RS, SH } },
4431
{ "srai",    XRC(31,824,0), X_MASK,	PWRCOM,		{ RA, RS, SH } },
4432
{ "srawi.",  XRC(31,824,1), X_MASK,	PPCCOM,		{ RA, RS, SH } },
4433
{ "srai.",   XRC(31,824,1), X_MASK,	PWRCOM,		{ RA, RS, SH } },
4434

4435
{ "slbmfev", X(31,851), XRA_MASK,	PPC64,		{ RT, RB } },
4436

4437
{ "lbzcix",  X(31,853),	X_MASK,		POWER6,		{ RT, RA0, RB } },
4438

4439
{ "mbar",    X(31,854),	X_MASK,		BOOKE,		{ MO } },
4440
{ "eieio",   X(31,854),	0xffffffff,	PPC,		{ 0 } },
4441

4442
{ "lfiwax",  X(31,855),	X_MASK,		POWER6,		{ FRT, RA0, RB } },
4443

4444
{ "ldcix",   X(31,885),	X_MASK,		POWER6,		{ RT, RA0, RB } },
4445

4446
{ "tlbsx",   XRC(31,914,0), X_MASK, 	PPC403|BOOKE,	{ RTO, RA, RB } },
4447
{ "tlbsx.",  XRC(31,914,1), X_MASK, 	PPC403|BOOKE,	{ RTO, RA, RB } },
4448
{ "tlbsxe",  XRC(31,915,0), X_MASK,	BOOKE64,	{ RA, RB } },
4449
{ "tlbsxe.", XRC(31,915,1), X_MASK,	BOOKE64,	{ RA, RB } },
4450

4451
{ "slbmfee", X(31,915), XRA_MASK,	PPC64,		{ RT, RB } },
4452

4453
{ "stwcix",  X(31,917),	X_MASK,		POWER6,		{ RS, RA0, RB } },
4454

4455
{ "sthbrx",  X(31,918),	X_MASK,		COM,		{ RS, RA0, RB } },
4456

4457
{ "sraq",    XRC(31,920,0), X_MASK,	M601,		{ RA, RS, RB } },
4458
{ "sraq.",   XRC(31,920,1), X_MASK,	M601,		{ RA, RS, RB } },
4459

4460
{ "srea",    XRC(31,921,0), X_MASK,	M601,		{ RA, RS, RB } },
4461
{ "srea.",   XRC(31,921,1), X_MASK,	M601,		{ RA, RS, RB } },
4462

4463
{ "extsh",   XRC(31,922,0), XRB_MASK,	PPCCOM,		{ RA, RS } },
4464
{ "exts",    XRC(31,922,0), XRB_MASK,	PWRCOM,		{ RA, RS } },
4465
{ "extsh.",  XRC(31,922,1), XRB_MASK,	PPCCOM,		{ RA, RS } },
4466
{ "exts.",   XRC(31,922,1), XRB_MASK,	PWRCOM,		{ RA, RS } },
4467

4468
{ "sthbrxe", X(31,926),	X_MASK,		BOOKE64,	{ RS, RA0, RB } },
4469

4470
{ "stdxe",   X(31,927), X_MASK,		BOOKE64,	{ RS, RA0, RB } },
4471

4472
{ "tlbrehi", XTLB(31,946,0), XTLB_MASK,	PPC403,		{ RT, RA } },
4473
{ "tlbrelo", XTLB(31,946,1), XTLB_MASK,	PPC403,		{ RT, RA } },
4474
{ "tlbre",   X(31,946),	X_MASK,		PPC403|BOOKE,	{ RSO, RAOPT, SHO } },
4475

4476
{ "sthcix",  X(31,949),	X_MASK,		POWER6,		{ RS, RA0, RB } },
4477

4478
{ "sraiq",   XRC(31,952,0), X_MASK,	M601,		{ RA, RS, SH } },
4479
{ "sraiq.",  XRC(31,952,1), X_MASK,	M601,		{ RA, RS, SH } },
4480

4481
{ "extsb",   XRC(31,954,0), XRB_MASK,	PPC,		{ RA, RS} },
4482
{ "extsb.",  XRC(31,954,1), XRB_MASK,	PPC,		{ RA, RS} },
4483

4484
{ "stduxe",  X(31,959),	X_MASK,		BOOKE64,	{ RS, RAS, RB } },
4485

4486
{ "iccci",   X(31,966),	XRT_MASK,	PPC403|PPC440,	{ RA, RB } },
4487

4488
{ "tlbwehi", XTLB(31,978,0), XTLB_MASK,	PPC403,		{ RT, RA } },
4489
{ "tlbwelo", XTLB(31,978,1), XTLB_MASK,	PPC403,		{ RT, RA } },
4490
{ "tlbwe",   X(31,978),	X_MASK,		PPC403|BOOKE,	{ RSO, RAOPT, SHO } },
4491
{ "tlbld",   X(31,978),	XRTRA_MASK,	PPC,		{ RB } },
4492

4493
{ "stbcix",  X(31,981),	X_MASK,		POWER6,		{ RS, RA0, RB } },
4494

4495
{ "icbi",    X(31,982),	XRT_MASK,	PPC,		{ RA, RB } },
4496

4497
{ "stfiwx",  X(31,983),	X_MASK,		PPC,		{ FRS, RA0, RB } },
4498

4499
{ "extsw",   XRC(31,986,0), XRB_MASK,	PPC64 | BOOKE64,{ RA, RS } },
4500
{ "extsw.",  XRC(31,986,1), XRB_MASK,	PPC64,		{ RA, RS } },
4501

4502
{ "icread",  X(31,998),	XRT_MASK,	PPC403|PPC440,	{ RA, RB } },
4503

4504
{ "icbie",   X(31,990),	XRT_MASK,	BOOKE64,	{ RA, RB } },
4505
{ "stfiwxe", X(31,991),	X_MASK,		BOOKE64,	{ FRS, RA0, RB } },
4506

4507
{ "tlbli",   X(31,1010), XRTRA_MASK,	PPC,		{ RB } },
4508

4509
{ "stdcix",  X(31,1013), X_MASK,	POWER6,		{ RS, RA0, RB } },
4510

4511
{ "dcbzl",   XOPL(31,1014,1), XRT_MASK,POWER4,            { RA, RB } },
4512
{ "dcbz",    X(31,1014), XRT_MASK,	PPC,		{ RA, RB } },
4513
{ "dclz",    X(31,1014), XRT_MASK,	PPC,		{ RA, RB } },
4514

4515
{ "dcbze",   X(31,1022), XRT_MASK,	BOOKE64,	{ RA, RB } },
4516

4517
{ "lvebx",   X(31,   7), X_MASK,	PPCVEC,		{ VD, RA, RB } },
4518
{ "lvehx",   X(31,  39), X_MASK,	PPCVEC,		{ VD, RA, RB } },
4519
{ "lvewx",   X(31,  71), X_MASK,	PPCVEC,		{ VD, RA, RB } },
4520
{ "lvsl",    X(31,   6), X_MASK,	PPCVEC,		{ VD, RA, RB } },
4521
{ "lvsr",    X(31,  38), X_MASK,	PPCVEC,		{ VD, RA, RB } },
4522
{ "lvx",     X(31, 103), X_MASK,	PPCVEC,		{ VD, RA, RB } },
4523
{ "lvxl",    X(31, 359), X_MASK,	PPCVEC,		{ VD, RA, RB } },
4524
{ "stvebx",  X(31, 135), X_MASK,	PPCVEC,		{ VS, RA, RB } },
4525
{ "stvehx",  X(31, 167), X_MASK,	PPCVEC,		{ VS, RA, RB } },
4526
{ "stvewx",  X(31, 199), X_MASK,	PPCVEC,		{ VS, RA, RB } },
4527
{ "stvx",    X(31, 231), X_MASK,	PPCVEC,		{ VS, RA, RB } },
4528
{ "stvxl",   X(31, 487), X_MASK,	PPCVEC,		{ VS, RA, RB } },
4529

4530
/* New load/store left/right index vector instructions that are in the Cell only.  */
4531
{ "lvlx",    X(31, 519), X_MASK,	CELL,		{ VD, RA0, RB } },
4532
{ "lvlxl",   X(31, 775), X_MASK,	CELL,		{ VD, RA0, RB } },
4533
{ "lvrx",    X(31, 551), X_MASK,	CELL,		{ VD, RA0, RB } },
4534
{ "lvrxl",   X(31, 807), X_MASK,	CELL,		{ VD, RA0, RB } },
4535
{ "stvlx",   X(31, 647), X_MASK,	CELL,		{ VS, RA0, RB } },
4536
{ "stvlxl",  X(31, 903), X_MASK,	CELL,		{ VS, RA0, RB } },
4537
{ "stvrx",   X(31, 679), X_MASK,	CELL,		{ VS, RA0, RB } },
4538
{ "stvrxl",  X(31, 935), X_MASK,	CELL,		{ VS, RA0, RB } },
4539

4540
{ "lwz",     OP(32),	OP_MASK,	PPCCOM,		{ RT, D, RA0 } },
4541
{ "l",	     OP(32),	OP_MASK,	PWRCOM,		{ RT, D, RA0 } },
4542

4543
{ "lwzu",    OP(33),	OP_MASK,	PPCCOM,		{ RT, D, RAL } },
4544
{ "lu",      OP(33),	OP_MASK,	PWRCOM,		{ RT, D, RA0 } },
4545

4546
{ "lbz",     OP(34),	OP_MASK,	COM,		{ RT, D, RA0 } },
4547

4548
{ "lbzu",    OP(35),	OP_MASK,	COM,		{ RT, D, RAL } },
4549

4550
{ "stw",     OP(36),	OP_MASK,	PPCCOM,		{ RS, D, RA0 } },
4551
{ "st",      OP(36),	OP_MASK,	PWRCOM,		{ RS, D, RA0 } },
4552

4553
{ "stwu",    OP(37),	OP_MASK,	PPCCOM,		{ RS, D, RAS } },
4554
{ "stu",     OP(37),	OP_MASK,	PWRCOM,		{ RS, D, RA0 } },
4555

4556
{ "stb",     OP(38),	OP_MASK,	COM,		{ RS, D, RA0 } },
4557

4558
{ "stbu",    OP(39),	OP_MASK,	COM,		{ RS, D, RAS } },
4559

4560
{ "lhz",     OP(40),	OP_MASK,	COM,		{ RT, D, RA0 } },
4561

4562
{ "lhzu",    OP(41),	OP_MASK,	COM,		{ RT, D, RAL } },
4563

4564
{ "lha",     OP(42),	OP_MASK,	COM,		{ RT, D, RA0 } },
4565

4566
{ "lhau",    OP(43),	OP_MASK,	COM,		{ RT, D, RAL } },
4567

4568
{ "sth",     OP(44),	OP_MASK,	COM,		{ RS, D, RA0 } },
4569

4570
{ "sthu",    OP(45),	OP_MASK,	COM,		{ RS, D, RAS } },
4571

4572
{ "lmw",     OP(46),	OP_MASK,	PPCCOM,		{ RT, D, RAM } },
4573
{ "lm",      OP(46),	OP_MASK,	PWRCOM,		{ RT, D, RA0 } },
4574

4575
{ "stmw",    OP(47),	OP_MASK,	PPCCOM,		{ RS, D, RA0 } },
4576
{ "stm",     OP(47),	OP_MASK,	PWRCOM,		{ RS, D, RA0 } },
4577

4578
{ "lfs",     OP(48),	OP_MASK,	COM,		{ FRT, D, RA0 } },
4579

4580
{ "lfsu",    OP(49),	OP_MASK,	COM,		{ FRT, D, RAS } },
4581

4582
{ "lfd",     OP(50),	OP_MASK,	COM,		{ FRT, D, RA0 } },
4583

4584
{ "lfdu",    OP(51),	OP_MASK,	COM,		{ FRT, D, RAS } },
4585

4586
{ "stfs",    OP(52),	OP_MASK,	COM,		{ FRS, D, RA0 } },
4587

4588
{ "stfsu",   OP(53),	OP_MASK,	COM,		{ FRS, D, RAS } },
4589

4590
{ "stfd",    OP(54),	OP_MASK,	COM,		{ FRS, D, RA0 } },
4591

4592
{ "stfdu",   OP(55),	OP_MASK,	COM,		{ FRS, D, RAS } },
4593

4594
{ "lq",      OP(56),	OP_MASK,	POWER4,		{ RTQ, DQ, RAQ } },
4595

4596
{ "lfq",     OP(56),	OP_MASK,	POWER2,		{ FRT, D, RA0 } },
4597

4598
{ "lfqu",    OP(57),	OP_MASK,	POWER2,		{ FRT, D, RA0 } },
4599

4600
{ "lfdp",    OP(57),	OP_MASK,	POWER6,		{ FRT, D, RA0 } },
4601

4602
{ "lbze",    DEO(58,0), DE_MASK,	BOOKE64,	{ RT, DE, RA0 } },
4603
{ "lbzue",   DEO(58,1), DE_MASK,	BOOKE64,	{ RT, DE, RAL } },
4604
{ "lhze",    DEO(58,2), DE_MASK,	BOOKE64,	{ RT, DE, RA0 } },
4605
{ "lhzue",   DEO(58,3), DE_MASK,	BOOKE64,	{ RT, DE, RAL } },
4606
{ "lhae",    DEO(58,4), DE_MASK,	BOOKE64,	{ RT, DE, RA0 } },
4607
{ "lhaue",   DEO(58,5), DE_MASK,	BOOKE64,	{ RT, DE, RAL } },
4608
{ "lwze",    DEO(58,6), DE_MASK,	BOOKE64,	{ RT, DE, RA0 } },
4609
{ "lwzue",   DEO(58,7), DE_MASK,	BOOKE64,	{ RT, DE, RAL } },
4610
{ "stbe",    DEO(58,8), DE_MASK,	BOOKE64,	{ RS, DE, RA0 } },
4611
{ "stbue",   DEO(58,9), DE_MASK,	BOOKE64,	{ RS, DE, RAS } },
4612
{ "sthe",    DEO(58,10), DE_MASK,	BOOKE64,	{ RS, DE, RA0 } },
4613
{ "sthue",   DEO(58,11), DE_MASK,	BOOKE64,	{ RS, DE, RAS } },
4614
{ "stwe",    DEO(58,14), DE_MASK,	BOOKE64,	{ RS, DE, RA0 } },
4615
{ "stwue",   DEO(58,15), DE_MASK,	BOOKE64,	{ RS, DE, RAS } },
4616

4617
{ "ld",      DSO(58,0),	DS_MASK,	PPC64,		{ RT, DS, RA0 } },
4618

4619
{ "ldu",     DSO(58,1), DS_MASK,	PPC64,		{ RT, DS, RAL } },
4620

4621
{ "lwa",     DSO(58,2), DS_MASK,	PPC64,		{ RT, DS, RA0 } },
4622

4623
{ "dadd",    XRC(59,2,0), X_MASK,	POWER6,		{ FRT, FRA, FRB } },
4624
{ "dadd.",   XRC(59,2,1), X_MASK,	POWER6,		{ FRT, FRA, FRB } },
4625

4626
{ "dqua",    ZRC(59,3,0), Z_MASK,	POWER6,		{ FRT, FRA, FRB, RMC } },
4627
{ "dqua.",   ZRC(59,3,1), Z_MASK,	POWER6,		{ FRT, FRA, FRB, RMC } },
4628

4629
{ "fdivs",   A(59,18,0), AFRC_MASK,	PPC,		{ FRT, FRA, FRB } },
4630
{ "fdivs.",  A(59,18,1), AFRC_MASK,	PPC,		{ FRT, FRA, FRB } },
4631

4632
{ "fsubs",   A(59,20,0), AFRC_MASK,	PPC,		{ FRT, FRA, FRB } },
4633
{ "fsubs.",  A(59,20,1), AFRC_MASK,	PPC,		{ FRT, FRA, FRB } },
4634

4635
{ "fadds",   A(59,21,0), AFRC_MASK,	PPC,		{ FRT, FRA, FRB } },
4636
{ "fadds.",  A(59,21,1), AFRC_MASK,	PPC,		{ FRT, FRA, FRB } },
4637

4638
{ "fsqrts",  A(59,22,0), AFRAFRC_MASK,	PPC,		{ FRT, FRB } },
4639
{ "fsqrts.", A(59,22,1), AFRAFRC_MASK,	PPC,		{ FRT, FRB } },
4640

4641
{ "fres",    A(59,24,0), AFRALFRC_MASK,	PPC,		{ FRT, FRB, A_L } },
4642
{ "fres.",   A(59,24,1), AFRALFRC_MASK,	PPC,		{ FRT, FRB, A_L } },
4643

4644
{ "fmuls",   A(59,25,0), AFRB_MASK,	PPC,		{ FRT, FRA, FRC } },
4645
{ "fmuls.",  A(59,25,1), AFRB_MASK,	PPC,		{ FRT, FRA, FRC } },
4646

4647
{ "frsqrtes", A(59,26,0), AFRALFRC_MASK,POWER5,		{ FRT, FRB, A_L } },
4648
{ "frsqrtes.",A(59,26,1), AFRALFRC_MASK,POWER5,		{ FRT, FRB, A_L } },
4649

4650
{ "fmsubs",  A(59,28,0), A_MASK,	PPC,		{ FRT,FRA,FRC,FRB } },
4651
{ "fmsubs.", A(59,28,1), A_MASK,	PPC,		{ FRT,FRA,FRC,FRB } },
4652

4653
{ "fmadds",  A(59,29,0), A_MASK,	PPC,		{ FRT,FRA,FRC,FRB } },
4654
{ "fmadds.", A(59,29,1), A_MASK,	PPC,		{ FRT,FRA,FRC,FRB } },
4655

4656
{ "fnmsubs", A(59,30,0), A_MASK,	PPC,		{ FRT,FRA,FRC,FRB } },
4657
{ "fnmsubs.",A(59,30,1), A_MASK,	PPC,		{ FRT,FRA,FRC,FRB } },
4658

4659
{ "fnmadds", A(59,31,0), A_MASK,	PPC,		{ FRT,FRA,FRC,FRB } },
4660
{ "fnmadds.",A(59,31,1), A_MASK,	PPC,		{ FRT,FRA,FRC,FRB } },
4661

4662
{ "dmul",    XRC(59,34,0), X_MASK,	POWER6,		{ FRT, FRA, FRB } },
4663
{ "dmul.",   XRC(59,34,1), X_MASK,	POWER6,		{ FRT, FRA, FRB } },
4664

4665
{ "drrnd",   ZRC(59,35,0), Z_MASK,	POWER6,		{ FRT, FRA, FRB, RMC } },
4666
{ "drrnd.",  ZRC(59,35,1), Z_MASK,	POWER6,		{ FRT, FRA, FRB, RMC } },
4667

4668
{ "dscli",   ZRC(59,66,0), Z_MASK,	POWER6,		{ FRT, FRA, SH16 } },
4669
{ "dscli.",  ZRC(59,66,1), Z_MASK,	POWER6,		{ FRT, FRA, SH16 } },
4670

4671
{ "dquai",   ZRC(59,67,0), Z_MASK,	POWER6,		{ TE,  FRT, FRB, RMC } },
4672
{ "dquai.",  ZRC(59,67,1), Z_MASK,	POWER6,		{ TE,  FRT, FRB, RMC } },
4673

4674
{ "dscri",   ZRC(59,98,0), Z_MASK,	POWER6,		{ FRT, FRA, SH16 } },
4675
{ "dscri.",  ZRC(59,98,1), Z_MASK,	POWER6,		{ FRT, FRA, SH16 } },
4676

4677
{ "drintx",  ZRC(59,99,0), Z_MASK,	POWER6,		{ R, FRT, FRB, RMC } },
4678
{ "drintx.", ZRC(59,99,1), Z_MASK,	POWER6,		{ R, FRT, FRB, RMC } },
4679

4680
{ "dcmpo",   X(59,130),	   X_MASK,	POWER6,		{ BF,  FRA, FRB } },
4681

4682
{ "dtstex",  X(59,162),	   X_MASK,	POWER6,		{ BF,  FRA, FRB } },
4683
{ "dtstdc",  Z(59,194),	   Z_MASK,	POWER6,		{ BF,  FRA, DCM } },
4684
{ "dtstdg",  Z(59,226),	   Z_MASK,	POWER6,		{ BF,  FRA, DGM } },
4685

4686
{ "drintn",  ZRC(59,227,0), Z_MASK,	POWER6,		{ R, FRT, FRB, RMC } },
4687
{ "drintn.", ZRC(59,227,1), Z_MASK,	POWER6,		{ R, FRT, FRB, RMC } },
4688

4689
{ "dctdp",   XRC(59,258,0), X_MASK,	POWER6,		{ FRT, FRB } },
4690
{ "dctdp.",  XRC(59,258,1), X_MASK,	POWER6,		{ FRT, FRB } },
4691

4692
{ "dctfix",  XRC(59,290,0), X_MASK,	POWER6,		{ FRT, FRB } },
4693
{ "dctfix.", XRC(59,290,1), X_MASK,	POWER6,		{ FRT, FRB } },
4694

4695
{ "ddedpd",  XRC(59,322,0), X_MASK,	POWER6,		{ SP, FRT, FRB } }, 
4696
{ "ddedpd.", XRC(59,322,1), X_MASK,	POWER6,		{ SP, FRT, FRB } }, 
4697

4698
{ "dxex",    XRC(59,354,0), X_MASK,	POWER6,		{ FRT, FRB } },
4699
{ "dxex.",   XRC(59,354,1), X_MASK,	POWER6,		{ FRT, FRB } },
4700

4701
{ "dsub",    XRC(59,514,0), X_MASK,	POWER6,		{ FRT, FRA, FRB } },
4702
{ "dsub.",   XRC(59,514,1), X_MASK,	POWER6,		{ FRT, FRA, FRB } },
4703

4704
{ "ddiv",    XRC(59,546,0), X_MASK,	POWER6,		{ FRT, FRA, FRB } },
4705
{ "ddiv.",   XRC(59,546,1), X_MASK,	POWER6,		{ FRT, FRA, FRB } },
4706

4707
{ "dcmpu",   X(59,642),	    X_MASK,	POWER6,		{ BF,  FRA, FRB } },
4708

4709
{ "dtstsf",  X(59,674),	   X_MASK,	POWER6,		{ BF,  FRA, FRB } },
4710

4711
{ "drsp",    XRC(59,770,0), X_MASK,	POWER6,		{ FRT, FRB } },
4712
{ "drsp.",   XRC(59,770,1), X_MASK,	POWER6,		{ FRT, FRB } },
4713

4714
{ "dcffix",  XRC(59,802,0), X_MASK,	POWER6,		{ FRT, FRB } },
4715
{ "dcffix.", XRC(59,802,1), X_MASK,	POWER6,		{ FRT, FRB } },
4716

4717
{ "denbcd",  XRC(59,834,0), X_MASK,	POWER6,		{ S, FRT, FRB } },
4718
{ "denbcd.", XRC(59,834,1), X_MASK,	POWER6,		{ S, FRT, FRB } },
4719

4720
{ "diex",    XRC(59,866,0), X_MASK,	POWER6,		{ FRT, FRA, FRB } },
4721
{ "diex.",   XRC(59,866,1), X_MASK,	POWER6,		{ FRT, FRA, FRB } },
4722

4723
{ "stfq",    OP(60),	OP_MASK,	POWER2,		{ FRS, D, RA } },
4724

4725
{ "stfqu",   OP(61),	OP_MASK,	POWER2,		{ FRS, D, RA } },
4726

4727
{ "stfdp",   OP(61),	OP_MASK,	POWER6,		{ FRT, D, RA0 } },
4728

4729
{ "lde",     DEO(62,0), DE_MASK,	BOOKE64,	{ RT, DES, RA0 } },
4730
{ "ldue",    DEO(62,1), DE_MASK,	BOOKE64,	{ RT, DES, RA0 } },
4731
{ "lfse",    DEO(62,4), DE_MASK,	BOOKE64,	{ FRT, DES, RA0 } },
4732
{ "lfsue",   DEO(62,5), DE_MASK,	BOOKE64,	{ FRT, DES, RAS } },
4733
{ "lfde",    DEO(62,6), DE_MASK,	BOOKE64,	{ FRT, DES, RA0 } },
4734
{ "lfdue",   DEO(62,7), DE_MASK,	BOOKE64,	{ FRT, DES, RAS } },
4735
{ "stde",    DEO(62,8), DE_MASK,	BOOKE64,	{ RS, DES, RA0 } },
4736
{ "stdue",   DEO(62,9), DE_MASK,	BOOKE64,	{ RS, DES, RAS } },
4737
{ "stfse",   DEO(62,12), DE_MASK,	BOOKE64,	{ FRS, DES, RA0 } },
4738
{ "stfsue",  DEO(62,13), DE_MASK,	BOOKE64,	{ FRS, DES, RAS } },
4739
{ "stfde",   DEO(62,14), DE_MASK,	BOOKE64,	{ FRS, DES, RA0 } },
4740
{ "stfdue",  DEO(62,15), DE_MASK,	BOOKE64,	{ FRS, DES, RAS } },
4741

4742
{ "std",     DSO(62,0),	DS_MASK,	PPC64,		{ RS, DS, RA0 } },
4743

4744
{ "stdu",    DSO(62,1),	DS_MASK,	PPC64,		{ RS, DS, RAS } },
4745

4746
{ "stq",     DSO(62,2),	DS_MASK,	POWER4,		{ RSQ, DS, RA0 } },
4747

4748
{ "fcmpu",   X(63,0),	X_MASK|(3<<21),	COM,		{ BF, FRA, FRB } },
4749

4750
{ "daddq",   XRC(63,2,0), X_MASK,	POWER6,		{ FRT, FRA, FRB } },
4751
{ "daddq.",  XRC(63,2,1), X_MASK,	POWER6,		{ FRT, FRA, FRB } },
4752

4753
{ "dquaq",   ZRC(63,3,0), Z_MASK,	POWER6,		{ FRT, FRA, FRB, RMC } },
4754
{ "dquaq.",  ZRC(63,3,1), Z_MASK,	POWER6,		{ FRT, FRA, FRB, RMC } },
4755

4756
{ "fcpsgn",  XRC(63,8,0), X_MASK,	POWER6,		{ FRT, FRA, FRB } },
4757
{ "fcpsgn.", XRC(63,8,1), X_MASK,	POWER6,		{ FRT, FRA, FRB } },
4758

4759
{ "frsp",    XRC(63,12,0), XRA_MASK,	COM,		{ FRT, FRB } },
4760
{ "frsp.",   XRC(63,12,1), XRA_MASK,	COM,		{ FRT, FRB } },
4761

4762
{ "fctiw",   XRC(63,14,0), XRA_MASK,	PPCCOM,		{ FRT, FRB } },
4763
{ "fcir",    XRC(63,14,0), XRA_MASK,	POWER2,		{ FRT, FRB } },
4764
{ "fctiw.",  XRC(63,14,1), XRA_MASK,	PPCCOM,		{ FRT, FRB } },
4765
{ "fcir.",   XRC(63,14,1), XRA_MASK,	POWER2,		{ FRT, FRB } },
4766

4767
{ "fctiwz",  XRC(63,15,0), XRA_MASK,	PPCCOM,		{ FRT, FRB } },
4768
{ "fcirz",   XRC(63,15,0), XRA_MASK,	POWER2,		{ FRT, FRB } },
4769
{ "fctiwz.", XRC(63,15,1), XRA_MASK,	PPCCOM,		{ FRT, FRB } },
4770
{ "fcirz.",  XRC(63,15,1), XRA_MASK,	POWER2,		{ FRT, FRB } },
4771

4772
{ "fdiv",    A(63,18,0), AFRC_MASK,	PPCCOM,		{ FRT, FRA, FRB } },
4773
{ "fd",      A(63,18,0), AFRC_MASK,	PWRCOM,		{ FRT, FRA, FRB } },
4774
{ "fdiv.",   A(63,18,1), AFRC_MASK,	PPCCOM,		{ FRT, FRA, FRB } },
4775
{ "fd.",     A(63,18,1), AFRC_MASK,	PWRCOM,		{ FRT, FRA, FRB } },
4776

4777
{ "fsub",    A(63,20,0), AFRC_MASK,	PPCCOM,		{ FRT, FRA, FRB } },
4778
{ "fs",      A(63,20,0), AFRC_MASK,	PWRCOM,		{ FRT, FRA, FRB } },
4779
{ "fsub.",   A(63,20,1), AFRC_MASK,	PPCCOM,		{ FRT, FRA, FRB } },
4780
{ "fs.",     A(63,20,1), AFRC_MASK,	PWRCOM,		{ FRT, FRA, FRB } },
4781

4782
{ "fadd",    A(63,21,0), AFRC_MASK,	PPCCOM,		{ FRT, FRA, FRB } },
4783
{ "fa",      A(63,21,0), AFRC_MASK,	PWRCOM,		{ FRT, FRA, FRB } },
4784
{ "fadd.",   A(63,21,1), AFRC_MASK,	PPCCOM,		{ FRT, FRA, FRB } },
4785
{ "fa.",     A(63,21,1), AFRC_MASK,	PWRCOM,		{ FRT, FRA, FRB } },
4786

4787
{ "fsqrt",   A(63,22,0), AFRAFRC_MASK,	PPCPWR2,	{ FRT, FRB } },
4788
{ "fsqrt.",  A(63,22,1), AFRAFRC_MASK,	PPCPWR2,	{ FRT, FRB } },
4789

4790
{ "fsel",    A(63,23,0), A_MASK,	PPC,		{ FRT,FRA,FRC,FRB } },
4791
{ "fsel.",   A(63,23,1), A_MASK,	PPC,		{ FRT,FRA,FRC,FRB } },
4792

4793
{ "fre",     A(63,24,0), AFRALFRC_MASK,	POWER5,		{ FRT, FRB, A_L } },
4794
{ "fre.",    A(63,24,1), AFRALFRC_MASK,	POWER5,		{ FRT, FRB, A_L } },
4795

4796
{ "fmul",    A(63,25,0), AFRB_MASK,	PPCCOM,		{ FRT, FRA, FRC } },
4797
{ "fm",      A(63,25,0), AFRB_MASK,	PWRCOM,		{ FRT, FRA, FRC } },
4798
{ "fmul.",   A(63,25,1), AFRB_MASK,	PPCCOM,		{ FRT, FRA, FRC } },
4799
{ "fm.",     A(63,25,1), AFRB_MASK,	PWRCOM,		{ FRT, FRA, FRC } },
4800

4801
{ "frsqrte", A(63,26,0), AFRALFRC_MASK,	PPC,		{ FRT, FRB, A_L } },
4802
{ "frsqrte.",A(63,26,1), AFRALFRC_MASK,	PPC,		{ FRT, FRB, A_L } },
4803

4804
{ "fmsub",   A(63,28,0), A_MASK,	PPCCOM,		{ FRT,FRA,FRC,FRB } },
4805
{ "fms",     A(63,28,0), A_MASK,	PWRCOM,		{ FRT,FRA,FRC,FRB } },
4806
{ "fmsub.",  A(63,28,1), A_MASK,	PPCCOM,		{ FRT,FRA,FRC,FRB } },
4807
{ "fms.",    A(63,28,1), A_MASK,	PWRCOM,		{ FRT,FRA,FRC,FRB } },
4808

4809
{ "fmadd",   A(63,29,0), A_MASK,	PPCCOM,		{ FRT,FRA,FRC,FRB } },
4810
{ "fma",     A(63,29,0), A_MASK,	PWRCOM,		{ FRT,FRA,FRC,FRB } },
4811
{ "fmadd.",  A(63,29,1), A_MASK,	PPCCOM,		{ FRT,FRA,FRC,FRB } },
4812
{ "fma.",    A(63,29,1), A_MASK,	PWRCOM,		{ FRT,FRA,FRC,FRB } },
4813

4814
{ "fnmsub",  A(63,30,0), A_MASK,	PPCCOM,		{ FRT,FRA,FRC,FRB } },
4815
{ "fnms",    A(63,30,0), A_MASK,	PWRCOM,		{ FRT,FRA,FRC,FRB } },
4816
{ "fnmsub.", A(63,30,1), A_MASK,	PPCCOM,		{ FRT,FRA,FRC,FRB } },
4817
{ "fnms.",   A(63,30,1), A_MASK,	PWRCOM,		{ FRT,FRA,FRC,FRB } },
4818

4819
{ "fnmadd",  A(63,31,0), A_MASK,	PPCCOM,		{ FRT,FRA,FRC,FRB } },
4820
{ "fnma",    A(63,31,0), A_MASK,	PWRCOM,		{ FRT,FRA,FRC,FRB } },
4821
{ "fnmadd.", A(63,31,1), A_MASK,	PPCCOM,		{ FRT,FRA,FRC,FRB } },
4822
{ "fnma.",   A(63,31,1), A_MASK,	PWRCOM,		{ FRT,FRA,FRC,FRB } },
4823

4824
{ "fcmpo",   X(63,32),	X_MASK|(3<<21),	COM,		{ BF, FRA, FRB } },
4825

4826
{ "dmulq",   XRC(63,34,0), X_MASK,	POWER6,		{ FRT, FRA, FRB } },
4827
{ "dmulq.",  XRC(63,34,1), X_MASK,	POWER6,		{ FRT, FRA, FRB } },
4828

4829
{ "drrndq",  ZRC(63,35,0), Z_MASK,	POWER6,		{ FRT, FRA, FRB, RMC } },
4830
{ "drrndq.", ZRC(63,35,1), Z_MASK,	POWER6,		{ FRT, FRA, FRB, RMC } },
4831

4832
{ "mtfsb1",  XRC(63,38,0), XRARB_MASK,	COM,		{ BT } },
4833
{ "mtfsb1.", XRC(63,38,1), XRARB_MASK,	COM,		{ BT } },
4834

4835
{ "fneg",    XRC(63,40,0), XRA_MASK,	COM,		{ FRT, FRB } },
4836
{ "fneg.",   XRC(63,40,1), XRA_MASK,	COM,		{ FRT, FRB } },
4837

4838
{ "mcrfs",   X(63,64),	XRB_MASK|(3<<21)|(3<<16), COM,	{ BF, BFA } },
4839

4840
{ "dscliq",  ZRC(63,66,0), Z_MASK,	POWER6,		{ FRT, FRA, SH16 } },
4841
{ "dscliq.", ZRC(63,66,1), Z_MASK,	POWER6,		{ FRT, FRA, SH16 } },
4842

4843
{ "dquaiq",  ZRC(63,67,0), Z_MASK,	POWER6,		{ TE,  FRT, FRB, RMC } },
4844
{ "dquaiq.", ZRC(63,67,1), Z_MASK,	POWER6,		{ FRT, FRA, FRB, RMC } },
4845

4846
{ "mtfsb0",  XRC(63,70,0), XRARB_MASK,	COM,		{ BT } },
4847
{ "mtfsb0.", XRC(63,70,1), XRARB_MASK,	COM,		{ BT } },
4848

4849
{ "fmr",     XRC(63,72,0), XRA_MASK,	COM,		{ FRT, FRB } },
4850
{ "fmr.",    XRC(63,72,1), XRA_MASK,	COM,		{ FRT, FRB } },
4851

4852
{ "dscriq",  ZRC(63,98,0), Z_MASK,	POWER6,		{ FRT, FRA, SH16 } },
4853
{ "dscriq.", ZRC(63,98,1), Z_MASK,	POWER6,		{ FRT, FRA, SH16 } },
4854

4855
{ "drintxq", ZRC(63,99,0), Z_MASK,	POWER6,		{ R, FRT, FRB, RMC } },
4856
{ "drintxq.",ZRC(63,99,1), Z_MASK,	POWER6,		{ R, FRT, FRB, RMC } },
4857

4858
{ "dcmpoq",  X(63,130),	   X_MASK,	POWER6,		{ BF,  FRA, FRB } },
4859

4860
{ "mtfsfi",  XRC(63,134,0), XRA_MASK|(3<<21)|(1<<11), COM, { BF, U } },
4861
{ "mtfsfi.", XRC(63,134,1), XRA_MASK|(3<<21)|(1<<11), COM, { BF, U } },
4862

4863
{ "fnabs",   XRC(63,136,0), XRA_MASK,	COM,		{ FRT, FRB } },
4864
{ "fnabs.",  XRC(63,136,1), XRA_MASK,	COM,		{ FRT, FRB } },
4865

4866
{ "dtstexq", X(63,162),	    X_MASK,	POWER6,		{ BF,  FRA, FRB } },
4867
{ "dtstdcq", Z(63,194),	    Z_MASK,	POWER6,		{ BF,  FRA, DCM } },
4868
{ "dtstdgq", Z(63,226),	    Z_MASK,	POWER6,		{ BF,  FRA, DGM } },
4869

4870
{ "drintnq", ZRC(63,227,0), Z_MASK,	POWER6,		{ R, FRT, FRB, RMC } },
4871
{ "drintnq.",ZRC(63,227,1), Z_MASK,	POWER6,		{ R, FRT, FRB, RMC } },
4872

4873
{ "dctqpq",  XRC(63,258,0), X_MASK,	POWER6,		{ FRT, FRB } },
4874
{ "dctqpq.", XRC(63,258,1), X_MASK,	POWER6,		{ FRT, FRB } },
4875

4876
{ "fabs",    XRC(63,264,0), XRA_MASK,	COM,		{ FRT, FRB } },
4877
{ "fabs.",   XRC(63,264,1), XRA_MASK,	COM,		{ FRT, FRB } },
4878

4879
{ "dctfixq", XRC(63,290,0), X_MASK,	POWER6,		{ FRT, FRB } },
4880
{ "dctfixq.",XRC(63,290,1), X_MASK,	POWER6,		{ FRT, FRB } },
4881

4882
{ "ddedpdq", XRC(63,322,0), X_MASK,	POWER6,		{ SP, FRT, FRB } },
4883
{ "ddedpdq.",XRC(63,322,1), X_MASK,	POWER6,		{ SP, FRT, FRB } },
4884

4885
{ "dxexq",   XRC(63,354,0), X_MASK,	POWER6,		{ FRT, FRB } },
4886
{ "dxexq.",  XRC(63,354,1), X_MASK,	POWER6,		{ FRT, FRB } },
4887

4888
{ "frin",    XRC(63,392,0), XRA_MASK,	POWER5,		{ FRT, FRB } },
4889
{ "frin.",   XRC(63,392,1), XRA_MASK,	POWER5,		{ FRT, FRB } },
4890
{ "friz",    XRC(63,424,0), XRA_MASK,	POWER5,		{ FRT, FRB } },
4891
{ "friz.",   XRC(63,424,1), XRA_MASK,	POWER5,		{ FRT, FRB } },
4892
{ "frip",    XRC(63,456,0), XRA_MASK,	POWER5,		{ FRT, FRB } },
4893
{ "frip.",   XRC(63,456,1), XRA_MASK,	POWER5,		{ FRT, FRB } },
4894
{ "frim",    XRC(63,488,0), XRA_MASK,	POWER5,		{ FRT, FRB } },
4895
{ "frim.",   XRC(63,488,1), XRA_MASK,	POWER5,		{ FRT, FRB } },
4896

4897
{ "dsubq",   XRC(63,514,0), X_MASK,	POWER6,		{ FRT, FRA, FRB } },
4898
{ "dsubq.",  XRC(63,514,1), X_MASK,	POWER6,		{ FRT, FRA, FRB } },
4899

4900
{ "ddivq",   XRC(63,546,0), X_MASK,	POWER6,		{ FRT, FRA, FRB } },
4901
{ "ddivq.",  XRC(63,546,1), X_MASK,	POWER6,		{ FRT, FRA, FRB } },
4902

4903
{ "mffs",    XRC(63,583,0), XRARB_MASK,	COM,		{ FRT } },
4904
{ "mffs.",   XRC(63,583,1), XRARB_MASK,	COM,		{ FRT } },
4905

4906
{ "dcmpuq",  X(63,642),	    X_MASK,	POWER6,		{ BF,  FRA, FRB } },
4907

4908
{ "dtstsfq", X(63,674),	    X_MASK,	POWER6,		{ BF,  FRA, FRB } },
4909

4910
{ "mtfsf",   XFL(63,711,0), XFL_MASK,	COM,		{ FLM, FRB } },
4911
{ "mtfsf.",  XFL(63,711,1), XFL_MASK,	COM,		{ FLM, FRB } },
4912

4913
{ "drdpq",   XRC(63,770,0), X_MASK,	POWER6,		{ FRT, FRB } },
4914
{ "drdpq.",  XRC(63,770,1), X_MASK,	POWER6,		{ FRT, FRB } },
4915

4916
{ "dcffixq", XRC(63,802,0), X_MASK,	POWER6,		{ FRT, FRB } },
4917
{ "dcffixq.",XRC(63,802,1), X_MASK,	POWER6,		{ FRT, FRB } },
4918

4919
{ "fctid",   XRC(63,814,0), XRA_MASK,	PPC64,		{ FRT, FRB } },
4920
{ "fctid.",  XRC(63,814,1), XRA_MASK,	PPC64,		{ FRT, FRB } },
4921

4922
{ "fctidz",  XRC(63,815,0), XRA_MASK,	PPC64,		{ FRT, FRB } },
4923
{ "fctidz.", XRC(63,815,1), XRA_MASK,	PPC64,		{ FRT, FRB } },
4924

4925
{ "denbcdq", XRC(63,834,0), X_MASK,	POWER6,		{ S, FRT, FRB } },
4926
{ "denbcdq.",XRC(63,834,1), X_MASK,	POWER6,		{ S, FRT, FRB } },
4927

4928
{ "fcfid",   XRC(63,846,0), XRA_MASK,	PPC64,		{ FRT, FRB } },
4929
{ "fcfid.",  XRC(63,846,1), XRA_MASK,	PPC64,		{ FRT, FRB } },
4930

4931
{ "diexq",   XRC(63,866,0), X_MASK,	POWER6,		{ FRT, FRA, FRB } },
4932
{ "diexq.",  XRC(63,866,1), X_MASK,	POWER6,		{ FRT, FRA, FRB } },
4933

4934
};
4935

4936
const int powerpc_num_opcodes = ARRAY_SIZE(powerpc_opcodes);
4937

4938
/* The macro table.  This is only used by the assembler.  */
4939

4940
/* The expressions of the form (-x ! 31) & (x | 31) have the value 0
4941
   when x=0; 32-x when x is between 1 and 31; are negative if x is
4942
   negative; and are 32 or more otherwise.  This is what you want
4943
   when, for instance, you are emulating a right shift by a
4944
   rotate-left-and-mask, because the underlying instructions support
4945
   shifts of size 0 but not shifts of size 32.  By comparison, when
4946
   extracting x bits from some word you want to use just 32-x, because
4947
   the underlying instructions don't support extracting 0 bits but do
4948
   support extracting the whole word (32 bits in this case).  */
4949

4950
const struct powerpc_macro powerpc_macros[] = {
4951
{ "extldi",  4,   PPC64,	"rldicr %0,%1,%3,(%2)-1" },
4952
{ "extldi.", 4,   PPC64,	"rldicr. %0,%1,%3,(%2)-1" },
4953
{ "extrdi",  4,   PPC64,	"rldicl %0,%1,(%2)+(%3),64-(%2)" },
4954
{ "extrdi.", 4,   PPC64,	"rldicl. %0,%1,(%2)+(%3),64-(%2)" },
4955
{ "insrdi",  4,   PPC64,	"rldimi %0,%1,64-((%2)+(%3)),%3" },
4956
{ "insrdi.", 4,   PPC64,	"rldimi. %0,%1,64-((%2)+(%3)),%3" },
4957
{ "rotrdi",  3,   PPC64,	"rldicl %0,%1,(-(%2)!63)&((%2)|63),0" },
4958
{ "rotrdi.", 3,   PPC64,	"rldicl. %0,%1,(-(%2)!63)&((%2)|63),0" },
4959
{ "sldi",    3,   PPC64,	"rldicr %0,%1,%2,63-(%2)" },
4960
{ "sldi.",   3,   PPC64,	"rldicr. %0,%1,%2,63-(%2)" },
4961
{ "srdi",    3,   PPC64,	"rldicl %0,%1,(-(%2)!63)&((%2)|63),%2" },
4962
{ "srdi.",   3,   PPC64,	"rldicl. %0,%1,(-(%2)!63)&((%2)|63),%2" },
4963
{ "clrrdi",  3,   PPC64,	"rldicr %0,%1,0,63-(%2)" },
4964
{ "clrrdi.", 3,   PPC64,	"rldicr. %0,%1,0,63-(%2)" },
4965
{ "clrlsldi",4,   PPC64,	"rldic %0,%1,%3,(%2)-(%3)" },
4966
{ "clrlsldi.",4,  PPC64,	"rldic. %0,%1,%3,(%2)-(%3)" },
4967

4968
{ "extlwi",  4,   PPCCOM,	"rlwinm %0,%1,%3,0,(%2)-1" },
4969
{ "extlwi.", 4,   PPCCOM,	"rlwinm. %0,%1,%3,0,(%2)-1" },
4970
{ "extrwi",  4,   PPCCOM,	"rlwinm %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31" },
4971
{ "extrwi.", 4,   PPCCOM,	"rlwinm. %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31" },
4972
{ "inslwi",  4,   PPCCOM,	"rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1" },
4973
{ "inslwi.", 4,   PPCCOM,	"rlwimi. %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
4974
{ "insrwi",  4,   PPCCOM,	"rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1" },
4975
{ "insrwi.", 4,   PPCCOM,	"rlwimi. %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
4976
{ "rotrwi",  3,   PPCCOM,	"rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31" },
4977
{ "rotrwi.", 3,   PPCCOM,	"rlwinm. %0,%1,(-(%2)!31)&((%2)|31),0,31" },
4978
{ "slwi",    3,   PPCCOM,	"rlwinm %0,%1,%2,0,31-(%2)" },
4979
{ "sli",     3,   PWRCOM,	"rlinm %0,%1,%2,0,31-(%2)" },
4980
{ "slwi.",   3,   PPCCOM,	"rlwinm. %0,%1,%2,0,31-(%2)" },
4981
{ "sli.",    3,   PWRCOM,	"rlinm. %0,%1,%2,0,31-(%2)" },
4982
{ "srwi",    3,   PPCCOM,	"rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
4983
{ "sri",     3,   PWRCOM,	"rlinm %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
4984
{ "srwi.",   3,   PPCCOM,	"rlwinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
4985
{ "sri.",    3,   PWRCOM,	"rlinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
4986
{ "clrrwi",  3,   PPCCOM,	"rlwinm %0,%1,0,0,31-(%2)" },
4987
{ "clrrwi.", 3,   PPCCOM,	"rlwinm. %0,%1,0,0,31-(%2)" },
4988
{ "clrlslwi",4,   PPCCOM,	"rlwinm %0,%1,%3,(%2)-(%3),31-(%3)" },
4989
{ "clrlslwi.",4,  PPCCOM,	"rlwinm. %0,%1,%3,(%2)-(%3),31-(%3)" },
4990
};
4991

4992
const int powerpc_num_macros = ARRAY_SIZE(powerpc_macros);
4993

4994
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