CoCalc -- board-sh7757lcr.c

GitHub Repository: awilliam/linux-vfio
Path: blob/master/arch/sh/boards/board-sh7757lcr.c
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1
/*
2
 * Renesas R0P7757LC0012RL Support.
3
 *
4
 * Copyright (C) 2009 - 2010  Renesas Solutions Corp.
5
 *
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 * This file is subject to the terms and conditions of the GNU General Public
7
 * License.  See the file "COPYING" in the main directory of this archive
8
 * for more details.
9
 */
10

11
#include <linux/init.h>
12
#include <linux/platform_device.h>
13
#include <linux/gpio.h>
14
#include <linux/irq.h>
15
#include <linux/spi/spi.h>
16
#include <linux/spi/flash.h>
17
#include <linux/io.h>
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#include <linux/mmc/host.h>
19
#include <linux/mmc/sh_mmcif.h>
20
#include <linux/mmc/sh_mobile_sdhi.h>
21
#include <cpu/sh7757.h>
22
#include <asm/sh_eth.h>
23
#include <asm/heartbeat.h>
24

25
static struct resource heartbeat_resource = {
26
	.start	= 0xffec005c,	/* PUDR */
27
	.end	= 0xffec005c,
28
	.flags	= IORESOURCE_MEM | IORESOURCE_MEM_8BIT,
29
};
30

31
static unsigned char heartbeat_bit_pos[] = { 0, 1, 2, 3 };
32

33
static struct heartbeat_data heartbeat_data = {
34
	.bit_pos	= heartbeat_bit_pos,
35
	.nr_bits	= ARRAY_SIZE(heartbeat_bit_pos),
36
	.flags		= HEARTBEAT_INVERTED,
37
};
38

39
static struct platform_device heartbeat_device = {
40
	.name		= "heartbeat",
41
	.id		= -1,
42
	.dev	= {
43
		.platform_data	= &heartbeat_data,
44
	},
45
	.num_resources	= 1,
46
	.resource	= &heartbeat_resource,
47
};
48

49
/* Fast Ethernet */
50
#define GBECONT		0xffc10100
51
#define GBECONT_RMII1	BIT(17)
52
#define GBECONT_RMII0	BIT(16)
53
static void sh7757_eth_set_mdio_gate(unsigned long addr)
54
{
55
	if ((addr & 0x00000fff) < 0x0800)
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		writel(readl(GBECONT) | GBECONT_RMII0, GBECONT);
57
	else
58
		writel(readl(GBECONT) | GBECONT_RMII1, GBECONT);
59
}
60

61
static struct resource sh_eth0_resources[] = {
62
	{
63
		.start  = 0xfef00000,
64
		.end    = 0xfef001ff,
65
		.flags  = IORESOURCE_MEM,
66
	}, {
67
		.start  = 84,
68
		.end    = 84,
69
		.flags  = IORESOURCE_IRQ,
70
	},
71
};
72

73
static struct sh_eth_plat_data sh7757_eth0_pdata = {
74
	.phy = 1,
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	.edmac_endian = EDMAC_LITTLE_ENDIAN,
76
	.register_type = SH_ETH_REG_FAST_SH4,
77
	.set_mdio_gate = sh7757_eth_set_mdio_gate,
78
};
79

80
static struct platform_device sh7757_eth0_device = {
81
	.name		= "sh-eth",
82
	.resource	= sh_eth0_resources,
83
	.id		= 0,
84
	.num_resources	= ARRAY_SIZE(sh_eth0_resources),
85
	.dev		= {
86
		.platform_data = &sh7757_eth0_pdata,
87
	},
88
};
89

90
static struct resource sh_eth1_resources[] = {
91
	{
92
		.start  = 0xfef00800,
93
		.end    = 0xfef009ff,
94
		.flags  = IORESOURCE_MEM,
95
	}, {
96
		.start  = 84,
97
		.end    = 84,
98
		.flags  = IORESOURCE_IRQ,
99
	},
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};
101

102
static struct sh_eth_plat_data sh7757_eth1_pdata = {
103
	.phy = 1,
104
	.edmac_endian = EDMAC_LITTLE_ENDIAN,
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	.register_type = SH_ETH_REG_FAST_SH4,
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	.set_mdio_gate = sh7757_eth_set_mdio_gate,
107
};
108

109
static struct platform_device sh7757_eth1_device = {
110
	.name		= "sh-eth",
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	.resource	= sh_eth1_resources,
112
	.id		= 1,
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	.num_resources	= ARRAY_SIZE(sh_eth1_resources),
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	.dev		= {
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		.platform_data = &sh7757_eth1_pdata,
116
	},
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};
118

119
static void sh7757_eth_giga_set_mdio_gate(unsigned long addr)
120
{
121
	if ((addr & 0x00000fff) < 0x0800) {
122
		gpio_set_value(GPIO_PTT4, 1);
123
		writel(readl(GBECONT) & ~GBECONT_RMII0, GBECONT);
124
	} else {
125
		gpio_set_value(GPIO_PTT4, 0);
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		writel(readl(GBECONT) & ~GBECONT_RMII1, GBECONT);
127
	}
128
}
129

130
static struct resource sh_eth_giga0_resources[] = {
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	{
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		.start  = 0xfee00000,
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		.end    = 0xfee007ff,
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		.flags  = IORESOURCE_MEM,
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	}, {
136
		/* TSU */
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		.start  = 0xfee01800,
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		.end    = 0xfee01fff,
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		.flags  = IORESOURCE_MEM,
140
	}, {
141
		.start  = 315,
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		.end    = 315,
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		.flags  = IORESOURCE_IRQ,
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	},
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};
146

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static struct sh_eth_plat_data sh7757_eth_giga0_pdata = {
148
	.phy = 18,
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	.edmac_endian = EDMAC_LITTLE_ENDIAN,
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	.register_type = SH_ETH_REG_GIGABIT,
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	.set_mdio_gate = sh7757_eth_giga_set_mdio_gate,
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	.phy_interface = PHY_INTERFACE_MODE_RGMII_ID,
153
};
154

155
static struct platform_device sh7757_eth_giga0_device = {
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	.name		= "sh-eth",
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	.resource	= sh_eth_giga0_resources,
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	.id		= 2,
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	.num_resources	= ARRAY_SIZE(sh_eth_giga0_resources),
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	.dev		= {
161
		.platform_data = &sh7757_eth_giga0_pdata,
162
	},
163
};
164

165
static struct resource sh_eth_giga1_resources[] = {
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	{
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		.start  = 0xfee00800,
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		.end    = 0xfee00fff,
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		.flags  = IORESOURCE_MEM,
170
	}, {
171
		.start  = 316,
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		.end    = 316,
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		.flags  = IORESOURCE_IRQ,
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	},
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};
176

177
static struct sh_eth_plat_data sh7757_eth_giga1_pdata = {
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	.phy = 19,
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	.edmac_endian = EDMAC_LITTLE_ENDIAN,
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	.register_type = SH_ETH_REG_GIGABIT,
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	.set_mdio_gate = sh7757_eth_giga_set_mdio_gate,
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	.phy_interface = PHY_INTERFACE_MODE_RGMII_ID,
183
};
184

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static struct platform_device sh7757_eth_giga1_device = {
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	.name		= "sh-eth",
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	.resource	= sh_eth_giga1_resources,
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	.id		= 3,
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	.num_resources	= ARRAY_SIZE(sh_eth_giga1_resources),
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	.dev		= {
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		.platform_data = &sh7757_eth_giga1_pdata,
192
	},
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};
194

195
/* SH_MMCIF */
196
static struct resource sh_mmcif_resources[] = {
197
	[0] = {
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		.start	= 0xffcb0000,
199
		.end	= 0xffcb00ff,
200
		.flags	= IORESOURCE_MEM,
201
	},
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	[1] = {
203
		.start	= 211,
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		.flags	= IORESOURCE_IRQ,
205
	},
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	[2] = {
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		.start	= 212,
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		.flags	= IORESOURCE_IRQ,
209
	},
210
};
211

212
static struct sh_mmcif_dma sh7757lcr_mmcif_dma = {
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	.chan_priv_tx	= SHDMA_SLAVE_MMCIF_TX,
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	.chan_priv_rx	= SHDMA_SLAVE_MMCIF_RX,
215
};
216

217
static struct sh_mmcif_plat_data sh_mmcif_plat = {
218
	.dma		= &sh7757lcr_mmcif_dma,
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	.sup_pclk	= 0x0f,
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	.caps		= MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
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	.ocr		= MMC_VDD_32_33 | MMC_VDD_33_34,
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};
223

224
static struct platform_device sh_mmcif_device = {
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	.name		= "sh_mmcif",
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	.id		= 0,
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	.dev		= {
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		.platform_data		= &sh_mmcif_plat,
229
	},
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	.num_resources	= ARRAY_SIZE(sh_mmcif_resources),
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	.resource	= sh_mmcif_resources,
232
};
233

234
/* SDHI0 */
235
static struct sh_mobile_sdhi_info sdhi_info = {
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	.dma_slave_tx	= SHDMA_SLAVE_SDHI_TX,
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	.dma_slave_rx	= SHDMA_SLAVE_SDHI_RX,
238
	.tmio_caps	= MMC_CAP_SD_HIGHSPEED,
239
};
240

241
static struct resource sdhi_resources[] = {
242
	[0] = {
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		.start  = 0xffe50000,
244
		.end    = 0xffe501ff,
245
		.flags  = IORESOURCE_MEM,
246
	},
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	[1] = {
248
		.start  = 20,
249
		.flags  = IORESOURCE_IRQ,
250
	},
251
};
252

253
static struct platform_device sdhi_device = {
254
	.name           = "sh_mobile_sdhi",
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	.num_resources  = ARRAY_SIZE(sdhi_resources),
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	.resource       = sdhi_resources,
257
	.id             = 0,
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	.dev	= {
259
		.platform_data	= &sdhi_info,
260
	},
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};
262

263
static struct platform_device *sh7757lcr_devices[] __initdata = {
264
	&heartbeat_device,
265
	&sh7757_eth0_device,
266
	&sh7757_eth1_device,
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	&sh7757_eth_giga0_device,
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	&sh7757_eth_giga1_device,
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	&sh_mmcif_device,
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	&sdhi_device,
271
};
272

273
static struct flash_platform_data spi_flash_data = {
274
	.name = "m25p80",
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	.type = "m25px64",
276
};
277

278
static struct spi_board_info spi_board_info[] = {
279
	{
280
		.modalias = "m25p80",
281
		.max_speed_hz = 25000000,
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		.bus_num = 0,
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		.chip_select = 1,
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		.platform_data = &spi_flash_data,
285
	},
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};
287

288
static int __init sh7757lcr_devices_setup(void)
289
{
290
	/* RGMII (PTA) */
291
	gpio_request(GPIO_FN_ET0_MDC, NULL);
292
	gpio_request(GPIO_FN_ET0_MDIO, NULL);
293
	gpio_request(GPIO_FN_ET1_MDC, NULL);
294
	gpio_request(GPIO_FN_ET1_MDIO, NULL);
295

296
	/* ONFI (PTB, PTZ) */
297
	gpio_request(GPIO_FN_ON_NRE, NULL);
298
	gpio_request(GPIO_FN_ON_NWE, NULL);
299
	gpio_request(GPIO_FN_ON_NWP, NULL);
300
	gpio_request(GPIO_FN_ON_NCE0, NULL);
301
	gpio_request(GPIO_FN_ON_R_B0, NULL);
302
	gpio_request(GPIO_FN_ON_ALE, NULL);
303
	gpio_request(GPIO_FN_ON_CLE, NULL);
304

305
	gpio_request(GPIO_FN_ON_DQ7, NULL);
306
	gpio_request(GPIO_FN_ON_DQ6, NULL);
307
	gpio_request(GPIO_FN_ON_DQ5, NULL);
308
	gpio_request(GPIO_FN_ON_DQ4, NULL);
309
	gpio_request(GPIO_FN_ON_DQ3, NULL);
310
	gpio_request(GPIO_FN_ON_DQ2, NULL);
311
	gpio_request(GPIO_FN_ON_DQ1, NULL);
312
	gpio_request(GPIO_FN_ON_DQ0, NULL);
313

314
	/* IRQ8 to 0 (PTB, PTC) */
315
	gpio_request(GPIO_FN_IRQ8, NULL);
316
	gpio_request(GPIO_FN_IRQ7, NULL);
317
	gpio_request(GPIO_FN_IRQ6, NULL);
318
	gpio_request(GPIO_FN_IRQ5, NULL);
319
	gpio_request(GPIO_FN_IRQ4, NULL);
320
	gpio_request(GPIO_FN_IRQ3, NULL);
321
	gpio_request(GPIO_FN_IRQ2, NULL);
322
	gpio_request(GPIO_FN_IRQ1, NULL);
323
	gpio_request(GPIO_FN_IRQ0, NULL);
324

325
	/* SPI0 (PTD) */
326
	gpio_request(GPIO_FN_SP0_MOSI, NULL);
327
	gpio_request(GPIO_FN_SP0_MISO, NULL);
328
	gpio_request(GPIO_FN_SP0_SCK, NULL);
329
	gpio_request(GPIO_FN_SP0_SCK_FB, NULL);
330
	gpio_request(GPIO_FN_SP0_SS0, NULL);
331
	gpio_request(GPIO_FN_SP0_SS1, NULL);
332
	gpio_request(GPIO_FN_SP0_SS2, NULL);
333
	gpio_request(GPIO_FN_SP0_SS3, NULL);
334

335
	/* RMII 0/1 (PTE, PTF) */
336
	gpio_request(GPIO_FN_RMII0_CRS_DV, NULL);
337
	gpio_request(GPIO_FN_RMII0_TXD1, NULL);
338
	gpio_request(GPIO_FN_RMII0_TXD0, NULL);
339
	gpio_request(GPIO_FN_RMII0_TXEN, NULL);
340
	gpio_request(GPIO_FN_RMII0_REFCLK, NULL);
341
	gpio_request(GPIO_FN_RMII0_RXD1, NULL);
342
	gpio_request(GPIO_FN_RMII0_RXD0, NULL);
343
	gpio_request(GPIO_FN_RMII0_RX_ER, NULL);
344
	gpio_request(GPIO_FN_RMII1_CRS_DV, NULL);
345
	gpio_request(GPIO_FN_RMII1_TXD1, NULL);
346
	gpio_request(GPIO_FN_RMII1_TXD0, NULL);
347
	gpio_request(GPIO_FN_RMII1_TXEN, NULL);
348
	gpio_request(GPIO_FN_RMII1_REFCLK, NULL);
349
	gpio_request(GPIO_FN_RMII1_RXD1, NULL);
350
	gpio_request(GPIO_FN_RMII1_RXD0, NULL);
351
	gpio_request(GPIO_FN_RMII1_RX_ER, NULL);
352

353
	/* eMMC (PTG) */
354
	gpio_request(GPIO_FN_MMCCLK, NULL);
355
	gpio_request(GPIO_FN_MMCCMD, NULL);
356
	gpio_request(GPIO_FN_MMCDAT7, NULL);
357
	gpio_request(GPIO_FN_MMCDAT6, NULL);
358
	gpio_request(GPIO_FN_MMCDAT5, NULL);
359
	gpio_request(GPIO_FN_MMCDAT4, NULL);
360
	gpio_request(GPIO_FN_MMCDAT3, NULL);
361
	gpio_request(GPIO_FN_MMCDAT2, NULL);
362
	gpio_request(GPIO_FN_MMCDAT1, NULL);
363
	gpio_request(GPIO_FN_MMCDAT0, NULL);
364

365
	/* LPC (PTG, PTH, PTQ, PTU) */
366
	gpio_request(GPIO_FN_SERIRQ, NULL);
367
	gpio_request(GPIO_FN_LPCPD, NULL);
368
	gpio_request(GPIO_FN_LDRQ, NULL);
369
	gpio_request(GPIO_FN_WP, NULL);
370
	gpio_request(GPIO_FN_FMS0, NULL);
371
	gpio_request(GPIO_FN_LAD3, NULL);
372
	gpio_request(GPIO_FN_LAD2, NULL);
373
	gpio_request(GPIO_FN_LAD1, NULL);
374
	gpio_request(GPIO_FN_LAD0, NULL);
375
	gpio_request(GPIO_FN_LFRAME, NULL);
376
	gpio_request(GPIO_FN_LRESET, NULL);
377
	gpio_request(GPIO_FN_LCLK, NULL);
378
	gpio_request(GPIO_FN_LGPIO7, NULL);
379
	gpio_request(GPIO_FN_LGPIO6, NULL);
380
	gpio_request(GPIO_FN_LGPIO5, NULL);
381
	gpio_request(GPIO_FN_LGPIO4, NULL);
382

383
	/* SPI1 (PTH) */
384
	gpio_request(GPIO_FN_SP1_MOSI, NULL);
385
	gpio_request(GPIO_FN_SP1_MISO, NULL);
386
	gpio_request(GPIO_FN_SP1_SCK, NULL);
387
	gpio_request(GPIO_FN_SP1_SCK_FB, NULL);
388
	gpio_request(GPIO_FN_SP1_SS0, NULL);
389
	gpio_request(GPIO_FN_SP1_SS1, NULL);
390

391
	/* SDHI (PTI) */
392
	gpio_request(GPIO_FN_SD_WP, NULL);
393
	gpio_request(GPIO_FN_SD_CD, NULL);
394
	gpio_request(GPIO_FN_SD_CLK, NULL);
395
	gpio_request(GPIO_FN_SD_CMD, NULL);
396
	gpio_request(GPIO_FN_SD_D3, NULL);
397
	gpio_request(GPIO_FN_SD_D2, NULL);
398
	gpio_request(GPIO_FN_SD_D1, NULL);
399
	gpio_request(GPIO_FN_SD_D0, NULL);
400

401
	/* SCIF3/4 (PTJ, PTW) */
402
	gpio_request(GPIO_FN_RTS3, NULL);
403
	gpio_request(GPIO_FN_CTS3, NULL);
404
	gpio_request(GPIO_FN_TXD3, NULL);
405
	gpio_request(GPIO_FN_RXD3, NULL);
406
	gpio_request(GPIO_FN_RTS4, NULL);
407
	gpio_request(GPIO_FN_RXD4, NULL);
408
	gpio_request(GPIO_FN_TXD4, NULL);
409
	gpio_request(GPIO_FN_CTS4, NULL);
410

411
	/* SERMUX (PTK, PTL, PTO, PTV) */
412
	gpio_request(GPIO_FN_COM2_TXD, NULL);
413
	gpio_request(GPIO_FN_COM2_RXD, NULL);
414
	gpio_request(GPIO_FN_COM2_RTS, NULL);
415
	gpio_request(GPIO_FN_COM2_CTS, NULL);
416
	gpio_request(GPIO_FN_COM2_DTR, NULL);
417
	gpio_request(GPIO_FN_COM2_DSR, NULL);
418
	gpio_request(GPIO_FN_COM2_DCD, NULL);
419
	gpio_request(GPIO_FN_COM2_RI, NULL);
420
	gpio_request(GPIO_FN_RAC_RXD, NULL);
421
	gpio_request(GPIO_FN_RAC_RTS, NULL);
422
	gpio_request(GPIO_FN_RAC_CTS, NULL);
423
	gpio_request(GPIO_FN_RAC_DTR, NULL);
424
	gpio_request(GPIO_FN_RAC_DSR, NULL);
425
	gpio_request(GPIO_FN_RAC_DCD, NULL);
426
	gpio_request(GPIO_FN_RAC_TXD, NULL);
427
	gpio_request(GPIO_FN_COM1_TXD, NULL);
428
	gpio_request(GPIO_FN_COM1_RXD, NULL);
429
	gpio_request(GPIO_FN_COM1_RTS, NULL);
430
	gpio_request(GPIO_FN_COM1_CTS, NULL);
431

432
	writeb(0x10, 0xfe470000);	/* SMR0: SerMux mode 0 */
433

434
	/* IIC (PTM, PTR, PTS) */
435
	gpio_request(GPIO_FN_SDA7, NULL);
436
	gpio_request(GPIO_FN_SCL7, NULL);
437
	gpio_request(GPIO_FN_SDA6, NULL);
438
	gpio_request(GPIO_FN_SCL6, NULL);
439
	gpio_request(GPIO_FN_SDA5, NULL);
440
	gpio_request(GPIO_FN_SCL5, NULL);
441
	gpio_request(GPIO_FN_SDA4, NULL);
442
	gpio_request(GPIO_FN_SCL4, NULL);
443
	gpio_request(GPIO_FN_SDA3, NULL);
444
	gpio_request(GPIO_FN_SCL3, NULL);
445
	gpio_request(GPIO_FN_SDA2, NULL);
446
	gpio_request(GPIO_FN_SCL2, NULL);
447
	gpio_request(GPIO_FN_SDA1, NULL);
448
	gpio_request(GPIO_FN_SCL1, NULL);
449
	gpio_request(GPIO_FN_SDA0, NULL);
450
	gpio_request(GPIO_FN_SCL0, NULL);
451

452
	/* USB (PTN) */
453
	gpio_request(GPIO_FN_VBUS_EN, NULL);
454
	gpio_request(GPIO_FN_VBUS_OC, NULL);
455

456
	/* SGPIO1/0 (PTN, PTO) */
457
	gpio_request(GPIO_FN_SGPIO1_CLK, NULL);
458
	gpio_request(GPIO_FN_SGPIO1_LOAD, NULL);
459
	gpio_request(GPIO_FN_SGPIO1_DI, NULL);
460
	gpio_request(GPIO_FN_SGPIO1_DO, NULL);
461
	gpio_request(GPIO_FN_SGPIO0_CLK, NULL);
462
	gpio_request(GPIO_FN_SGPIO0_LOAD, NULL);
463
	gpio_request(GPIO_FN_SGPIO0_DI, NULL);
464
	gpio_request(GPIO_FN_SGPIO0_DO, NULL);
465

466
	/* WDT (PTN) */
467
	gpio_request(GPIO_FN_SUB_CLKIN, NULL);
468

469
	/* System (PTT) */
470
	gpio_request(GPIO_FN_STATUS1, NULL);
471
	gpio_request(GPIO_FN_STATUS0, NULL);
472

473
	/* PWMX (PTT) */
474
	gpio_request(GPIO_FN_PWMX1, NULL);
475
	gpio_request(GPIO_FN_PWMX0, NULL);
476

477
	/* R-SPI (PTV) */
478
	gpio_request(GPIO_FN_R_SPI_MOSI, NULL);
479
	gpio_request(GPIO_FN_R_SPI_MISO, NULL);
480
	gpio_request(GPIO_FN_R_SPI_RSPCK, NULL);
481
	gpio_request(GPIO_FN_R_SPI_SSL0, NULL);
482
	gpio_request(GPIO_FN_R_SPI_SSL1, NULL);
483

484
	/* EVC (PTV, PTW) */
485
	gpio_request(GPIO_FN_EVENT7, NULL);
486
	gpio_request(GPIO_FN_EVENT6, NULL);
487
	gpio_request(GPIO_FN_EVENT5, NULL);
488
	gpio_request(GPIO_FN_EVENT4, NULL);
489
	gpio_request(GPIO_FN_EVENT3, NULL);
490
	gpio_request(GPIO_FN_EVENT2, NULL);
491
	gpio_request(GPIO_FN_EVENT1, NULL);
492
	gpio_request(GPIO_FN_EVENT0, NULL);
493

494
	/* LED for heartbeat */
495
	gpio_request(GPIO_PTU3, NULL);
496
	gpio_direction_output(GPIO_PTU3, 1);
497
	gpio_request(GPIO_PTU2, NULL);
498
	gpio_direction_output(GPIO_PTU2, 1);
499
	gpio_request(GPIO_PTU1, NULL);
500
	gpio_direction_output(GPIO_PTU1, 1);
501
	gpio_request(GPIO_PTU0, NULL);
502
	gpio_direction_output(GPIO_PTU0, 1);
503

504
	/* control for MDIO of Gigabit Ethernet */
505
	gpio_request(GPIO_PTT4, NULL);
506
	gpio_direction_output(GPIO_PTT4, 1);
507

508
	/* control for eMMC */
509
	gpio_request(GPIO_PTT7, NULL);		/* eMMC_RST# */
510
	gpio_direction_output(GPIO_PTT7, 0);
511
	gpio_request(GPIO_PTT6, NULL);		/* eMMC_INDEX# */
512
	gpio_direction_output(GPIO_PTT6, 0);
513
	gpio_request(GPIO_PTT5, NULL);		/* eMMC_PRST# */
514
	gpio_direction_output(GPIO_PTT5, 1);
515

516
	/* register SPI device information */
517
	spi_register_board_info(spi_board_info,
518
				ARRAY_SIZE(spi_board_info));
519

520
	/* General platform */
521
	return platform_add_devices(sh7757lcr_devices,
522
				    ARRAY_SIZE(sh7757lcr_devices));
523
}
524
arch_initcall(sh7757lcr_devices_setup);
525

526
/* Initialize IRQ setting */
527
void __init init_sh7757lcr_IRQ(void)
528
{
529
	plat_irq_setup_pins(IRQ_MODE_IRQ7654);
530
	plat_irq_setup_pins(IRQ_MODE_IRQ3210);
531
}
532

533
/* Initialize the board */
534
static void __init sh7757lcr_setup(char **cmdline_p)
535
{
536
	printk(KERN_INFO "Renesas R0P7757LC0012RL support.\n");
537
}
538

539
static int sh7757lcr_mode_pins(void)
540
{
541
	int value = 0;
542

543
	/* These are the factory default settings of S3 (Low active).
544
	 * If you change these dip switches then you will need to
545
	 * adjust the values below as well.
546
	 */
547
	value |= MODE_PIN0;	/* Clock Mode: 1 */
548

549
	return value;
550
}
551

552
/* The Machine Vector */
553
static struct sh_machine_vector mv_sh7757lcr __initmv = {
554
	.mv_name		= "SH7757LCR",
555
	.mv_setup		= sh7757lcr_setup,
556
	.mv_init_irq		= init_sh7757lcr_IRQ,
557
	.mv_mode_pins		= sh7757lcr_mode_pins,
558
};
559

560

561
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