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awilliam
GitHub Repository: awilliam/linux-vfio
Path: blob/master/arch/sh/boards/mach-ap325rxa/setup.c
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1
/*
2
* Renesas - AP-325RXA
3
* (Compatible with Algo System ., LTD. - AP-320A)
4
*
5
* Copyright (C) 2008 Renesas Solutions Corp.
6
* Author : Yusuke Goda <[email protected]>
7
*
8
* This file is subject to the terms and conditions of the GNU General Public
9
* License. See the file "COPYING" in the main directory of this archive
10
* for more details.
11
*/
12
13
#include <linux/init.h>
14
#include <linux/device.h>
15
#include <linux/interrupt.h>
16
#include <linux/platform_device.h>
17
#include <linux/mmc/host.h>
18
#include <linux/mmc/sh_mobile_sdhi.h>
19
#include <linux/mtd/physmap.h>
20
#include <linux/mtd/sh_flctl.h>
21
#include <linux/delay.h>
22
#include <linux/i2c.h>
23
#include <linux/smsc911x.h>
24
#include <linux/gpio.h>
25
#include <media/ov772x.h>
26
#include <media/soc_camera.h>
27
#include <media/soc_camera_platform.h>
28
#include <media/sh_mobile_ceu.h>
29
#include <video/sh_mobile_lcdc.h>
30
#include <asm/io.h>
31
#include <asm/clock.h>
32
#include <asm/suspend.h>
33
#include <cpu/sh7723.h>
34
35
static struct smsc911x_platform_config smsc911x_config = {
36
.phy_interface = PHY_INTERFACE_MODE_MII,
37
.irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
38
.irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
39
.flags = SMSC911X_USE_32BIT,
40
};
41
42
static struct resource smsc9118_resources[] = {
43
[0] = {
44
.start = 0xb6080000,
45
.end = 0xb60fffff,
46
.flags = IORESOURCE_MEM,
47
},
48
[1] = {
49
.start = 35,
50
.end = 35,
51
.flags = IORESOURCE_IRQ,
52
}
53
};
54
55
static struct platform_device smsc9118_device = {
56
.name = "smsc911x",
57
.id = -1,
58
.num_resources = ARRAY_SIZE(smsc9118_resources),
59
.resource = smsc9118_resources,
60
.dev = {
61
.platform_data = &smsc911x_config,
62
},
63
};
64
65
/*
66
* AP320 and AP325RXA has CPLD data in NOR Flash(0xA80000-0xABFFFF).
67
* If this area erased, this board can not boot.
68
*/
69
static struct mtd_partition ap325rxa_nor_flash_partitions[] = {
70
{
71
.name = "uboot",
72
.offset = 0,
73
.size = (1 * 1024 * 1024),
74
.mask_flags = MTD_WRITEABLE, /* Read-only */
75
}, {
76
.name = "kernel",
77
.offset = MTDPART_OFS_APPEND,
78
.size = (2 * 1024 * 1024),
79
}, {
80
.name = "free-area0",
81
.offset = MTDPART_OFS_APPEND,
82
.size = ((7 * 1024 * 1024) + (512 * 1024)),
83
}, {
84
.name = "CPLD-Data",
85
.offset = MTDPART_OFS_APPEND,
86
.mask_flags = MTD_WRITEABLE, /* Read-only */
87
.size = (1024 * 128 * 2),
88
}, {
89
.name = "free-area1",
90
.offset = MTDPART_OFS_APPEND,
91
.size = MTDPART_SIZ_FULL,
92
},
93
};
94
95
static struct physmap_flash_data ap325rxa_nor_flash_data = {
96
.width = 2,
97
.parts = ap325rxa_nor_flash_partitions,
98
.nr_parts = ARRAY_SIZE(ap325rxa_nor_flash_partitions),
99
};
100
101
static struct resource ap325rxa_nor_flash_resources[] = {
102
[0] = {
103
.name = "NOR Flash",
104
.start = 0x00000000,
105
.end = 0x00ffffff,
106
.flags = IORESOURCE_MEM,
107
}
108
};
109
110
static struct platform_device ap325rxa_nor_flash_device = {
111
.name = "physmap-flash",
112
.resource = ap325rxa_nor_flash_resources,
113
.num_resources = ARRAY_SIZE(ap325rxa_nor_flash_resources),
114
.dev = {
115
.platform_data = &ap325rxa_nor_flash_data,
116
},
117
};
118
119
static struct mtd_partition nand_partition_info[] = {
120
{
121
.name = "nand_data",
122
.offset = 0,
123
.size = MTDPART_SIZ_FULL,
124
},
125
};
126
127
static struct resource nand_flash_resources[] = {
128
[0] = {
129
.start = 0xa4530000,
130
.end = 0xa45300ff,
131
.flags = IORESOURCE_MEM,
132
}
133
};
134
135
static struct sh_flctl_platform_data nand_flash_data = {
136
.parts = nand_partition_info,
137
.nr_parts = ARRAY_SIZE(nand_partition_info),
138
.flcmncr_val = FCKSEL_E | TYPESEL_SET | NANWF_E,
139
.has_hwecc = 1,
140
};
141
142
static struct platform_device nand_flash_device = {
143
.name = "sh_flctl",
144
.resource = nand_flash_resources,
145
.num_resources = ARRAY_SIZE(nand_flash_resources),
146
.dev = {
147
.platform_data = &nand_flash_data,
148
},
149
};
150
151
#define FPGA_LCDREG 0xB4100180
152
#define FPGA_BKLREG 0xB4100212
153
#define FPGA_LCDREG_VAL 0x0018
154
#define PORT_MSELCRB 0xA4050182
155
#define PORT_HIZCRC 0xA405015C
156
#define PORT_DRVCRA 0xA405018A
157
#define PORT_DRVCRB 0xA405018C
158
159
static int ap320_wvga_set_brightness(void *board_data, int brightness)
160
{
161
if (brightness) {
162
gpio_set_value(GPIO_PTS3, 0);
163
__raw_writew(0x100, FPGA_BKLREG);
164
} else {
165
__raw_writew(0, FPGA_BKLREG);
166
gpio_set_value(GPIO_PTS3, 1);
167
}
168
169
return 0;
170
}
171
172
static int ap320_wvga_get_brightness(void *board_data)
173
{
174
return gpio_get_value(GPIO_PTS3);
175
}
176
177
static void ap320_wvga_power_on(void *board_data, struct fb_info *info)
178
{
179
msleep(100);
180
181
/* ASD AP-320/325 LCD ON */
182
__raw_writew(FPGA_LCDREG_VAL, FPGA_LCDREG);
183
}
184
185
static void ap320_wvga_power_off(void *board_data)
186
{
187
/* ASD AP-320/325 LCD OFF */
188
__raw_writew(0, FPGA_LCDREG);
189
}
190
191
const static struct fb_videomode ap325rxa_lcdc_modes[] = {
192
{
193
.name = "LB070WV1",
194
.xres = 800,
195
.yres = 480,
196
.left_margin = 32,
197
.right_margin = 160,
198
.hsync_len = 8,
199
.upper_margin = 63,
200
.lower_margin = 80,
201
.vsync_len = 1,
202
.sync = 0, /* hsync and vsync are active low */
203
},
204
};
205
206
static struct sh_mobile_lcdc_info lcdc_info = {
207
.clock_source = LCDC_CLK_EXTERNAL,
208
.ch[0] = {
209
.chan = LCDC_CHAN_MAINLCD,
210
.bpp = 16,
211
.interface_type = RGB18,
212
.clock_divider = 1,
213
.lcd_cfg = ap325rxa_lcdc_modes,
214
.num_cfg = ARRAY_SIZE(ap325rxa_lcdc_modes),
215
.lcd_size_cfg = { /* 7.0 inch */
216
.width = 152,
217
.height = 91,
218
},
219
.board_cfg = {
220
.display_on = ap320_wvga_power_on,
221
.display_off = ap320_wvga_power_off,
222
.set_brightness = ap320_wvga_set_brightness,
223
.get_brightness = ap320_wvga_get_brightness,
224
},
225
.bl_info = {
226
.name = "sh_mobile_lcdc_bl",
227
.max_brightness = 1,
228
},
229
}
230
};
231
232
static struct resource lcdc_resources[] = {
233
[0] = {
234
.name = "LCDC",
235
.start = 0xfe940000, /* P4-only space */
236
.end = 0xfe942fff,
237
.flags = IORESOURCE_MEM,
238
},
239
[1] = {
240
.start = 28,
241
.flags = IORESOURCE_IRQ,
242
},
243
};
244
245
static struct platform_device lcdc_device = {
246
.name = "sh_mobile_lcdc_fb",
247
.num_resources = ARRAY_SIZE(lcdc_resources),
248
.resource = lcdc_resources,
249
.dev = {
250
.platform_data = &lcdc_info,
251
},
252
.archdata = {
253
.hwblk_id = HWBLK_LCDC,
254
},
255
};
256
257
static void camera_power(int val)
258
{
259
gpio_set_value(GPIO_PTZ5, val); /* RST_CAM/RSTB */
260
mdelay(10);
261
}
262
263
#ifdef CONFIG_I2C
264
/* support for the old ncm03j camera */
265
static unsigned char camera_ncm03j_magic[] =
266
{
267
0x87, 0x00, 0x88, 0x08, 0x89, 0x01, 0x8A, 0xE8,
268
0x1D, 0x00, 0x1E, 0x8A, 0x21, 0x00, 0x33, 0x36,
269
0x36, 0x60, 0x37, 0x08, 0x3B, 0x31, 0x44, 0x0F,
270
0x46, 0xF0, 0x4B, 0x28, 0x4C, 0x21, 0x4D, 0x55,
271
0x4E, 0x1B, 0x4F, 0xC7, 0x50, 0xFC, 0x51, 0x12,
272
0x58, 0x02, 0x66, 0xC0, 0x67, 0x46, 0x6B, 0xA0,
273
0x6C, 0x34, 0x7E, 0x25, 0x7F, 0x25, 0x8D, 0x0F,
274
0x92, 0x40, 0x93, 0x04, 0x94, 0x26, 0x95, 0x0A,
275
0x99, 0x03, 0x9A, 0xF0, 0x9B, 0x14, 0x9D, 0x7A,
276
0xC5, 0x02, 0xD6, 0x07, 0x59, 0x00, 0x5A, 0x1A,
277
0x5B, 0x2A, 0x5C, 0x37, 0x5D, 0x42, 0x5E, 0x56,
278
0xC8, 0x00, 0xC9, 0x1A, 0xCA, 0x2A, 0xCB, 0x37,
279
0xCC, 0x42, 0xCD, 0x56, 0xCE, 0x00, 0xCF, 0x1A,
280
0xD0, 0x2A, 0xD1, 0x37, 0xD2, 0x42, 0xD3, 0x56,
281
0x5F, 0x68, 0x60, 0x87, 0x61, 0xA3, 0x62, 0xBC,
282
0x63, 0xD4, 0x64, 0xEA, 0xD6, 0x0F,
283
};
284
285
static int camera_probe(void)
286
{
287
struct i2c_adapter *a = i2c_get_adapter(0);
288
struct i2c_msg msg;
289
int ret;
290
291
if (!a)
292
return -ENODEV;
293
294
camera_power(1);
295
msg.addr = 0x6e;
296
msg.buf = camera_ncm03j_magic;
297
msg.len = 2;
298
msg.flags = 0;
299
ret = i2c_transfer(a, &msg, 1);
300
camera_power(0);
301
302
return ret;
303
}
304
305
static int camera_set_capture(struct soc_camera_platform_info *info,
306
int enable)
307
{
308
struct i2c_adapter *a = i2c_get_adapter(0);
309
struct i2c_msg msg;
310
int ret = 0;
311
int i;
312
313
camera_power(0);
314
if (!enable)
315
return 0; /* no disable for now */
316
317
camera_power(1);
318
for (i = 0; i < ARRAY_SIZE(camera_ncm03j_magic); i += 2) {
319
u_int8_t buf[8];
320
321
msg.addr = 0x6e;
322
msg.buf = buf;
323
msg.len = 2;
324
msg.flags = 0;
325
326
buf[0] = camera_ncm03j_magic[i];
327
buf[1] = camera_ncm03j_magic[i + 1];
328
329
ret = (ret < 0) ? ret : i2c_transfer(a, &msg, 1);
330
}
331
332
return ret;
333
}
334
335
static int ap325rxa_camera_add(struct soc_camera_link *icl, struct device *dev);
336
static void ap325rxa_camera_del(struct soc_camera_link *icl);
337
338
static struct soc_camera_platform_info camera_info = {
339
.format_name = "UYVY",
340
.format_depth = 16,
341
.format = {
342
.code = V4L2_MBUS_FMT_UYVY8_2X8,
343
.colorspace = V4L2_COLORSPACE_SMPTE170M,
344
.field = V4L2_FIELD_NONE,
345
.width = 640,
346
.height = 480,
347
},
348
.bus_param = SOCAM_PCLK_SAMPLE_RISING | SOCAM_HSYNC_ACTIVE_HIGH |
349
SOCAM_VSYNC_ACTIVE_HIGH | SOCAM_MASTER | SOCAM_DATAWIDTH_8 |
350
SOCAM_DATA_ACTIVE_HIGH,
351
.set_capture = camera_set_capture,
352
};
353
354
static struct soc_camera_link camera_link = {
355
.bus_id = 0,
356
.add_device = ap325rxa_camera_add,
357
.del_device = ap325rxa_camera_del,
358
.module_name = "soc_camera_platform",
359
.priv = &camera_info,
360
};
361
362
static struct platform_device *camera_device;
363
364
static void ap325rxa_camera_release(struct device *dev)
365
{
366
soc_camera_platform_release(&camera_device);
367
}
368
369
static int ap325rxa_camera_add(struct soc_camera_link *icl,
370
struct device *dev)
371
{
372
int ret = soc_camera_platform_add(icl, dev, &camera_device, &camera_link,
373
ap325rxa_camera_release, 0);
374
if (ret < 0)
375
return ret;
376
377
ret = camera_probe();
378
if (ret < 0)
379
soc_camera_platform_del(icl, camera_device, &camera_link);
380
381
return ret;
382
}
383
384
static void ap325rxa_camera_del(struct soc_camera_link *icl)
385
{
386
soc_camera_platform_del(icl, camera_device, &camera_link);
387
}
388
#endif /* CONFIG_I2C */
389
390
static int ov7725_power(struct device *dev, int mode)
391
{
392
camera_power(0);
393
if (mode)
394
camera_power(1);
395
396
return 0;
397
}
398
399
static struct sh_mobile_ceu_info sh_mobile_ceu_info = {
400
.flags = SH_CEU_FLAG_USE_8BIT_BUS,
401
};
402
403
static struct resource ceu_resources[] = {
404
[0] = {
405
.name = "CEU",
406
.start = 0xfe910000,
407
.end = 0xfe91009f,
408
.flags = IORESOURCE_MEM,
409
},
410
[1] = {
411
.start = 52,
412
.flags = IORESOURCE_IRQ,
413
},
414
[2] = {
415
/* place holder for contiguous memory */
416
},
417
};
418
419
static struct platform_device ceu_device = {
420
.name = "sh_mobile_ceu",
421
.id = 0, /* "ceu0" clock */
422
.num_resources = ARRAY_SIZE(ceu_resources),
423
.resource = ceu_resources,
424
.dev = {
425
.platform_data = &sh_mobile_ceu_info,
426
},
427
.archdata = {
428
.hwblk_id = HWBLK_CEU,
429
},
430
};
431
432
static struct resource sdhi0_cn3_resources[] = {
433
[0] = {
434
.name = "SDHI0",
435
.start = 0x04ce0000,
436
.end = 0x04ce00ff,
437
.flags = IORESOURCE_MEM,
438
},
439
[1] = {
440
.start = 100,
441
.flags = IORESOURCE_IRQ,
442
},
443
};
444
445
static struct sh_mobile_sdhi_info sdhi0_cn3_data = {
446
.tmio_caps = MMC_CAP_SDIO_IRQ,
447
};
448
449
static struct platform_device sdhi0_cn3_device = {
450
.name = "sh_mobile_sdhi",
451
.id = 0, /* "sdhi0" clock */
452
.num_resources = ARRAY_SIZE(sdhi0_cn3_resources),
453
.resource = sdhi0_cn3_resources,
454
.dev = {
455
.platform_data = &sdhi0_cn3_data,
456
},
457
.archdata = {
458
.hwblk_id = HWBLK_SDHI0,
459
},
460
};
461
462
static struct resource sdhi1_cn7_resources[] = {
463
[0] = {
464
.name = "SDHI1",
465
.start = 0x04cf0000,
466
.end = 0x04cf00ff,
467
.flags = IORESOURCE_MEM,
468
},
469
[1] = {
470
.start = 23,
471
.flags = IORESOURCE_IRQ,
472
},
473
};
474
475
static struct sh_mobile_sdhi_info sdhi1_cn7_data = {
476
.tmio_caps = MMC_CAP_SDIO_IRQ,
477
};
478
479
static struct platform_device sdhi1_cn7_device = {
480
.name = "sh_mobile_sdhi",
481
.id = 1, /* "sdhi1" clock */
482
.num_resources = ARRAY_SIZE(sdhi1_cn7_resources),
483
.resource = sdhi1_cn7_resources,
484
.dev = {
485
.platform_data = &sdhi1_cn7_data,
486
},
487
.archdata = {
488
.hwblk_id = HWBLK_SDHI1,
489
},
490
};
491
492
static struct i2c_board_info __initdata ap325rxa_i2c_devices[] = {
493
{
494
I2C_BOARD_INFO("pcf8563", 0x51),
495
},
496
};
497
498
static struct i2c_board_info ap325rxa_i2c_camera[] = {
499
{
500
I2C_BOARD_INFO("ov772x", 0x21),
501
},
502
};
503
504
static struct ov772x_camera_info ov7725_info = {
505
.flags = OV772X_FLAG_VFLIP | OV772X_FLAG_HFLIP | \
506
OV772X_FLAG_8BIT,
507
.edgectrl = OV772X_AUTO_EDGECTRL(0xf, 0),
508
};
509
510
static struct soc_camera_link ov7725_link = {
511
.bus_id = 0,
512
.power = ov7725_power,
513
.board_info = &ap325rxa_i2c_camera[0],
514
.i2c_adapter_id = 0,
515
.priv = &ov7725_info,
516
};
517
518
static struct platform_device ap325rxa_camera[] = {
519
{
520
.name = "soc-camera-pdrv",
521
.id = 0,
522
.dev = {
523
.platform_data = &ov7725_link,
524
},
525
}, {
526
.name = "soc-camera-pdrv",
527
.id = 1,
528
.dev = {
529
.platform_data = &camera_link,
530
},
531
},
532
};
533
534
static struct platform_device *ap325rxa_devices[] __initdata = {
535
&smsc9118_device,
536
&ap325rxa_nor_flash_device,
537
&lcdc_device,
538
&ceu_device,
539
&nand_flash_device,
540
&sdhi0_cn3_device,
541
&sdhi1_cn7_device,
542
&ap325rxa_camera[0],
543
&ap325rxa_camera[1],
544
};
545
546
extern char ap325rxa_sdram_enter_start;
547
extern char ap325rxa_sdram_enter_end;
548
extern char ap325rxa_sdram_leave_start;
549
extern char ap325rxa_sdram_leave_end;
550
551
static int __init ap325rxa_devices_setup(void)
552
{
553
/* register board specific self-refresh code */
554
sh_mobile_register_self_refresh(SUSP_SH_STANDBY | SUSP_SH_SF,
555
&ap325rxa_sdram_enter_start,
556
&ap325rxa_sdram_enter_end,
557
&ap325rxa_sdram_leave_start,
558
&ap325rxa_sdram_leave_end);
559
560
/* LD3 and LD4 LEDs */
561
gpio_request(GPIO_PTX5, NULL); /* RUN */
562
gpio_direction_output(GPIO_PTX5, 1);
563
gpio_export(GPIO_PTX5, 0);
564
565
gpio_request(GPIO_PTX4, NULL); /* INDICATOR */
566
gpio_direction_output(GPIO_PTX4, 0);
567
gpio_export(GPIO_PTX4, 0);
568
569
/* SW1 input */
570
gpio_request(GPIO_PTF7, NULL); /* MODE */
571
gpio_direction_input(GPIO_PTF7);
572
gpio_export(GPIO_PTF7, 0);
573
574
/* LCDC */
575
gpio_request(GPIO_FN_LCDD15, NULL);
576
gpio_request(GPIO_FN_LCDD14, NULL);
577
gpio_request(GPIO_FN_LCDD13, NULL);
578
gpio_request(GPIO_FN_LCDD12, NULL);
579
gpio_request(GPIO_FN_LCDD11, NULL);
580
gpio_request(GPIO_FN_LCDD10, NULL);
581
gpio_request(GPIO_FN_LCDD9, NULL);
582
gpio_request(GPIO_FN_LCDD8, NULL);
583
gpio_request(GPIO_FN_LCDD7, NULL);
584
gpio_request(GPIO_FN_LCDD6, NULL);
585
gpio_request(GPIO_FN_LCDD5, NULL);
586
gpio_request(GPIO_FN_LCDD4, NULL);
587
gpio_request(GPIO_FN_LCDD3, NULL);
588
gpio_request(GPIO_FN_LCDD2, NULL);
589
gpio_request(GPIO_FN_LCDD1, NULL);
590
gpio_request(GPIO_FN_LCDD0, NULL);
591
gpio_request(GPIO_FN_LCDLCLK_PTR, NULL);
592
gpio_request(GPIO_FN_LCDDCK, NULL);
593
gpio_request(GPIO_FN_LCDVEPWC, NULL);
594
gpio_request(GPIO_FN_LCDVCPWC, NULL);
595
gpio_request(GPIO_FN_LCDVSYN, NULL);
596
gpio_request(GPIO_FN_LCDHSYN, NULL);
597
gpio_request(GPIO_FN_LCDDISP, NULL);
598
gpio_request(GPIO_FN_LCDDON, NULL);
599
600
/* LCD backlight */
601
gpio_request(GPIO_PTS3, NULL);
602
gpio_direction_output(GPIO_PTS3, 1);
603
604
/* CEU */
605
gpio_request(GPIO_FN_VIO_CLK2, NULL);
606
gpio_request(GPIO_FN_VIO_VD2, NULL);
607
gpio_request(GPIO_FN_VIO_HD2, NULL);
608
gpio_request(GPIO_FN_VIO_FLD, NULL);
609
gpio_request(GPIO_FN_VIO_CKO, NULL);
610
gpio_request(GPIO_FN_VIO_D15, NULL);
611
gpio_request(GPIO_FN_VIO_D14, NULL);
612
gpio_request(GPIO_FN_VIO_D13, NULL);
613
gpio_request(GPIO_FN_VIO_D12, NULL);
614
gpio_request(GPIO_FN_VIO_D11, NULL);
615
gpio_request(GPIO_FN_VIO_D10, NULL);
616
gpio_request(GPIO_FN_VIO_D9, NULL);
617
gpio_request(GPIO_FN_VIO_D8, NULL);
618
619
gpio_request(GPIO_PTZ7, NULL);
620
gpio_direction_output(GPIO_PTZ7, 0); /* OE_CAM */
621
gpio_request(GPIO_PTZ6, NULL);
622
gpio_direction_output(GPIO_PTZ6, 0); /* STBY_CAM */
623
gpio_request(GPIO_PTZ5, NULL);
624
gpio_direction_output(GPIO_PTZ5, 0); /* RST_CAM */
625
gpio_request(GPIO_PTZ4, NULL);
626
gpio_direction_output(GPIO_PTZ4, 0); /* SADDR */
627
628
__raw_writew(__raw_readw(PORT_MSELCRB) & ~0x0001, PORT_MSELCRB);
629
630
/* FLCTL */
631
gpio_request(GPIO_FN_FCE, NULL);
632
gpio_request(GPIO_FN_NAF7, NULL);
633
gpio_request(GPIO_FN_NAF6, NULL);
634
gpio_request(GPIO_FN_NAF5, NULL);
635
gpio_request(GPIO_FN_NAF4, NULL);
636
gpio_request(GPIO_FN_NAF3, NULL);
637
gpio_request(GPIO_FN_NAF2, NULL);
638
gpio_request(GPIO_FN_NAF1, NULL);
639
gpio_request(GPIO_FN_NAF0, NULL);
640
gpio_request(GPIO_FN_FCDE, NULL);
641
gpio_request(GPIO_FN_FOE, NULL);
642
gpio_request(GPIO_FN_FSC, NULL);
643
gpio_request(GPIO_FN_FWE, NULL);
644
gpio_request(GPIO_FN_FRB, NULL);
645
646
__raw_writew(0, PORT_HIZCRC);
647
__raw_writew(0xFFFF, PORT_DRVCRA);
648
__raw_writew(0xFFFF, PORT_DRVCRB);
649
650
platform_resource_setup_memory(&ceu_device, "ceu", 4 << 20);
651
652
/* SDHI0 - CN3 - SD CARD */
653
gpio_request(GPIO_FN_SDHI0CD_PTD, NULL);
654
gpio_request(GPIO_FN_SDHI0WP_PTD, NULL);
655
gpio_request(GPIO_FN_SDHI0D3_PTD, NULL);
656
gpio_request(GPIO_FN_SDHI0D2_PTD, NULL);
657
gpio_request(GPIO_FN_SDHI0D1_PTD, NULL);
658
gpio_request(GPIO_FN_SDHI0D0_PTD, NULL);
659
gpio_request(GPIO_FN_SDHI0CMD_PTD, NULL);
660
gpio_request(GPIO_FN_SDHI0CLK_PTD, NULL);
661
662
/* SDHI1 - CN7 - MICRO SD CARD */
663
gpio_request(GPIO_FN_SDHI1CD, NULL);
664
gpio_request(GPIO_FN_SDHI1D3, NULL);
665
gpio_request(GPIO_FN_SDHI1D2, NULL);
666
gpio_request(GPIO_FN_SDHI1D1, NULL);
667
gpio_request(GPIO_FN_SDHI1D0, NULL);
668
gpio_request(GPIO_FN_SDHI1CMD, NULL);
669
gpio_request(GPIO_FN_SDHI1CLK, NULL);
670
671
i2c_register_board_info(0, ap325rxa_i2c_devices,
672
ARRAY_SIZE(ap325rxa_i2c_devices));
673
674
return platform_add_devices(ap325rxa_devices,
675
ARRAY_SIZE(ap325rxa_devices));
676
}
677
arch_initcall(ap325rxa_devices_setup);
678
679
/* Return the board specific boot mode pin configuration */
680
static int ap325rxa_mode_pins(void)
681
{
682
/* MD0=0, MD1=0, MD2=0: Clock Mode 0
683
* MD3=0: 16-bit Area0 Bus Width
684
* MD5=1: Little Endian
685
* TSTMD=1, MD8=1: Test Mode Disabled
686
*/
687
return MODE_PIN5 | MODE_PIN8;
688
}
689
690
static struct sh_machine_vector mv_ap325rxa __initmv = {
691
.mv_name = "AP-325RXA",
692
.mv_mode_pins = ap325rxa_mode_pins,
693
};
694
695