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awilliam
GitHub Repository: awilliam/linux-vfio
 Path: blob/master/arch/sh/boards/mach-hp6xx/pm.c
15126 views
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/*

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 * hp6x0 Power Management Routines

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 *

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 * Copyright (c) 2006 Andriy Skulysh <[email protected]>

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 *

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 * This program is free software; you can redistribute it and/or

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 * modify it under the terms of the GNU General Public License.

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 */

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#include <linux/init.h>

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#include <linux/suspend.h>

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#include <linux/errno.h>

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#include <linux/time.h>

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#include <linux/delay.h>

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#include <linux/gfp.h>

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#include <asm/io.h>

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#include <asm/hd64461.h>

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#include <mach/hp6xx.h>

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#include <cpu/dac.h>

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#include <asm/freq.h>

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#include <asm/watchdog.h>

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#define INTR_OFFSET	0x600

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#define STBCR		0xffffff82

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#define STBCR2		0xffffff88

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#define STBCR_STBY	0x80

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#define STBCR_MSTP2	0x04

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#define MCR		0xffffff68

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#define RTCNT		0xffffff70

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#define MCR_RMODE	2

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#define MCR_RFSH	4

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extern u8 wakeup_start;

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extern u8 wakeup_end;

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static void pm_enter(void)

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{

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	u8 stbcr, csr;

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	u16 frqcr, mcr;

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	u32 vbr_new, vbr_old;

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	set_bl_bit();

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	/* set wdt */

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	csr = sh_wdt_read_csr();

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	csr &= ~WTCSR_TME;

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	csr |= WTCSR_CKS_4096;

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	sh_wdt_write_csr(csr);

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	csr = sh_wdt_read_csr();

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	sh_wdt_write_cnt(0);

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	/* disable PLL1 */

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	frqcr = __raw_readw(FRQCR);

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	frqcr &= ~(FRQCR_PLLEN | FRQCR_PSTBY);

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	__raw_writew(frqcr, FRQCR);

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	/* enable standby */

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	stbcr = __raw_readb(STBCR);

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	__raw_writeb(stbcr | STBCR_STBY | STBCR_MSTP2, STBCR);

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	/* set self-refresh */

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	mcr = __raw_readw(MCR);

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	__raw_writew(mcr & ~MCR_RFSH, MCR);

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	/* set interrupt handler */

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	asm volatile("stc vbr, %0" : "=r" (vbr_old));

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	vbr_new = get_zeroed_page(GFP_ATOMIC);

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	udelay(50);

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	memcpy((void*)(vbr_new + INTR_OFFSET),

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	       &wakeup_start, &wakeup_end - &wakeup_start);

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	asm volatile("ldc %0, vbr" : : "r" (vbr_new));

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	__raw_writew(0, RTCNT);

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	__raw_writew(mcr | MCR_RFSH | MCR_RMODE, MCR);

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	cpu_sleep();

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	asm volatile("ldc %0, vbr" : : "r" (vbr_old));

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	free_page(vbr_new);

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	/* enable PLL1 */

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	frqcr = __raw_readw(FRQCR);

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	frqcr |= FRQCR_PSTBY;

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	__raw_writew(frqcr, FRQCR);

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	udelay(50);

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	frqcr |= FRQCR_PLLEN;

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	__raw_writew(frqcr, FRQCR);

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	__raw_writeb(stbcr, STBCR);

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	clear_bl_bit();

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}

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static int hp6x0_pm_enter(suspend_state_t state)

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{

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	u8 stbcr, stbcr2;

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#ifdef CONFIG_HD64461_ENABLER

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	u8 scr;

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	u16 hd64461_stbcr;

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#endif

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#ifdef CONFIG_HD64461_ENABLER

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	outb(0, HD64461_PCC1CSCIER);

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	scr = inb(HD64461_PCC1SCR);

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	scr |= HD64461_PCCSCR_VCC1;

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	outb(scr, HD64461_PCC1SCR);

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	hd64461_stbcr = inw(HD64461_STBCR);

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	hd64461_stbcr |= HD64461_STBCR_SPC1ST;

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	outw(hd64461_stbcr, HD64461_STBCR);

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#endif

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	__raw_writeb(0x1f, DACR);

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	stbcr = __raw_readb(STBCR);

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	__raw_writeb(0x01, STBCR);

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	stbcr2 = __raw_readb(STBCR2);

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	__raw_writeb(0x7f , STBCR2);

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	outw(0xf07f, HD64461_SCPUCR);

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	pm_enter();

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	outw(0, HD64461_SCPUCR);

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	__raw_writeb(stbcr, STBCR);

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	__raw_writeb(stbcr2, STBCR2);

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#ifdef CONFIG_HD64461_ENABLER

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	hd64461_stbcr = inw(HD64461_STBCR);

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	hd64461_stbcr &= ~HD64461_STBCR_SPC1ST;

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	outw(hd64461_stbcr, HD64461_STBCR);

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	outb(0x4c, HD64461_PCC1CSCIER);

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	outb(0x00, HD64461_PCC1CSCR);

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#endif

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	return 0;

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}

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static const struct platform_suspend_ops hp6x0_pm_ops = {

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	.enter		= hp6x0_pm_enter,

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	.valid		= suspend_valid_only_mem,

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};

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static int __init hp6x0_pm_init(void)

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{

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	suspend_set_ops(&hp6x0_pm_ops);

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	return 0;

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}

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late_initcall(hp6x0_pm_init);

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