Path: blob/master/arch/sh/drivers/pci/pci-sh7780.h
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/*1* Low-Level PCI Support for SH7780 targets2*3* Dustin McIntire ([email protected]) (c) 20014* Paul Mundt ([email protected]) (c) 20035*6* May be copied or modified under the terms of the GNU General Public7* License. See linux/COPYING for more information.8*9*/1011#ifndef _PCI_SH7780_H_12#define _PCI_SH7780_H_1314/* SH7780 Control Registers */15#define PCIECR 0xFE00000816#define PCIECR_ENBL 0x011718/* SH7780 Specific Values */19#define SH7780_PCI_CONFIG_BASE 0xFD000000 /* Config space base addr */20#define SH7780_PCI_CONFIG_SIZE 0x01000000 /* Config space size */2122#define SH7780_PCIREG_BASE 0xFE040000 /* PCI regs base address */2324/* SH7780 PCI Config Registers */25#define SH7780_PCIIR 0x114 /* PCI Interrupt Register */26#define SH7780_PCIIMR 0x118 /* PCI Interrupt Mask Register */27#define SH7780_PCIAIR 0x11C /* Error Address Register */28#define SH7780_PCICIR 0x120 /* Error Command/Data Register */29#define SH7780_PCIAINT 0x130 /* Arbiter Interrupt Register */30#define SH7780_PCIAINTM 0x134 /* Arbiter Int. Mask Register */31#define SH7780_PCIBMIR 0x138 /* Error Bus Master Register */32#define SH7780_PCIPAR 0x1C0 /* PIO Address Register */33#define SH7780_PCIPINT 0x1CC /* Power Mgmnt Int. Register */34#define SH7780_PCIPINTM 0x1D0 /* Power Mgmnt Mask Register */3536#define SH7780_PCIMBR(x) (0x1E0 + ((x) * 8))37#define SH7780_PCIMBMR(x) (0x1E4 + ((x) * 8))38#define SH7780_PCIIOBR 0x1F839#define SH7780_PCIIOBMR 0x1FC40#define SH7780_PCICSCR0 0x210 /* Cache Snoop1 Cnt. Register */41#define SH7780_PCICSCR1 0x214 /* Cache Snoop2 Cnt. Register */42#define SH7780_PCICSAR0 0x218 /* Cache Snoop1 Addr. Register */43#define SH7780_PCICSAR1 0x21C /* Cache Snoop2 Addr. Register */4445#endif /* _PCI_SH7780_H_ */464748