Path: blob/master/arch/sh/include/cpu-sh2/cpu/cache.h
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/*1* include/asm-sh/cpu-sh2/cache.h2*3* Copyright (C) 2003 Paul Mundt4*5* This file is subject to the terms and conditions of the GNU General Public6* License. See the file "COPYING" in the main directory of this archive7* for more details.8*/9#ifndef __ASM_CPU_SH2_CACHE_H10#define __ASM_CPU_SH2_CACHE_H1112#define L1_CACHE_SHIFT 41314#define SH_CACHE_VALID 115#define SH_CACHE_UPDATED 216#define SH_CACHE_COMBINED 417#define SH_CACHE_ASSOC 81819#if defined(CONFIG_CPU_SUBTYPE_SH7619)20#define CCR 0xffffffec2122#define CCR_CACHE_CE 0x01 /* Cache enable */23#define CCR_CACHE_WT 0x02 /* CCR[bit1=1,bit2=1] */24/* 0x00000000-0x7fffffff: Write-through */25/* 0x80000000-0x9fffffff: Write-back */26/* 0xc0000000-0xdfffffff: Write-through */27#define CCR_CACHE_CB 0x04 /* CCR[bit1=0,bit2=0] */28/* 0x00000000-0x7fffffff: Write-back */29/* 0x80000000-0x9fffffff: Write-through */30/* 0xc0000000-0xdfffffff: Write-back */31#define CCR_CACHE_CF 0x08 /* Cache invalidate */3233#define CACHE_OC_ADDRESS_ARRAY 0xf000000034#define CACHE_OC_DATA_ARRAY 0xf10000003536#define CCR_CACHE_ENABLE CCR_CACHE_CE37#define CCR_CACHE_INVALIDATE CCR_CACHE_CF38#define CACHE_PHYSADDR_MASK 0x1ffffc003940#endif4142#endif /* __ASM_CPU_SH2_CACHE_H */434445