Path: blob/master/arch/sh/include/cpu-sh3/cpu/cache.h
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/*1* include/asm-sh/cpu-sh3/cache.h2*3* Copyright (C) 1999 Niibe Yutaka4*5* This file is subject to the terms and conditions of the GNU General Public6* License. See the file "COPYING" in the main directory of this archive7* for more details.8*/9#ifndef __ASM_CPU_SH3_CACHE_H10#define __ASM_CPU_SH3_CACHE_H1112#define L1_CACHE_SHIFT 41314#define SH_CACHE_VALID 115#define SH_CACHE_UPDATED 216#define SH_CACHE_COMBINED 417#define SH_CACHE_ASSOC 81819#define CCR 0xffffffec /* Address of Cache Control Register */2021#define CCR_CACHE_CE 0x01 /* Cache Enable */22#define CCR_CACHE_WT 0x02 /* Write-Through (for P0,U0,P3) (else writeback) */23#define CCR_CACHE_CB 0x04 /* Write-Back (for P1) (else writethrough) */24#define CCR_CACHE_CF 0x08 /* Cache Flush */25#define CCR_CACHE_ORA 0x20 /* RAM mode */2627#define CACHE_OC_ADDRESS_ARRAY 0xf000000028#define CACHE_PHYSADDR_MASK 0x1ffffc002930#define CCR_CACHE_ENABLE CCR_CACHE_CE31#define CCR_CACHE_INVALIDATE CCR_CACHE_CF3233#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \34defined(CONFIG_CPU_SUBTYPE_SH7710) || \35defined(CONFIG_CPU_SUBTYPE_SH7720) || \36defined(CONFIG_CPU_SUBTYPE_SH7721)37#define CCR3_REG 0xa40000b438#define CCR_CACHE_16KB 0x0001000039#define CCR_CACHE_32KB 0x0002000040#endif4142#endif /* __ASM_CPU_SH3_CACHE_H */434445