Path: blob/master/arch/sh/include/cpu-sh3/cpu/dma-register.h
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/*1* SH3 CPU-specific DMA definitions, used by both DMA drivers2*3* Copyright (C) 2010 Guennadi Liakhovetski <[email protected]>4*5* This program is free software; you can redistribute it and/or modify6* it under the terms of the GNU General Public License version 2 as7* published by the Free Software Foundation.8*/9#ifndef CPU_DMA_REGISTER_H10#define CPU_DMA_REGISTER_H1112#define CHCR_TS_LOW_MASK 0x1813#define CHCR_TS_LOW_SHIFT 314#define CHCR_TS_HIGH_MASK 015#define CHCR_TS_HIGH_SHIFT 01617#define DMAOR_INIT DMAOR_DME1819/*20* The SuperH DMAC supports a number of transmit sizes, we list them here,21* with their respective values as they appear in the CHCR registers.22*/23enum {24XMIT_SZ_8BIT,25XMIT_SZ_16BIT,26XMIT_SZ_32BIT,27XMIT_SZ_128BIT,28};2930/* log2(size / 8) - used to calculate number of transfers */31#define TS_SHIFT { \32[XMIT_SZ_8BIT] = 0, \33[XMIT_SZ_16BIT] = 1, \34[XMIT_SZ_32BIT] = 2, \35[XMIT_SZ_128BIT] = 4, \36}3738#define TS_INDEX2VAL(i) (((i) & 3) << CHCR_TS_LOW_SHIFT)3940#endif414243