Path: blob/master/arch/sh/include/cpu-sh3/cpu/mmu_context.h
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/*1* include/asm-sh/cpu-sh3/mmu_context.h2*3* Copyright (C) 1999 Niibe Yutaka4*5* This file is subject to the terms and conditions of the GNU General Public6* License. See the file "COPYING" in the main directory of this archive7* for more details.8*/9#ifndef __ASM_CPU_SH3_MMU_CONTEXT_H10#define __ASM_CPU_SH3_MMU_CONTEXT_H1112#define MMU_PTEH 0xFFFFFFF0 /* Page table entry register HIGH */13#define MMU_PTEL 0xFFFFFFF4 /* Page table entry register LOW */14#define MMU_TTB 0xFFFFFFF8 /* Translation table base register */15#define MMU_TEA 0xFFFFFFFC /* TLB Exception Address */1617#define MMUCR 0xFFFFFFE0 /* MMU Control Register */18#define MMUCR_TI (1 << 2) /* TLB flush bit */1920#define MMU_TLB_ADDRESS_ARRAY 0xF200000021#define MMU_PAGE_ASSOC_BIT 0x802223#define MMU_NTLB_ENTRIES 128 /* for 7708 */24#define MMU_NTLB_WAYS 425#define MMU_CONTROL_INIT 0x007 /* SV=0, TF=1, IX=1, AT=1 */2627#define TRA 0xffffffd028#define EXPEVT 0xffffffd42930#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \31defined(CONFIG_CPU_SUBTYPE_SH7706) || \32defined(CONFIG_CPU_SUBTYPE_SH7707) || \33defined(CONFIG_CPU_SUBTYPE_SH7709) || \34defined(CONFIG_CPU_SUBTYPE_SH7710) || \35defined(CONFIG_CPU_SUBTYPE_SH7712) || \36defined(CONFIG_CPU_SUBTYPE_SH7720) || \37defined(CONFIG_CPU_SUBTYPE_SH7721)38#define INTEVT 0xa4000000 /* INTEVTE2(0xa4000000) */39#else40#define INTEVT 0xffffffd841#endif4243#endif /* __ASM_CPU_SH3_MMU_CONTEXT_H */44454647