Path: blob/master/arch/sh/include/cpu-sh4/cpu/cache.h
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/*1* include/asm-sh/cpu-sh4/cache.h2*3* Copyright (C) 1999 Niibe Yutaka4*5* This file is subject to the terms and conditions of the GNU General Public6* License. See the file "COPYING" in the main directory of this archive7* for more details.8*/9#ifndef __ASM_CPU_SH4_CACHE_H10#define __ASM_CPU_SH4_CACHE_H1112#define L1_CACHE_SHIFT 51314#define SH_CACHE_VALID 115#define SH_CACHE_UPDATED 216#define SH_CACHE_COMBINED 417#define SH_CACHE_ASSOC 81819#define CCR 0xff00001c /* Address of Cache Control Register */20#define CCR_CACHE_OCE 0x0001 /* Operand Cache Enable */21#define CCR_CACHE_WT 0x0002 /* Write-Through (for P0,U0,P3) (else writeback)*/22#define CCR_CACHE_CB 0x0004 /* Copy-Back (for P1) (else writethrough) */23#define CCR_CACHE_OCI 0x0008 /* OC Invalidate */24#define CCR_CACHE_ORA 0x0020 /* OC RAM Mode */25#define CCR_CACHE_OIX 0x0080 /* OC Index Enable */26#define CCR_CACHE_ICE 0x0100 /* Instruction Cache Enable */27#define CCR_CACHE_ICI 0x0800 /* IC Invalidate */28#define CCR_CACHE_IIX 0x8000 /* IC Index Enable */29#ifndef CONFIG_CPU_SH4A30#define CCR_CACHE_EMODE 0x80000000 /* EMODE Enable */31#endif3233/* Default CCR setup: 8k+16k-byte cache,P1-wb,enable */34#define CCR_CACHE_ENABLE (CCR_CACHE_OCE|CCR_CACHE_ICE)35#define CCR_CACHE_INVALIDATE (CCR_CACHE_OCI|CCR_CACHE_ICI)3637#define CACHE_IC_ADDRESS_ARRAY 0xf000000038#define CACHE_OC_ADDRESS_ARRAY 0xf40000003940#define RAMCR 0xFF0000744142#endif /* __ASM_CPU_SH4_CACHE_H */43444546