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awilliam
GitHub Repository: awilliam/linux-vfio
 Path: blob/master/arch/sh/include/cpu-sh4/cpu/dma-sh4a.h
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#ifndef __ASM_SH_CPU_SH4_DMA_SH7780_H

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#define __ASM_SH_CPU_SH4_DMA_SH7780_H

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#if defined(CONFIG_CPU_SUBTYPE_SH7343) || \

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	defined(CONFIG_CPU_SUBTYPE_SH7730)

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#define DMTE0_IRQ	48

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#define DMTE4_IRQ	76

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#define DMAE0_IRQ	78	/* DMA Error IRQ*/

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#define SH_DMAC_BASE0	0xFE008020

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#define SH_DMARS_BASE0	0xFE009000

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#elif defined(CONFIG_CPU_SUBTYPE_SH7722)

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#define DMTE0_IRQ	48

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#define DMTE4_IRQ	76

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#define DMAE0_IRQ	78	/* DMA Error IRQ*/

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#define SH_DMAC_BASE0	0xFE008020

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#define SH_DMARS_BASE0	0xFE009000

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#elif defined(CONFIG_CPU_SUBTYPE_SH7763) || \

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	defined(CONFIG_CPU_SUBTYPE_SH7764)

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#define DMTE0_IRQ	34

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#define DMTE4_IRQ	44

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#define DMAE0_IRQ	38

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#define SH_DMAC_BASE0	0xFF608020

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#define SH_DMARS_BASE0	0xFF609000

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#elif defined(CONFIG_CPU_SUBTYPE_SH7723)

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#define DMTE0_IRQ	48	/* DMAC0A*/

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#define DMTE4_IRQ	76	/* DMAC0B */

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#define DMTE6_IRQ	40

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#define DMTE8_IRQ	42	/* DMAC1A */

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#define DMTE9_IRQ	43

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#define DMTE10_IRQ	72	/* DMAC1B */

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#define DMTE11_IRQ	73

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#define DMAE0_IRQ	78	/* DMA Error IRQ*/

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#define DMAE1_IRQ	74	/* DMA Error IRQ*/

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#define SH_DMAC_BASE0	0xFE008020

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#define SH_DMAC_BASE1	0xFDC08020

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#define SH_DMARS_BASE0	0xFDC09000

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#elif defined(CONFIG_CPU_SUBTYPE_SH7724)

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#define DMTE0_IRQ	48	/* DMAC0A*/

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#define DMTE4_IRQ	76	/* DMAC0B */

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#define DMTE6_IRQ	40

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#define DMTE8_IRQ	42	/* DMAC1A */

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#define DMTE9_IRQ	43

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#define DMTE10_IRQ	72	/* DMAC1B */

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#define DMTE11_IRQ	73

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#define DMAE0_IRQ	78	/* DMA Error IRQ*/

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#define DMAE1_IRQ	74	/* DMA Error IRQ*/

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#define SH_DMAC_BASE0	0xFE008020

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#define SH_DMAC_BASE1	0xFDC08020

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#define SH_DMARS_BASE0	0xFE009000

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#define SH_DMARS_BASE1	0xFDC09000

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#elif defined(CONFIG_CPU_SUBTYPE_SH7780)

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#define DMTE0_IRQ	34

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#define DMTE4_IRQ	44

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#define DMTE6_IRQ	46

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#define DMTE8_IRQ	92

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#define DMTE9_IRQ	93

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#define DMTE10_IRQ	94

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#define DMTE11_IRQ	95

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#define DMAE0_IRQ	38	/* DMA Error IRQ */

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#define SH_DMAC_BASE0	0xFC808020

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#define SH_DMAC_BASE1	0xFC818020

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#define SH_DMARS_BASE0	0xFC809000

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#else /* SH7785 */

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#define DMTE0_IRQ	33

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#define DMTE4_IRQ	37

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#define DMTE6_IRQ	52

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#define DMTE8_IRQ	54

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#define DMTE9_IRQ	55

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#define DMTE10_IRQ	56

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#define DMTE11_IRQ	57

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#define DMAE0_IRQ	39	/* DMA Error IRQ0 */

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#define DMAE1_IRQ	58	/* DMA Error IRQ1 */

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#define SH_DMAC_BASE0	0xFC808020

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#define SH_DMAC_BASE1	0xFCC08020

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#define SH_DMARS_BASE0	0xFC809000

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#endif

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#define REQ_HE		0x000000C0

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#define REQ_H		0x00000080

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#define REQ_LE		0x00000040

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#define TM_BURST	0x00000020

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#endif /* __ASM_SH_CPU_SH4_DMA_SH7780_H */

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