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awilliam
GitHub Repository: awilliam/linux-vfio
 Path: blob/master/arch/sh/include/cpu-sh5/cpu/irq.h
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#ifndef __ASM_SH_CPU_SH5_IRQ_H

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#define __ASM_SH_CPU_SH5_IRQ_H

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/*

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 * include/asm-sh/cpu-sh5/irq.h

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 *

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 * Copyright (C) 2000, 2001  Paolo Alberelli

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 *

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 * This file is subject to the terms and conditions of the GNU General Public

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 * License.  See the file "COPYING" in the main directory of this archive

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 * for more details.

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 */

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/*

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 * Encoded IRQs are not considered worth to be supported.

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 * Main reason is that there's no per-encoded-interrupt

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 * enable/disable mechanism (as there was in SH3/4).

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 * An all enabled/all disabled is worth only if there's

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 * a cascaded IC to disable/enable/ack on. Until such

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 * IC is available there's no such support.

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 *

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 * Presumably Encoded IRQs may use extra IRQs beyond 64,

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 * below. Some logic must be added to cope with IRQ_IRL?

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 * in an exclusive way.

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 *

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 * Priorities are set at Platform level, when IRQ_IRL0-3

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 * are set to 0 Encoding is allowed. Otherwise it's not

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 * allowed.

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 */

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/* Independent IRQs */

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#define IRQ_IRL0	0

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#define IRQ_IRL1	1

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#define IRQ_IRL2	2

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#define IRQ_IRL3	3

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#define IRQ_INTA	4

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#define IRQ_INTB	5

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#define IRQ_INTC	6

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#define IRQ_INTD	7

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#define IRQ_SERR	12

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#define IRQ_ERR		13

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#define IRQ_PWR3	14

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#define IRQ_PWR2	15

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#define IRQ_PWR1	16

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#define IRQ_PWR0	17

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#define IRQ_DMTE0	18

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#define IRQ_DMTE1	19

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#define IRQ_DMTE2	20

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#define IRQ_DMTE3	21

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#define IRQ_DAERR	22

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#define IRQ_TUNI0	32

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#define IRQ_TUNI1	33

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#define IRQ_TUNI2	34

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#define IRQ_TICPI2	35

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#define IRQ_ATI		36

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#define IRQ_PRI		37

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#define IRQ_CUI		38

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#define IRQ_ERI		39

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#define IRQ_RXI		40

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#define IRQ_BRI		41

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#define IRQ_TXI		42

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#define IRQ_ITI		63

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#define NR_INTC_IRQS	64

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#ifdef CONFIG_SH_CAYMAN

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#define NR_EXT_IRQS     32

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#define START_EXT_IRQS  64

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/* PCI bus 2 uses encoded external interrupts on the Cayman board */

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#define IRQ_P2INTA      (START_EXT_IRQS + (3*8) + 0)

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#define IRQ_P2INTB      (START_EXT_IRQS + (3*8) + 1)

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#define IRQ_P2INTC      (START_EXT_IRQS + (3*8) + 2)

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#define IRQ_P2INTD      (START_EXT_IRQS + (3*8) + 3)

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#define I8042_KBD_IRQ	(START_EXT_IRQS + 2)

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#define I8042_AUX_IRQ	(START_EXT_IRQS + 6)

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#define IRQ_CFCARD	(START_EXT_IRQS + 7)

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#define IRQ_PCMCIA	(0)

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#else

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#define NR_EXT_IRQS	0

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#endif

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/* Default IRQs, fixed */

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#define TIMER_IRQ	IRQ_TUNI0

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#define RTC_IRQ		IRQ_CUI

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/* Default Priorities, Platform may choose differently */

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#define	NO_PRIORITY	0	/* Disabled */

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#define TIMER_PRIORITY	2

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#define RTC_PRIORITY	TIMER_PRIORITY

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#define SCIF_PRIORITY	3

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#define INTD_PRIORITY	3

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#define	IRL3_PRIORITY	4

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#define INTC_PRIORITY	6

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#define	IRL2_PRIORITY	7

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#define INTB_PRIORITY	9

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#define	IRL1_PRIORITY	10

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#define INTA_PRIORITY	12

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#define	IRL0_PRIORITY	13

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#define TOP_PRIORITY	15

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extern int intc_evt_to_irq[(0xE20/0x20)+1];

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extern int platform_int_priority[NR_INTC_IRQS];

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#endif /* __ASM_SH_CPU_SH5_IRQ_H */

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