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awilliam
GitHub Repository: awilliam/linux-vfio
 Path: blob/master/arch/sh/include/cpu-sh5/cpu/registers.h
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#ifndef __ASM_SH_CPU_SH5_REGISTERS_H

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#define __ASM_SH_CPU_SH5_REGISTERS_H

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/*

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 * include/asm-sh/cpu-sh5/registers.h

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 *

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 * Copyright (C) 2000, 2001  Paolo Alberelli

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 * Copyright (C) 2004  Richard Curnow

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 *

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 * This file is subject to the terms and conditions of the GNU General Public

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 * License.  See the file "COPYING" in the main directory of this archive

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 * for more details.

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 */

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#ifdef __ASSEMBLY__

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/* =====================================================================

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**

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** Section 1: acts on assembly sources pre-processed by GPP ( <source.S>).

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**	      Assigns symbolic names to control & target registers.

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*/

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/*

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 * Define some useful aliases for control registers.

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 */

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#define SR	cr0

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#define SSR	cr1

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#define PSSR	cr2

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			/* cr3 UNDEFINED */

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#define INTEVT	cr4

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#define EXPEVT	cr5

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#define PEXPEVT	cr6

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#define TRA	cr7

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#define SPC	cr8

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#define PSPC	cr9

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#define RESVEC	cr10

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#define VBR	cr11

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			/* cr12 UNDEFINED */

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#define TEA	cr13

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			/* cr14-cr15 UNDEFINED */

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#define DCR	cr16

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#define KCR0	cr17

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#define KCR1	cr18

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			/* cr19-cr31 UNDEFINED */

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			/* cr32-cr61 RESERVED */

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#define CTC	cr62

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#define USR	cr63

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/*

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 * ABI dependent registers (general purpose set)

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 */

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#define RET	r2

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#define ARG1	r2

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#define ARG2	r3

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#define ARG3	r4

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#define ARG4	r5

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#define ARG5	r6

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#define ARG6	r7

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#define SP	r15

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#define LINK	r18

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#define ZERO	r63

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/*

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 * Status register defines: used only by assembly sources (and

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 * 			    syntax independednt)

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 */

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#define SR_RESET_VAL	0x0000000050008000

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#define SR_HARMLESS	0x00000000500080f0	/* Write ignores for most */

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#define SR_ENABLE_FPU	0xffffffffffff7fff	/* AND with this */

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#if defined (CONFIG_SH64_SR_WATCH)

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#define SR_ENABLE_MMU	0x0000000084000000	/* OR with this */

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#else

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#define SR_ENABLE_MMU	0x0000000080000000	/* OR with this */

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#endif

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#define SR_UNBLOCK_EXC	0xffffffffefffffff	/* AND with this */

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#define SR_BLOCK_EXC	0x0000000010000000	/* OR with this */

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#else	/* Not __ASSEMBLY__ syntax */

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/*

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** Stringify reg. name

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*/

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#define __str(x)  #x

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/* Stringify control register names for use in inline assembly */

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#define __SR __str(SR)

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#define __SSR __str(SSR)

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#define __PSSR __str(PSSR)

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#define __INTEVT __str(INTEVT)

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#define __EXPEVT __str(EXPEVT)

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#define __PEXPEVT __str(PEXPEVT)

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#define __TRA __str(TRA)

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#define __SPC __str(SPC)

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#define __PSPC __str(PSPC)

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#define __RESVEC __str(RESVEC)

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#define __VBR __str(VBR)

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#define __TEA __str(TEA)

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#define __DCR __str(DCR)

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#define __KCR0 __str(KCR0)

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#define __KCR1 __str(KCR1)

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#define __CTC __str(CTC)

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#define __USR __str(USR)

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#endif /* __ASSEMBLY__ */

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#endif /* __ASM_SH_CPU_SH5_REGISTERS_H */

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