1#ifndef __ASM_SH_CPU_SH5_RTC_H 2#define __ASM_SH_CPU_SH5_RTC_H 3 4#define rtc_reg_size sizeof(u32) 5#define RTC_BIT_INVERTED 0 /* The SH-5 RTC is surprisingly sane! */ 6#define RTC_DEF_CAPABILITIES RTC_CAP_4_DIGIT_YEAR 7 8#endif /* __ASM_SH_CPU_SH5_RTC_H */ 9 10
