Path: blob/master/arch/sh/kernel/cpu/sh3/setup-sh7705.c
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/*1* SH7705 Setup2*3* Copyright (C) 2006 - 2009 Paul Mundt4* Copyright (C) 2007 Nobuhiro Iwamatsu5*6* This file is subject to the terms and conditions of the GNU General Public7* License. See the file "COPYING" in the main directory of this archive8* for more details.9*/10#include <linux/platform_device.h>11#include <linux/init.h>12#include <linux/irq.h>13#include <linux/serial.h>14#include <linux/serial_sci.h>15#include <linux/sh_timer.h>16#include <asm/rtc.h>1718enum {19UNUSED = 0,2021/* interrupt sources */22IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5,23PINT07, PINT815,2425DMAC, SCIF0, SCIF2, ADC_ADI, USB,2627TPU0, TPU1, TPU2, TPU3,28TMU0, TMU1, TMU2,2930RTC, WDT, REF_RCMI,31};3233static struct intc_vect vectors[] __initdata = {34/* IRQ0->5 are handled in setup-sh3.c */35INTC_VECT(PINT07, 0x700), INTC_VECT(PINT815, 0x720),36INTC_VECT(DMAC, 0x800), INTC_VECT(DMAC, 0x820),37INTC_VECT(DMAC, 0x840), INTC_VECT(DMAC, 0x860),38INTC_VECT(SCIF0, 0x880), INTC_VECT(SCIF0, 0x8a0),39INTC_VECT(SCIF0, 0x8e0),40INTC_VECT(SCIF2, 0x900), INTC_VECT(SCIF2, 0x920),41INTC_VECT(SCIF2, 0x960),42INTC_VECT(ADC_ADI, 0x980),43INTC_VECT(USB, 0xa20), INTC_VECT(USB, 0xa40),44INTC_VECT(TPU0, 0xc00), INTC_VECT(TPU1, 0xc20),45INTC_VECT(TPU2, 0xc80), INTC_VECT(TPU3, 0xca0),46INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),47INTC_VECT(TMU2, 0x440), INTC_VECT(TMU2, 0x460),48INTC_VECT(RTC, 0x480), INTC_VECT(RTC, 0x4a0),49INTC_VECT(RTC, 0x4c0),50INTC_VECT(WDT, 0x560),51INTC_VECT(REF_RCMI, 0x580),52};5354static struct intc_prio_reg prio_registers[] __initdata = {55{ 0xfffffee2, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },56{ 0xfffffee4, 0, 16, 4, /* IPRB */ { WDT, REF_RCMI, 0, 0 } },57{ 0xa4000016, 0, 16, 4, /* IPRC */ { IRQ3, IRQ2, IRQ1, IRQ0 } },58{ 0xa4000018, 0, 16, 4, /* IPRD */ { PINT07, PINT815, IRQ5, IRQ4 } },59{ 0xa400001a, 0, 16, 4, /* IPRE */ { DMAC, SCIF0, SCIF2, ADC_ADI } },60{ 0xa4080000, 0, 16, 4, /* IPRF */ { 0, 0, USB } },61{ 0xa4080002, 0, 16, 4, /* IPRG */ { TPU0, TPU1 } },62{ 0xa4080004, 0, 16, 4, /* IPRH */ { TPU2, TPU3 } },6364};6566static DECLARE_INTC_DESC(intc_desc, "sh7705", vectors, NULL,67NULL, prio_registers, NULL);6869static struct plat_sci_port scif0_platform_data = {70.mapbase = 0xa4410000,71.flags = UPF_BOOT_AUTOCONF,72.scscr = SCSCR_TIE | SCSCR_RIE | SCSCR_TE |73SCSCR_RE | SCSCR_CKE1 | SCSCR_CKE0,74.scbrr_algo_id = SCBRR_ALGO_4,75.type = PORT_SCIF,76.irqs = { 56, 56, 56 },77};7879static struct platform_device scif0_device = {80.name = "sh-sci",81.id = 0,82.dev = {83.platform_data = &scif0_platform_data,84},85};8687static struct plat_sci_port scif1_platform_data = {88.mapbase = 0xa4400000,89.flags = UPF_BOOT_AUTOCONF,90.scscr = SCSCR_TIE | SCSCR_RIE | SCSCR_TE | SCSCR_RE,91.scbrr_algo_id = SCBRR_ALGO_4,92.type = PORT_SCIF,93.irqs = { 52, 52, 52 },94};9596static struct platform_device scif1_device = {97.name = "sh-sci",98.id = 1,99.dev = {100.platform_data = &scif1_platform_data,101},102};103104static struct resource rtc_resources[] = {105[0] = {106.start = 0xfffffec0,107.end = 0xfffffec0 + 0x1e,108.flags = IORESOURCE_IO,109},110[1] = {111.start = 20,112.flags = IORESOURCE_IRQ,113},114};115116static struct sh_rtc_platform_info rtc_info = {117.capabilities = RTC_CAP_4_DIGIT_YEAR,118};119120static struct platform_device rtc_device = {121.name = "sh-rtc",122.id = -1,123.num_resources = ARRAY_SIZE(rtc_resources),124.resource = rtc_resources,125.dev = {126.platform_data = &rtc_info,127},128};129130static struct sh_timer_config tmu0_platform_data = {131.channel_offset = 0x02,132.timer_bit = 0,133.clockevent_rating = 200,134};135136static struct resource tmu0_resources[] = {137[0] = {138.start = 0xfffffe94,139.end = 0xfffffe9f,140.flags = IORESOURCE_MEM,141},142[1] = {143.start = 16,144.flags = IORESOURCE_IRQ,145},146};147148static struct platform_device tmu0_device = {149.name = "sh_tmu",150.id = 0,151.dev = {152.platform_data = &tmu0_platform_data,153},154.resource = tmu0_resources,155.num_resources = ARRAY_SIZE(tmu0_resources),156};157158static struct sh_timer_config tmu1_platform_data = {159.channel_offset = 0xe,160.timer_bit = 1,161.clocksource_rating = 200,162};163164static struct resource tmu1_resources[] = {165[0] = {166.start = 0xfffffea0,167.end = 0xfffffeab,168.flags = IORESOURCE_MEM,169},170[1] = {171.start = 17,172.flags = IORESOURCE_IRQ,173},174};175176static struct platform_device tmu1_device = {177.name = "sh_tmu",178.id = 1,179.dev = {180.platform_data = &tmu1_platform_data,181},182.resource = tmu1_resources,183.num_resources = ARRAY_SIZE(tmu1_resources),184};185186static struct sh_timer_config tmu2_platform_data = {187.channel_offset = 0x1a,188.timer_bit = 2,189};190191static struct resource tmu2_resources[] = {192[0] = {193.start = 0xfffffeac,194.end = 0xfffffebb,195.flags = IORESOURCE_MEM,196},197[1] = {198.start = 18,199.flags = IORESOURCE_IRQ,200},201};202203static struct platform_device tmu2_device = {204.name = "sh_tmu",205.id = 2,206.dev = {207.platform_data = &tmu2_platform_data,208},209.resource = tmu2_resources,210.num_resources = ARRAY_SIZE(tmu2_resources),211};212213static struct platform_device *sh7705_devices[] __initdata = {214&scif0_device,215&scif1_device,216&tmu0_device,217&tmu1_device,218&tmu2_device,219&rtc_device,220};221222static int __init sh7705_devices_setup(void)223{224return platform_add_devices(sh7705_devices,225ARRAY_SIZE(sh7705_devices));226}227arch_initcall(sh7705_devices_setup);228229static struct platform_device *sh7705_early_devices[] __initdata = {230&scif0_device,231&scif1_device,232&tmu0_device,233&tmu1_device,234&tmu2_device,235};236237void __init plat_early_device_setup(void)238{239early_platform_add_devices(sh7705_early_devices,240ARRAY_SIZE(sh7705_early_devices));241}242243void __init plat_irq_setup(void)244{245register_intc_controller(&intc_desc);246plat_irq_setup_sh3();247}248249250