CoCalc -- pinmux-sh7786.c

GitHub Repository: awilliam/linux-vfio
Path: blob/master/arch/sh/kernel/cpu/sh4a/pinmux-sh7786.c
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1
/*
2
 * SH7786 Pinmux
3
 *
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 * Copyright (C) 2008, 2009  Renesas Solutions Corp.
5
 * Kuninori Morimoto <[email protected]>
6
 *
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 *  Based on SH7785 pinmux
8
 *
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 *  Copyright (C) 2008  Magnus Damm
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 *
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 * This file is subject to the terms and conditions of the GNU General Public
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 * License.  See the file "COPYING" in the main directory of this archive
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 * for more details.
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 */
15

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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/gpio.h>
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#include <cpu/sh7786.h>
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enum {
22
	PINMUX_RESERVED = 0,
23

24
	PINMUX_DATA_BEGIN,
25
	PA7_DATA, PA6_DATA, PA5_DATA, PA4_DATA,
26
	PA3_DATA, PA2_DATA, PA1_DATA, PA0_DATA,
27
	PB7_DATA, PB6_DATA, PB5_DATA, PB4_DATA,
28
	PB3_DATA, PB2_DATA, PB1_DATA, PB0_DATA,
29
	PC7_DATA, PC6_DATA, PC5_DATA, PC4_DATA,
30
	PC3_DATA, PC2_DATA, PC1_DATA, PC0_DATA,
31
	PD7_DATA, PD6_DATA, PD5_DATA, PD4_DATA,
32
	PD3_DATA, PD2_DATA, PD1_DATA, PD0_DATA,
33
	PE7_DATA, PE6_DATA,
34
	PF7_DATA, PF6_DATA, PF5_DATA, PF4_DATA,
35
	PF3_DATA, PF2_DATA, PF1_DATA, PF0_DATA,
36
	PG7_DATA, PG6_DATA, PG5_DATA,
37
	PH7_DATA, PH6_DATA, PH5_DATA, PH4_DATA,
38
	PH3_DATA, PH2_DATA, PH1_DATA, PH0_DATA,
39
	PJ7_DATA, PJ6_DATA, PJ5_DATA, PJ4_DATA,
40
	PJ3_DATA, PJ2_DATA, PJ1_DATA,
41
	PINMUX_DATA_END,
42

43
	PINMUX_INPUT_BEGIN,
44
	PA7_IN, PA6_IN, PA5_IN, PA4_IN,
45
	PA3_IN, PA2_IN, PA1_IN, PA0_IN,
46
	PB7_IN, PB6_IN, PB5_IN, PB4_IN,
47
	PB3_IN, PB2_IN, PB1_IN, PB0_IN,
48
	PC7_IN, PC6_IN, PC5_IN, PC4_IN,
49
	PC3_IN, PC2_IN, PC1_IN, PC0_IN,
50
	PD7_IN, PD6_IN, PD5_IN, PD4_IN,
51
	PD3_IN, PD2_IN, PD1_IN, PD0_IN,
52
	PE7_IN, PE6_IN,
53
	PF7_IN, PF6_IN, PF5_IN, PF4_IN,
54
	PF3_IN, PF2_IN, PF1_IN, PF0_IN,
55
	PG7_IN, PG6_IN, PG5_IN,
56
	PH7_IN, PH6_IN, PH5_IN, PH4_IN,
57
	PH3_IN, PH2_IN, PH1_IN, PH0_IN,
58
	PJ7_IN, PJ6_IN, PJ5_IN, PJ4_IN,
59
	PJ3_IN, PJ2_IN, PJ1_IN,
60
	PINMUX_INPUT_END,
61

62
	PINMUX_INPUT_PULLUP_BEGIN,
63
	PA7_IN_PU, PA6_IN_PU, PA5_IN_PU, PA4_IN_PU,
64
	PA3_IN_PU, PA2_IN_PU, PA1_IN_PU, PA0_IN_PU,
65
	PB7_IN_PU, PB6_IN_PU, PB5_IN_PU, PB4_IN_PU,
66
	PB3_IN_PU, PB2_IN_PU, PB1_IN_PU, PB0_IN_PU,
67
	PC7_IN_PU, PC6_IN_PU, PC5_IN_PU, PC4_IN_PU,
68
	PC3_IN_PU, PC2_IN_PU, PC1_IN_PU, PC0_IN_PU,
69
	PD7_IN_PU, PD6_IN_PU, PD5_IN_PU, PD4_IN_PU,
70
	PD3_IN_PU, PD2_IN_PU, PD1_IN_PU, PD0_IN_PU,
71
	PE7_IN_PU, PE6_IN_PU,
72
	PF7_IN_PU, PF6_IN_PU, PF5_IN_PU, PF4_IN_PU,
73
	PF3_IN_PU, PF2_IN_PU, PF1_IN_PU, PF0_IN_PU,
74
	PG7_IN_PU, PG6_IN_PU, PG5_IN_PU,
75
	PH7_IN_PU, PH6_IN_PU, PH5_IN_PU, PH4_IN_PU,
76
	PH3_IN_PU, PH2_IN_PU, PH1_IN_PU, PH0_IN_PU,
77
	PJ7_IN_PU, PJ6_IN_PU, PJ5_IN_PU, PJ4_IN_PU,
78
	PJ3_IN_PU, PJ2_IN_PU, PJ1_IN_PU,
79
	PINMUX_INPUT_PULLUP_END,
80

81
	PINMUX_OUTPUT_BEGIN,
82
	PA7_OUT, PA6_OUT, PA5_OUT, PA4_OUT,
83
	PA3_OUT, PA2_OUT, PA1_OUT, PA0_OUT,
84
	PB7_OUT, PB6_OUT, PB5_OUT, PB4_OUT,
85
	PB3_OUT, PB2_OUT, PB1_OUT, PB0_OUT,
86
	PC7_OUT, PC6_OUT, PC5_OUT, PC4_OUT,
87
	PC3_OUT, PC2_OUT, PC1_OUT, PC0_OUT,
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	PD7_OUT, PD6_OUT, PD5_OUT, PD4_OUT,
89
	PD3_OUT, PD2_OUT, PD1_OUT, PD0_OUT,
90
	PE7_OUT, PE6_OUT,
91
	PF7_OUT, PF6_OUT, PF5_OUT, PF4_OUT,
92
	PF3_OUT, PF2_OUT, PF1_OUT, PF0_OUT,
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	PG7_OUT, PG6_OUT, PG5_OUT,
94
	PH7_OUT, PH6_OUT, PH5_OUT, PH4_OUT,
95
	PH3_OUT, PH2_OUT, PH1_OUT, PH0_OUT,
96
	PJ7_OUT, PJ6_OUT, PJ5_OUT, PJ4_OUT,
97
	PJ3_OUT, PJ2_OUT, PJ1_OUT,
98
	PINMUX_OUTPUT_END,
99

100
	PINMUX_FUNCTION_BEGIN,
101
	PA7_FN, PA6_FN, PA5_FN, PA4_FN,
102
	PA3_FN, PA2_FN, PA1_FN, PA0_FN,
103
	PB7_FN, PB6_FN, PB5_FN, PB4_FN,
104
	PB3_FN, PB2_FN, PB1_FN, PB0_FN,
105
	PC7_FN, PC6_FN, PC5_FN, PC4_FN,
106
	PC3_FN, PC2_FN, PC1_FN, PC0_FN,
107
	PD7_FN, PD6_FN, PD5_FN, PD4_FN,
108
	PD3_FN, PD2_FN, PD1_FN, PD0_FN,
109
	PE7_FN, PE6_FN,
110
	PF7_FN, PF6_FN, PF5_FN, PF4_FN,
111
	PF3_FN, PF2_FN, PF1_FN, PF0_FN,
112
	PG7_FN, PG6_FN, PG5_FN,
113
	PH7_FN, PH6_FN, PH5_FN, PH4_FN,
114
	PH3_FN, PH2_FN, PH1_FN, PH0_FN,
115
	PJ7_FN, PJ6_FN, PJ5_FN, PJ4_FN,
116
	PJ3_FN, PJ2_FN, PJ1_FN,
117
	P1MSEL14_0, P1MSEL14_1,
118
	P1MSEL13_0, P1MSEL13_1,
119
	P1MSEL12_0, P1MSEL12_1,
120
	P1MSEL11_0, P1MSEL11_1,
121
	P1MSEL10_0, P1MSEL10_1,
122
	P1MSEL9_0, P1MSEL9_1,
123
	P1MSEL8_0, P1MSEL8_1,
124
	P1MSEL7_0, P1MSEL7_1,
125
	P1MSEL6_0, P1MSEL6_1,
126
	P1MSEL5_0, P1MSEL5_1,
127
	P1MSEL4_0, P1MSEL4_1,
128
	P1MSEL3_0, P1MSEL3_1,
129
	P1MSEL2_0, P1MSEL2_1,
130
	P1MSEL1_0, P1MSEL1_1,
131
	P1MSEL0_0, P1MSEL0_1,
132

133
	P2MSEL15_0, P2MSEL15_1,
134
	P2MSEL14_0, P2MSEL14_1,
135
	P2MSEL13_0, P2MSEL13_1,
136
	P2MSEL12_0, P2MSEL12_1,
137
	P2MSEL11_0, P2MSEL11_1,
138
	P2MSEL10_0, P2MSEL10_1,
139
	P2MSEL9_0, P2MSEL9_1,
140
	P2MSEL8_0, P2MSEL8_1,
141
	P2MSEL7_0, P2MSEL7_1,
142
	P2MSEL6_0, P2MSEL6_1,
143
	P2MSEL5_0, P2MSEL5_1,
144
	P2MSEL4_0, P2MSEL4_1,
145
	P2MSEL3_0, P2MSEL3_1,
146
	P2MSEL2_0, P2MSEL2_1,
147
	P2MSEL1_0, P2MSEL1_1,
148
	P2MSEL0_0, P2MSEL0_1,
149
	PINMUX_FUNCTION_END,
150

151
	PINMUX_MARK_BEGIN,
152
	DCLKIN_MARK, DCLKOUT_MARK, ODDF_MARK,
153
	VSYNC_MARK, HSYNC_MARK, CDE_MARK, DISP_MARK,
154
	DR0_MARK, DR1_MARK, DR2_MARK, DR3_MARK, DR4_MARK, DR5_MARK,
155
	DG0_MARK, DG1_MARK, DG2_MARK, DG3_MARK, DG4_MARK, DG5_MARK,
156
	DB0_MARK, DB1_MARK, DB2_MARK, DB3_MARK, DB4_MARK, DB5_MARK,
157
	ETH_MAGIC_MARK, ETH_LINK_MARK, ETH_TX_ER_MARK, ETH_TX_EN_MARK,
158
	ETH_MDIO_MARK, ETH_RX_CLK_MARK, ETH_MDC_MARK, ETH_COL_MARK,
159
	ETH_TX_CLK_MARK, ETH_CRS_MARK, ETH_RX_DV_MARK, ETH_RX_ER_MARK,
160
	ETH_TXD3_MARK, ETH_TXD2_MARK, ETH_TXD1_MARK, ETH_TXD0_MARK,
161
	ETH_RXD3_MARK, ETH_RXD2_MARK, ETH_RXD1_MARK, ETH_RXD0_MARK,
162
	HSPI_CLK_MARK, HSPI_CS_MARK, HSPI_RX_MARK, HSPI_TX_MARK,
163
	SCIF0_CTS_MARK, SCIF0_RTS_MARK,
164
	SCIF0_SCK_MARK, SCIF0_RXD_MARK, SCIF0_TXD_MARK,
165
	SCIF1_SCK_MARK, SCIF1_RXD_MARK, SCIF1_TXD_MARK,
166
	SCIF3_SCK_MARK, SCIF3_RXD_MARK, SCIF3_TXD_MARK,
167
	SCIF4_SCK_MARK, SCIF4_RXD_MARK, SCIF4_TXD_MARK,
168
	SCIF5_SCK_MARK, SCIF5_RXD_MARK, SCIF5_TXD_MARK,
169
	BREQ_MARK, IOIS16_MARK, CE2B_MARK, CE2A_MARK, BACK_MARK,
170
	FALE_MARK, FRB_MARK, FSTATUS_MARK,
171
	FSE_MARK, FCLE_MARK,
172
	DACK0_MARK, DACK1_MARK, DACK2_MARK, DACK3_MARK,
173
	DREQ0_MARK, DREQ1_MARK, DREQ2_MARK, DREQ3_MARK,
174
	DRAK0_MARK, DRAK1_MARK, DRAK2_MARK, DRAK3_MARK,
175
	USB_OVC1_MARK, USB_OVC0_MARK,
176
	USB_PENC1_MARK, USB_PENC0_MARK,
177
	HAC_RES_MARK,
178
	HAC1_SDOUT_MARK, HAC1_SDIN_MARK, HAC1_SYNC_MARK, HAC1_BITCLK_MARK,
179
	HAC0_SDOUT_MARK, HAC0_SDIN_MARK, HAC0_SYNC_MARK, HAC0_BITCLK_MARK,
180
	SSI0_SDATA_MARK, SSI0_SCK_MARK, SSI0_WS_MARK, SSI0_CLK_MARK,
181
	SSI1_SDATA_MARK, SSI1_SCK_MARK, SSI1_WS_MARK, SSI1_CLK_MARK,
182
	SSI2_SDATA_MARK, SSI2_SCK_MARK, SSI2_WS_MARK,
183
	SSI3_SDATA_MARK, SSI3_SCK_MARK, SSI3_WS_MARK,
184
	SDIF1CMD_MARK, SDIF1CD_MARK, SDIF1WP_MARK, SDIF1CLK_MARK,
185
	SDIF1D3_MARK, SDIF1D2_MARK, SDIF1D1_MARK, SDIF1D0_MARK,
186
	SDIF0CMD_MARK, SDIF0CD_MARK, SDIF0WP_MARK, SDIF0CLK_MARK,
187
	SDIF0D3_MARK, SDIF0D2_MARK, SDIF0D1_MARK, SDIF0D0_MARK,
188
	TCLK_MARK,
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	IRL7_MARK, IRL6_MARK, IRL5_MARK, IRL4_MARK,
190
	PINMUX_MARK_END,
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};
192

193
static pinmux_enum_t pinmux_data[] = {
194

195
	/* PA GPIO */
196
	PINMUX_DATA(PA7_DATA, PA7_IN, PA7_OUT, PA7_IN_PU),
197
	PINMUX_DATA(PA6_DATA, PA6_IN, PA6_OUT, PA6_IN_PU),
198
	PINMUX_DATA(PA5_DATA, PA5_IN, PA5_OUT, PA5_IN_PU),
199
	PINMUX_DATA(PA4_DATA, PA4_IN, PA4_OUT, PA4_IN_PU),
200
	PINMUX_DATA(PA3_DATA, PA3_IN, PA3_OUT, PA3_IN_PU),
201
	PINMUX_DATA(PA2_DATA, PA2_IN, PA2_OUT, PA2_IN_PU),
202
	PINMUX_DATA(PA1_DATA, PA1_IN, PA1_OUT, PA1_IN_PU),
203
	PINMUX_DATA(PA0_DATA, PA0_IN, PA0_OUT, PA0_IN_PU),
204

205
	/* PB GPIO */
206
	PINMUX_DATA(PB7_DATA, PB7_IN, PB7_OUT, PB7_IN_PU),
207
	PINMUX_DATA(PB6_DATA, PB6_IN, PB6_OUT, PB6_IN_PU),
208
	PINMUX_DATA(PB5_DATA, PB5_IN, PB5_OUT, PB5_IN_PU),
209
	PINMUX_DATA(PB4_DATA, PB4_IN, PB4_OUT, PB4_IN_PU),
210
	PINMUX_DATA(PB3_DATA, PB3_IN, PB3_OUT, PB3_IN_PU),
211
	PINMUX_DATA(PB2_DATA, PB2_IN, PB2_OUT, PB2_IN_PU),
212
	PINMUX_DATA(PB1_DATA, PB1_IN, PB1_OUT, PB1_IN_PU),
213
	PINMUX_DATA(PB0_DATA, PB0_IN, PB0_OUT, PB0_IN_PU),
214

215
	/* PC GPIO */
216
	PINMUX_DATA(PC7_DATA, PC7_IN, PC7_OUT, PC7_IN_PU),
217
	PINMUX_DATA(PC6_DATA, PC6_IN, PC6_OUT, PC6_IN_PU),
218
	PINMUX_DATA(PC5_DATA, PC5_IN, PC5_OUT, PC5_IN_PU),
219
	PINMUX_DATA(PC4_DATA, PC4_IN, PC4_OUT, PC4_IN_PU),
220
	PINMUX_DATA(PC3_DATA, PC3_IN, PC3_OUT, PC3_IN_PU),
221
	PINMUX_DATA(PC2_DATA, PC2_IN, PC2_OUT, PC2_IN_PU),
222
	PINMUX_DATA(PC1_DATA, PC1_IN, PC1_OUT, PC1_IN_PU),
223
	PINMUX_DATA(PC0_DATA, PC0_IN, PC0_OUT, PC0_IN_PU),
224

225
	/* PD GPIO */
226
	PINMUX_DATA(PD7_DATA, PD7_IN, PD7_OUT, PD7_IN_PU),
227
	PINMUX_DATA(PD6_DATA, PD6_IN, PD6_OUT, PD6_IN_PU),
228
	PINMUX_DATA(PD5_DATA, PD5_IN, PD5_OUT, PD5_IN_PU),
229
	PINMUX_DATA(PD4_DATA, PD4_IN, PD4_OUT, PD4_IN_PU),
230
	PINMUX_DATA(PD3_DATA, PD3_IN, PD3_OUT, PD3_IN_PU),
231
	PINMUX_DATA(PD2_DATA, PD2_IN, PD2_OUT, PD2_IN_PU),
232
	PINMUX_DATA(PD1_DATA, PD1_IN, PD1_OUT, PD1_IN_PU),
233
	PINMUX_DATA(PD0_DATA, PD0_IN, PD0_OUT, PD0_IN_PU),
234

235
	/* PE GPIO */
236
	PINMUX_DATA(PE7_DATA, PE7_IN, PE7_OUT, PE7_IN_PU),
237
	PINMUX_DATA(PE6_DATA, PE6_IN, PE6_OUT, PE6_IN_PU),
238

239
	/* PF GPIO */
240
	PINMUX_DATA(PF7_DATA, PF7_IN, PF7_OUT, PF7_IN_PU),
241
	PINMUX_DATA(PF6_DATA, PF6_IN, PF6_OUT, PF6_IN_PU),
242
	PINMUX_DATA(PF5_DATA, PF5_IN, PF5_OUT, PF5_IN_PU),
243
	PINMUX_DATA(PF4_DATA, PF4_IN, PF4_OUT, PF4_IN_PU),
244
	PINMUX_DATA(PF3_DATA, PF3_IN, PF3_OUT, PF3_IN_PU),
245
	PINMUX_DATA(PF2_DATA, PF2_IN, PF2_OUT, PF2_IN_PU),
246
	PINMUX_DATA(PF1_DATA, PF1_IN, PF1_OUT, PF1_IN_PU),
247
	PINMUX_DATA(PF0_DATA, PF0_IN, PF0_OUT, PF0_IN_PU),
248

249
	/* PG GPIO */
250
	PINMUX_DATA(PG7_DATA, PG7_IN, PG7_OUT, PG7_IN_PU),
251
	PINMUX_DATA(PG6_DATA, PG6_IN, PG6_OUT, PG6_IN_PU),
252
	PINMUX_DATA(PG5_DATA, PG5_IN, PG5_OUT, PG5_IN_PU),
253

254
	/* PH GPIO */
255
	PINMUX_DATA(PH7_DATA, PH7_IN, PH7_OUT, PH7_IN_PU),
256
	PINMUX_DATA(PH6_DATA, PH6_IN, PH6_OUT, PH6_IN_PU),
257
	PINMUX_DATA(PH5_DATA, PH5_IN, PH5_OUT, PH5_IN_PU),
258
	PINMUX_DATA(PH4_DATA, PH4_IN, PH4_OUT, PH4_IN_PU),
259
	PINMUX_DATA(PH3_DATA, PH3_IN, PH3_OUT, PH3_IN_PU),
260
	PINMUX_DATA(PH2_DATA, PH2_IN, PH2_OUT, PH2_IN_PU),
261
	PINMUX_DATA(PH1_DATA, PH1_IN, PH1_OUT, PH1_IN_PU),
262
	PINMUX_DATA(PH0_DATA, PH0_IN, PH0_OUT, PH0_IN_PU),
263

264
	/* PJ GPIO */
265
	PINMUX_DATA(PJ7_DATA, PJ7_IN, PJ7_OUT, PJ7_IN_PU),
266
	PINMUX_DATA(PJ6_DATA, PJ6_IN, PJ6_OUT, PJ6_IN_PU),
267
	PINMUX_DATA(PJ5_DATA, PJ5_IN, PJ5_OUT, PJ5_IN_PU),
268
	PINMUX_DATA(PJ4_DATA, PJ4_IN, PJ4_OUT, PJ4_IN_PU),
269
	PINMUX_DATA(PJ3_DATA, PJ3_IN, PJ3_OUT, PJ3_IN_PU),
270
	PINMUX_DATA(PJ2_DATA, PJ2_IN, PJ2_OUT, PJ2_IN_PU),
271
	PINMUX_DATA(PJ1_DATA, PJ1_IN, PJ1_OUT, PJ1_IN_PU),
272

273
	/* PA FN */
274
	PINMUX_DATA(CDE_MARK,		P1MSEL2_0, PA7_FN),
275
	PINMUX_DATA(DISP_MARK,		P1MSEL2_0, PA6_FN),
276
	PINMUX_DATA(DR5_MARK,		P1MSEL2_0, PA5_FN),
277
	PINMUX_DATA(DR4_MARK,		P1MSEL2_0, PA4_FN),
278
	PINMUX_DATA(DR3_MARK,		P1MSEL2_0, PA3_FN),
279
	PINMUX_DATA(DR2_MARK,		P1MSEL2_0, PA2_FN),
280
	PINMUX_DATA(DR1_MARK,		P1MSEL2_0, PA1_FN),
281
	PINMUX_DATA(DR0_MARK,		P1MSEL2_0, PA0_FN),
282
	PINMUX_DATA(ETH_MAGIC_MARK,	P1MSEL2_1, PA7_FN),
283
	PINMUX_DATA(ETH_LINK_MARK,	P1MSEL2_1, PA6_FN),
284
	PINMUX_DATA(ETH_TX_ER_MARK,	P1MSEL2_1, PA5_FN),
285
	PINMUX_DATA(ETH_TX_EN_MARK,	P1MSEL2_1, PA4_FN),
286
	PINMUX_DATA(ETH_TXD3_MARK,	P1MSEL2_1, PA3_FN),
287
	PINMUX_DATA(ETH_TXD2_MARK,	P1MSEL2_1, PA2_FN),
288
	PINMUX_DATA(ETH_TXD1_MARK,	P1MSEL2_1, PA1_FN),
289
	PINMUX_DATA(ETH_TXD0_MARK,	P1MSEL2_1, PA0_FN),
290

291
	/* PB FN */
292
	PINMUX_DATA(VSYNC_MARK,		P1MSEL3_0, PB7_FN),
293
	PINMUX_DATA(ODDF_MARK,		P1MSEL3_0, PB6_FN),
294
	PINMUX_DATA(DG5_MARK,		P1MSEL2_0, PB5_FN),
295
	PINMUX_DATA(DG4_MARK,		P1MSEL2_0, PB4_FN),
296
	PINMUX_DATA(DG3_MARK,		P1MSEL2_0, PB3_FN),
297
	PINMUX_DATA(DG2_MARK,		P1MSEL2_0, PB2_FN),
298
	PINMUX_DATA(DG1_MARK,		P1MSEL2_0, PB1_FN),
299
	PINMUX_DATA(DG0_MARK,		P1MSEL2_0, PB0_FN),
300
	PINMUX_DATA(HSPI_CLK_MARK,	P1MSEL3_1, PB7_FN),
301
	PINMUX_DATA(HSPI_CS_MARK,	P1MSEL3_1, PB6_FN),
302
	PINMUX_DATA(ETH_MDIO_MARK,	P1MSEL2_1, PB5_FN),
303
	PINMUX_DATA(ETH_RX_CLK_MARK,	P1MSEL2_1, PB4_FN),
304
	PINMUX_DATA(ETH_MDC_MARK,	P1MSEL2_1, PB3_FN),
305
	PINMUX_DATA(ETH_COL_MARK,	P1MSEL2_1, PB2_FN),
306
	PINMUX_DATA(ETH_TX_CLK_MARK,	P1MSEL2_1, PB1_FN),
307
	PINMUX_DATA(ETH_CRS_MARK,	P1MSEL2_1, PB0_FN),
308

309
	/* PC FN */
310
	PINMUX_DATA(DCLKIN_MARK,	P1MSEL3_0, PC7_FN),
311
	PINMUX_DATA(HSYNC_MARK,		P1MSEL3_0, PC6_FN),
312
	PINMUX_DATA(DB5_MARK,		P1MSEL2_0, PC5_FN),
313
	PINMUX_DATA(DB4_MARK,		P1MSEL2_0, PC4_FN),
314
	PINMUX_DATA(DB3_MARK,		P1MSEL2_0, PC3_FN),
315
	PINMUX_DATA(DB2_MARK,		P1MSEL2_0, PC2_FN),
316
	PINMUX_DATA(DB1_MARK,		P1MSEL2_0, PC1_FN),
317
	PINMUX_DATA(DB0_MARK,		P1MSEL2_0, PC0_FN),
318

319
	PINMUX_DATA(HSPI_RX_MARK,	P1MSEL3_1, PC7_FN),
320
	PINMUX_DATA(HSPI_TX_MARK,	P1MSEL3_1, PC6_FN),
321
	PINMUX_DATA(ETH_RXD3_MARK,	P1MSEL2_1, PC5_FN),
322
	PINMUX_DATA(ETH_RXD2_MARK,	P1MSEL2_1, PC4_FN),
323
	PINMUX_DATA(ETH_RXD1_MARK,	P1MSEL2_1, PC3_FN),
324
	PINMUX_DATA(ETH_RXD0_MARK,	P1MSEL2_1, PC2_FN),
325
	PINMUX_DATA(ETH_RX_DV_MARK,	P1MSEL2_1, PC1_FN),
326
	PINMUX_DATA(ETH_RX_ER_MARK,	P1MSEL2_1, PC0_FN),
327

328
	/* PD FN */
329
	PINMUX_DATA(DCLKOUT_MARK,	PD7_FN),
330
	PINMUX_DATA(SCIF1_SCK_MARK,	PD6_FN),
331
	PINMUX_DATA(SCIF1_RXD_MARK,	PD5_FN),
332
	PINMUX_DATA(SCIF1_TXD_MARK,	PD4_FN),
333
	PINMUX_DATA(DACK1_MARK,		P1MSEL13_1, P1MSEL12_0, PD3_FN),
334
	PINMUX_DATA(BACK_MARK,		P1MSEL13_0, P1MSEL12_1, PD3_FN),
335
	PINMUX_DATA(FALE_MARK,		P1MSEL13_0, P1MSEL12_0, PD3_FN),
336
	PINMUX_DATA(DACK0_MARK,		P1MSEL14_1, PD2_FN),
337
	PINMUX_DATA(FCLE_MARK,		P1MSEL14_0, PD2_FN),
338
	PINMUX_DATA(DREQ1_MARK,		P1MSEL10_0, P1MSEL9_1, PD1_FN),
339
	PINMUX_DATA(BREQ_MARK,		P1MSEL10_1, P1MSEL9_0, PD1_FN),
340
	PINMUX_DATA(USB_OVC1_MARK,	P1MSEL10_0, P1MSEL9_0, PD1_FN),
341
	PINMUX_DATA(DREQ0_MARK,		P1MSEL11_1, PD0_FN),
342
	PINMUX_DATA(USB_OVC0_MARK,	P1MSEL11_0, PD0_FN),
343

344
	/* PE FN */
345
	PINMUX_DATA(USB_PENC1_MARK,	PE7_FN),
346
	PINMUX_DATA(USB_PENC0_MARK,	PE6_FN),
347

348
	/* PF FN */
349
	PINMUX_DATA(HAC1_SDOUT_MARK,	P2MSEL15_0, P2MSEL14_0, PF7_FN),
350
	PINMUX_DATA(HAC1_SDIN_MARK,	P2MSEL15_0, P2MSEL14_0, PF6_FN),
351
	PINMUX_DATA(HAC1_SYNC_MARK,	P2MSEL15_0, P2MSEL14_0, PF5_FN),
352
	PINMUX_DATA(HAC1_BITCLK_MARK,	P2MSEL15_0, P2MSEL14_0, PF4_FN),
353
	PINMUX_DATA(HAC0_SDOUT_MARK,	P2MSEL13_0, P2MSEL12_0, PF3_FN),
354
	PINMUX_DATA(HAC0_SDIN_MARK,	P2MSEL13_0, P2MSEL12_0, PF2_FN),
355
	PINMUX_DATA(HAC0_SYNC_MARK,	P2MSEL13_0, P2MSEL12_0, PF1_FN),
356
	PINMUX_DATA(HAC0_BITCLK_MARK,	P2MSEL13_0, P2MSEL12_0, PF0_FN),
357
	PINMUX_DATA(SSI1_SDATA_MARK,	P2MSEL15_0, P2MSEL14_1, PF7_FN),
358
	PINMUX_DATA(SSI1_SCK_MARK,	P2MSEL15_0, P2MSEL14_1, PF6_FN),
359
	PINMUX_DATA(SSI1_WS_MARK,	P2MSEL15_0, P2MSEL14_1, PF5_FN),
360
	PINMUX_DATA(SSI1_CLK_MARK,	P2MSEL15_0, P2MSEL14_1, PF4_FN),
361
	PINMUX_DATA(SSI0_SDATA_MARK,	P2MSEL13_0, P2MSEL12_1, PF3_FN),
362
	PINMUX_DATA(SSI0_SCK_MARK,	P2MSEL13_0, P2MSEL12_1, PF2_FN),
363
	PINMUX_DATA(SSI0_WS_MARK,	P2MSEL13_0, P2MSEL12_1, PF1_FN),
364
	PINMUX_DATA(SSI0_CLK_MARK,	P2MSEL13_0, P2MSEL12_1, PF0_FN),
365
	PINMUX_DATA(SDIF1CMD_MARK,	P2MSEL15_1, P2MSEL14_0, PF7_FN),
366
	PINMUX_DATA(SDIF1CD_MARK,	P2MSEL15_1, P2MSEL14_0, PF6_FN),
367
	PINMUX_DATA(SDIF1WP_MARK,	P2MSEL15_1, P2MSEL14_0, PF5_FN),
368
	PINMUX_DATA(SDIF1CLK_MARK,	P2MSEL15_1, P2MSEL14_0, PF4_FN),
369
	PINMUX_DATA(SDIF1D3_MARK,	P2MSEL13_1, P2MSEL12_0, PF3_FN),
370
	PINMUX_DATA(SDIF1D2_MARK,	P2MSEL13_1, P2MSEL12_0, PF2_FN),
371
	PINMUX_DATA(SDIF1D1_MARK,	P2MSEL13_1, P2MSEL12_0, PF1_FN),
372
	PINMUX_DATA(SDIF1D0_MARK,	P2MSEL13_1, P2MSEL12_0, PF0_FN),
373

374
	/* PG FN */
375
	PINMUX_DATA(SCIF3_SCK_MARK,	P1MSEL8_0, PG7_FN),
376
	PINMUX_DATA(SSI2_SDATA_MARK,	P1MSEL8_1, PG7_FN),
377
	PINMUX_DATA(SCIF3_RXD_MARK,	P1MSEL7_0, P1MSEL6_0, PG6_FN),
378
	PINMUX_DATA(SSI2_SCK_MARK,	P1MSEL7_1, P1MSEL6_0, PG6_FN),
379
	PINMUX_DATA(TCLK_MARK,		P1MSEL7_0, P1MSEL6_1, PG6_FN),
380
	PINMUX_DATA(SCIF3_TXD_MARK,	P1MSEL5_0, P1MSEL4_0, PG5_FN),
381
	PINMUX_DATA(SSI2_WS_MARK,	P1MSEL5_1, P1MSEL4_0, PG5_FN),
382
	PINMUX_DATA(HAC_RES_MARK,	P1MSEL5_0, P1MSEL4_1, PG5_FN),
383

384
	/* PH FN */
385
	PINMUX_DATA(DACK3_MARK,		P2MSEL4_0, PH7_FN),
386
	PINMUX_DATA(SDIF0CMD_MARK,	P2MSEL4_1, PH7_FN),
387
	PINMUX_DATA(DACK2_MARK,		P2MSEL4_0, PH6_FN),
388
	PINMUX_DATA(SDIF0CD_MARK,	P2MSEL4_1, PH6_FN),
389
	PINMUX_DATA(DREQ3_MARK,		P2MSEL4_0, PH5_FN),
390
	PINMUX_DATA(SDIF0WP_MARK,	P2MSEL4_1, PH5_FN),
391
	PINMUX_DATA(DREQ2_MARK,		P2MSEL3_0, P2MSEL2_1, PH4_FN),
392
	PINMUX_DATA(SDIF0CLK_MARK,	P2MSEL3_1, P2MSEL2_0, PH4_FN),
393
	PINMUX_DATA(SCIF0_CTS_MARK,	P2MSEL3_0, P2MSEL2_0, PH4_FN),
394
	PINMUX_DATA(SDIF0D3_MARK,	P2MSEL1_1, P2MSEL0_0, PH3_FN),
395
	PINMUX_DATA(SCIF0_RTS_MARK,	P2MSEL1_0, P2MSEL0_0, PH3_FN),
396
	PINMUX_DATA(IRL7_MARK,		P2MSEL1_0, P2MSEL0_1, PH3_FN),
397
	PINMUX_DATA(SDIF0D2_MARK,	P2MSEL1_1, P2MSEL0_0, PH2_FN),
398
	PINMUX_DATA(SCIF0_SCK_MARK,	P2MSEL1_0, P2MSEL0_0, PH2_FN),
399
	PINMUX_DATA(IRL6_MARK,		P2MSEL1_0, P2MSEL0_1, PH2_FN),
400
	PINMUX_DATA(SDIF0D1_MARK,	P2MSEL1_1, P2MSEL0_0, PH1_FN),
401
	PINMUX_DATA(SCIF0_RXD_MARK,	P2MSEL1_0, P2MSEL0_0, PH1_FN),
402
	PINMUX_DATA(IRL5_MARK,		P2MSEL1_0, P2MSEL0_1, PH1_FN),
403
	PINMUX_DATA(SDIF0D0_MARK,	P2MSEL1_1, P2MSEL0_0, PH0_FN),
404
	PINMUX_DATA(SCIF0_TXD_MARK,	P2MSEL1_0, P2MSEL0_0, PH0_FN),
405
	PINMUX_DATA(IRL4_MARK,		P2MSEL1_0, P2MSEL0_1, PH0_FN),
406

407
	/* PJ FN */
408
	PINMUX_DATA(SCIF5_SCK_MARK,	P2MSEL11_1, PJ7_FN),
409
	PINMUX_DATA(FRB_MARK,		P2MSEL11_0, PJ7_FN),
410
	PINMUX_DATA(SCIF5_RXD_MARK,	P2MSEL10_0, PJ6_FN),
411
	PINMUX_DATA(IOIS16_MARK,	P2MSEL10_1, PJ6_FN),
412
	PINMUX_DATA(SCIF5_TXD_MARK,	P2MSEL10_0, PJ5_FN),
413
	PINMUX_DATA(CE2B_MARK,		P2MSEL10_1, PJ5_FN),
414
	PINMUX_DATA(DRAK3_MARK,		P2MSEL7_0, PJ4_FN),
415
	PINMUX_DATA(CE2A_MARK,		P2MSEL7_1, PJ4_FN),
416
	PINMUX_DATA(SCIF4_SCK_MARK,	P2MSEL9_0, P2MSEL8_0, PJ3_FN),
417
	PINMUX_DATA(DRAK2_MARK,		P2MSEL9_0, P2MSEL8_1, PJ3_FN),
418
	PINMUX_DATA(SSI3_WS_MARK,	P2MSEL9_1, P2MSEL8_0, PJ3_FN),
419
	PINMUX_DATA(SCIF4_RXD_MARK,	P2MSEL6_1, P2MSEL5_0, PJ2_FN),
420
	PINMUX_DATA(DRAK1_MARK,		P2MSEL6_0, P2MSEL5_1, PJ2_FN),
421
	PINMUX_DATA(FSTATUS_MARK,	P2MSEL6_0, P2MSEL5_0, PJ2_FN),
422
	PINMUX_DATA(SSI3_SDATA_MARK,	P2MSEL6_1, P2MSEL5_1, PJ2_FN),
423
	PINMUX_DATA(SCIF4_TXD_MARK,	P2MSEL6_1, P2MSEL5_0, PJ1_FN),
424
	PINMUX_DATA(DRAK0_MARK,		P2MSEL6_0, P2MSEL5_1, PJ1_FN),
425
	PINMUX_DATA(FSE_MARK,		P2MSEL6_0, P2MSEL5_0, PJ1_FN),
426
	PINMUX_DATA(SSI3_SCK_MARK,	P2MSEL6_1, P2MSEL5_1, PJ1_FN),
427
};
428

429
static struct pinmux_gpio pinmux_gpios[] = {
430
	/* PA */
431
	PINMUX_GPIO(GPIO_PA7, PA7_DATA),
432
	PINMUX_GPIO(GPIO_PA6, PA6_DATA),
433
	PINMUX_GPIO(GPIO_PA5, PA5_DATA),
434
	PINMUX_GPIO(GPIO_PA4, PA4_DATA),
435
	PINMUX_GPIO(GPIO_PA3, PA3_DATA),
436
	PINMUX_GPIO(GPIO_PA2, PA2_DATA),
437
	PINMUX_GPIO(GPIO_PA1, PA1_DATA),
438
	PINMUX_GPIO(GPIO_PA0, PA0_DATA),
439

440
	/* PB */
441
	PINMUX_GPIO(GPIO_PB7, PB7_DATA),
442
	PINMUX_GPIO(GPIO_PB6, PB6_DATA),
443
	PINMUX_GPIO(GPIO_PB5, PB5_DATA),
444
	PINMUX_GPIO(GPIO_PB4, PB4_DATA),
445
	PINMUX_GPIO(GPIO_PB3, PB3_DATA),
446
	PINMUX_GPIO(GPIO_PB2, PB2_DATA),
447
	PINMUX_GPIO(GPIO_PB1, PB1_DATA),
448
	PINMUX_GPIO(GPIO_PB0, PB0_DATA),
449

450
	/* PC */
451
	PINMUX_GPIO(GPIO_PC7, PC7_DATA),
452
	PINMUX_GPIO(GPIO_PC6, PC6_DATA),
453
	PINMUX_GPIO(GPIO_PC5, PC5_DATA),
454
	PINMUX_GPIO(GPIO_PC4, PC4_DATA),
455
	PINMUX_GPIO(GPIO_PC3, PC3_DATA),
456
	PINMUX_GPIO(GPIO_PC2, PC2_DATA),
457
	PINMUX_GPIO(GPIO_PC1, PC1_DATA),
458
	PINMUX_GPIO(GPIO_PC0, PC0_DATA),
459

460
	/* PD */
461
	PINMUX_GPIO(GPIO_PD7, PD7_DATA),
462
	PINMUX_GPIO(GPIO_PD6, PD6_DATA),
463
	PINMUX_GPIO(GPIO_PD5, PD5_DATA),
464
	PINMUX_GPIO(GPIO_PD4, PD4_DATA),
465
	PINMUX_GPIO(GPIO_PD3, PD3_DATA),
466
	PINMUX_GPIO(GPIO_PD2, PD2_DATA),
467
	PINMUX_GPIO(GPIO_PD1, PD1_DATA),
468
	PINMUX_GPIO(GPIO_PD0, PD0_DATA),
469

470
	/* PE */
471
	PINMUX_GPIO(GPIO_PE5, PE7_DATA),
472
	PINMUX_GPIO(GPIO_PE4, PE6_DATA),
473

474
	/* PF */
475
	PINMUX_GPIO(GPIO_PF7, PF7_DATA),
476
	PINMUX_GPIO(GPIO_PF6, PF6_DATA),
477
	PINMUX_GPIO(GPIO_PF5, PF5_DATA),
478
	PINMUX_GPIO(GPIO_PF4, PF4_DATA),
479
	PINMUX_GPIO(GPIO_PF3, PF3_DATA),
480
	PINMUX_GPIO(GPIO_PF2, PF2_DATA),
481
	PINMUX_GPIO(GPIO_PF1, PF1_DATA),
482
	PINMUX_GPIO(GPIO_PF0, PF0_DATA),
483

484
	/* PG */
485
	PINMUX_GPIO(GPIO_PG7, PG7_DATA),
486
	PINMUX_GPIO(GPIO_PG6, PG6_DATA),
487
	PINMUX_GPIO(GPIO_PG5, PG5_DATA),
488

489
	/* PH */
490
	PINMUX_GPIO(GPIO_PH7, PH7_DATA),
491
	PINMUX_GPIO(GPIO_PH6, PH6_DATA),
492
	PINMUX_GPIO(GPIO_PH5, PH5_DATA),
493
	PINMUX_GPIO(GPIO_PH4, PH4_DATA),
494
	PINMUX_GPIO(GPIO_PH3, PH3_DATA),
495
	PINMUX_GPIO(GPIO_PH2, PH2_DATA),
496
	PINMUX_GPIO(GPIO_PH1, PH1_DATA),
497
	PINMUX_GPIO(GPIO_PH0, PH0_DATA),
498

499
	/* PJ */
500
	PINMUX_GPIO(GPIO_PJ7, PJ7_DATA),
501
	PINMUX_GPIO(GPIO_PJ6, PJ6_DATA),
502
	PINMUX_GPIO(GPIO_PJ5, PJ5_DATA),
503
	PINMUX_GPIO(GPIO_PJ4, PJ4_DATA),
504
	PINMUX_GPIO(GPIO_PJ3, PJ3_DATA),
505
	PINMUX_GPIO(GPIO_PJ2, PJ2_DATA),
506
	PINMUX_GPIO(GPIO_PJ1, PJ1_DATA),
507

508
	/* FN */
509
	PINMUX_GPIO(GPIO_FN_CDE,		CDE_MARK),
510
	PINMUX_GPIO(GPIO_FN_ETH_MAGIC,		ETH_MAGIC_MARK),
511
	PINMUX_GPIO(GPIO_FN_DISP,		DISP_MARK),
512
	PINMUX_GPIO(GPIO_FN_ETH_LINK,		ETH_LINK_MARK),
513
	PINMUX_GPIO(GPIO_FN_DR5,		DR5_MARK),
514
	PINMUX_GPIO(GPIO_FN_ETH_TX_ER,		ETH_TX_ER_MARK),
515
	PINMUX_GPIO(GPIO_FN_DR4,		DR4_MARK),
516
	PINMUX_GPIO(GPIO_FN_ETH_TX_EN,		ETH_TX_EN_MARK),
517
	PINMUX_GPIO(GPIO_FN_DR3,		DR3_MARK),
518
	PINMUX_GPIO(GPIO_FN_ETH_TXD3,		ETH_TXD3_MARK),
519
	PINMUX_GPIO(GPIO_FN_DR2,		DR2_MARK),
520
	PINMUX_GPIO(GPIO_FN_ETH_TXD2,		ETH_TXD2_MARK),
521
	PINMUX_GPIO(GPIO_FN_DR1,		DR1_MARK),
522
	PINMUX_GPIO(GPIO_FN_ETH_TXD1,		ETH_TXD1_MARK),
523
	PINMUX_GPIO(GPIO_FN_DR0,		DR0_MARK),
524
	PINMUX_GPIO(GPIO_FN_ETH_TXD0,		ETH_TXD0_MARK),
525
	PINMUX_GPIO(GPIO_FN_VSYNC,		VSYNC_MARK),
526
	PINMUX_GPIO(GPIO_FN_HSPI_CLK,		HSPI_CLK_MARK),
527
	PINMUX_GPIO(GPIO_FN_ODDF,		ODDF_MARK),
528
	PINMUX_GPIO(GPIO_FN_HSPI_CS,		HSPI_CS_MARK),
529
	PINMUX_GPIO(GPIO_FN_DG5,		DG5_MARK),
530
	PINMUX_GPIO(GPIO_FN_ETH_MDIO,		ETH_MDIO_MARK),
531
	PINMUX_GPIO(GPIO_FN_DG4,		DG4_MARK),
532
	PINMUX_GPIO(GPIO_FN_ETH_RX_CLK,		ETH_RX_CLK_MARK),
533
	PINMUX_GPIO(GPIO_FN_DG3,		DG3_MARK),
534
	PINMUX_GPIO(GPIO_FN_ETH_MDC,		ETH_MDC_MARK),
535
	PINMUX_GPIO(GPIO_FN_DG2,		DG2_MARK),
536
	PINMUX_GPIO(GPIO_FN_ETH_COL,		ETH_COL_MARK),
537
	PINMUX_GPIO(GPIO_FN_DG1,		DG1_MARK),
538
	PINMUX_GPIO(GPIO_FN_ETH_TX_CLK,		ETH_TX_CLK_MARK),
539
	PINMUX_GPIO(GPIO_FN_DG0,		DG0_MARK),
540
	PINMUX_GPIO(GPIO_FN_ETH_CRS,		ETH_CRS_MARK),
541
	PINMUX_GPIO(GPIO_FN_DCLKIN,		DCLKIN_MARK),
542
	PINMUX_GPIO(GPIO_FN_HSPI_RX,		HSPI_RX_MARK),
543
	PINMUX_GPIO(GPIO_FN_HSYNC,		HSYNC_MARK),
544
	PINMUX_GPIO(GPIO_FN_HSPI_TX,		HSPI_TX_MARK),
545
	PINMUX_GPIO(GPIO_FN_DB5,		DB5_MARK),
546
	PINMUX_GPIO(GPIO_FN_ETH_RXD3,		ETH_RXD3_MARK),
547
	PINMUX_GPIO(GPIO_FN_DB4,		DB4_MARK),
548
	PINMUX_GPIO(GPIO_FN_ETH_RXD2,		ETH_RXD2_MARK),
549
	PINMUX_GPIO(GPIO_FN_DB3,		DB3_MARK),
550
	PINMUX_GPIO(GPIO_FN_ETH_RXD1,		ETH_RXD1_MARK),
551
	PINMUX_GPIO(GPIO_FN_DB2,		DB2_MARK),
552
	PINMUX_GPIO(GPIO_FN_ETH_RXD0,		ETH_RXD0_MARK),
553
	PINMUX_GPIO(GPIO_FN_DB1,		DB1_MARK),
554
	PINMUX_GPIO(GPIO_FN_ETH_RX_DV,		ETH_RX_DV_MARK),
555
	PINMUX_GPIO(GPIO_FN_DB0,		DB0_MARK),
556
	PINMUX_GPIO(GPIO_FN_ETH_RX_ER,		ETH_RX_ER_MARK),
557
	PINMUX_GPIO(GPIO_FN_DCLKOUT,		DCLKOUT_MARK),
558
	PINMUX_GPIO(GPIO_FN_SCIF1_SCK,		SCIF1_SCK_MARK),
559
	PINMUX_GPIO(GPIO_FN_SCIF1_RXD,		SCIF1_RXD_MARK),
560
	PINMUX_GPIO(GPIO_FN_SCIF1_TXD,		SCIF1_TXD_MARK),
561
	PINMUX_GPIO(GPIO_FN_DACK1,		DACK1_MARK),
562
	PINMUX_GPIO(GPIO_FN_BACK,		BACK_MARK),
563
	PINMUX_GPIO(GPIO_FN_FALE,		FALE_MARK),
564
	PINMUX_GPIO(GPIO_FN_DACK0,		DACK0_MARK),
565
	PINMUX_GPIO(GPIO_FN_FCLE,		FCLE_MARK),
566
	PINMUX_GPIO(GPIO_FN_DREQ1,		DREQ1_MARK),
567
	PINMUX_GPIO(GPIO_FN_BREQ,		BREQ_MARK),
568
	PINMUX_GPIO(GPIO_FN_USB_OVC1,		USB_OVC1_MARK),
569
	PINMUX_GPIO(GPIO_FN_DREQ0,		DREQ0_MARK),
570
	PINMUX_GPIO(GPIO_FN_USB_OVC0,		USB_OVC0_MARK),
571
	PINMUX_GPIO(GPIO_FN_USB_PENC1,		USB_PENC1_MARK),
572
	PINMUX_GPIO(GPIO_FN_USB_PENC0,		USB_PENC0_MARK),
573
	PINMUX_GPIO(GPIO_FN_HAC1_SDOUT,		HAC1_SDOUT_MARK),
574
	PINMUX_GPIO(GPIO_FN_SSI1_SDATA,		SSI1_SDATA_MARK),
575
	PINMUX_GPIO(GPIO_FN_SDIF1CMD,		SDIF1CMD_MARK),
576
	PINMUX_GPIO(GPIO_FN_HAC1_SDIN,		HAC1_SDIN_MARK),
577
	PINMUX_GPIO(GPIO_FN_SSI1_SCK,		SSI1_SCK_MARK),
578
	PINMUX_GPIO(GPIO_FN_SDIF1CD,		SDIF1CD_MARK),
579
	PINMUX_GPIO(GPIO_FN_HAC1_SYNC,		HAC1_SYNC_MARK),
580
	PINMUX_GPIO(GPIO_FN_SSI1_WS,		SSI1_WS_MARK),
581
	PINMUX_GPIO(GPIO_FN_SDIF1WP,		SDIF1WP_MARK),
582
	PINMUX_GPIO(GPIO_FN_HAC1_BITCLK,	HAC1_BITCLK_MARK),
583
	PINMUX_GPIO(GPIO_FN_SSI1_CLK,		SSI1_CLK_MARK),
584
	PINMUX_GPIO(GPIO_FN_SDIF1CLK,		SDIF1CLK_MARK),
585
	PINMUX_GPIO(GPIO_FN_HAC0_SDOUT,		HAC0_SDOUT_MARK),
586
	PINMUX_GPIO(GPIO_FN_SSI0_SDATA,		SSI0_SDATA_MARK),
587
	PINMUX_GPIO(GPIO_FN_SDIF1D3,		SDIF1D3_MARK),
588
	PINMUX_GPIO(GPIO_FN_HAC0_SDIN,		HAC0_SDIN_MARK),
589
	PINMUX_GPIO(GPIO_FN_SSI0_SCK,		SSI0_SCK_MARK),
590
	PINMUX_GPIO(GPIO_FN_SDIF1D2,		SDIF1D2_MARK),
591
	PINMUX_GPIO(GPIO_FN_HAC0_SYNC,		HAC0_SYNC_MARK),
592
	PINMUX_GPIO(GPIO_FN_SSI0_WS,		SSI0_WS_MARK),
593
	PINMUX_GPIO(GPIO_FN_SDIF1D1,		SDIF1D1_MARK),
594
	PINMUX_GPIO(GPIO_FN_HAC0_BITCLK,	HAC0_BITCLK_MARK),
595
	PINMUX_GPIO(GPIO_FN_SSI0_CLK,		SSI0_CLK_MARK),
596
	PINMUX_GPIO(GPIO_FN_SDIF1D0,		SDIF1D0_MARK),
597
	PINMUX_GPIO(GPIO_FN_SCIF3_SCK,		SCIF3_SCK_MARK),
598
	PINMUX_GPIO(GPIO_FN_SSI2_SDATA,		SSI2_SDATA_MARK),
599
	PINMUX_GPIO(GPIO_FN_SCIF3_RXD,		SCIF3_RXD_MARK),
600
	PINMUX_GPIO(GPIO_FN_TCLK,		TCLK_MARK),
601
	PINMUX_GPIO(GPIO_FN_SSI2_SCK,		SSI2_SCK_MARK),
602
	PINMUX_GPIO(GPIO_FN_SCIF3_TXD,		SCIF3_TXD_MARK),
603
	PINMUX_GPIO(GPIO_FN_HAC_RES,		HAC_RES_MARK),
604
	PINMUX_GPIO(GPIO_FN_SSI2_WS,		SSI2_WS_MARK),
605
	PINMUX_GPIO(GPIO_FN_DACK3,		DACK3_MARK),
606
	PINMUX_GPIO(GPIO_FN_SDIF0CMD,		SDIF0CMD_MARK),
607
	PINMUX_GPIO(GPIO_FN_DACK2,		DACK2_MARK),
608
	PINMUX_GPIO(GPIO_FN_SDIF0CD,		SDIF0CD_MARK),
609
	PINMUX_GPIO(GPIO_FN_DREQ3,		DREQ3_MARK),
610
	PINMUX_GPIO(GPIO_FN_SDIF0WP,		SDIF0WP_MARK),
611
	PINMUX_GPIO(GPIO_FN_SCIF0_CTS,		SCIF0_CTS_MARK),
612
	PINMUX_GPIO(GPIO_FN_DREQ2,		DREQ2_MARK),
613
	PINMUX_GPIO(GPIO_FN_SDIF0CLK,		SDIF0CLK_MARK),
614
	PINMUX_GPIO(GPIO_FN_SCIF0_RTS,		SCIF0_RTS_MARK),
615
	PINMUX_GPIO(GPIO_FN_IRL7,		IRL7_MARK),
616
	PINMUX_GPIO(GPIO_FN_SDIF0D3,		SDIF0D3_MARK),
617
	PINMUX_GPIO(GPIO_FN_SCIF0_SCK,		SCIF0_SCK_MARK),
618
	PINMUX_GPIO(GPIO_FN_IRL6,		IRL6_MARK),
619
	PINMUX_GPIO(GPIO_FN_SDIF0D2,		SDIF0D2_MARK),
620
	PINMUX_GPIO(GPIO_FN_SCIF0_RXD,		SCIF0_RXD_MARK),
621
	PINMUX_GPIO(GPIO_FN_IRL5,		IRL5_MARK),
622
	PINMUX_GPIO(GPIO_FN_SDIF0D1,		SDIF0D1_MARK),
623
	PINMUX_GPIO(GPIO_FN_SCIF0_TXD,		SCIF0_TXD_MARK),
624
	PINMUX_GPIO(GPIO_FN_IRL4,		IRL4_MARK),
625
	PINMUX_GPIO(GPIO_FN_SDIF0D0,		SDIF0D0_MARK),
626
	PINMUX_GPIO(GPIO_FN_SCIF5_SCK,		SCIF5_SCK_MARK),
627
	PINMUX_GPIO(GPIO_FN_FRB,		FRB_MARK),
628
	PINMUX_GPIO(GPIO_FN_SCIF5_RXD,		SCIF5_RXD_MARK),
629
	PINMUX_GPIO(GPIO_FN_IOIS16,		IOIS16_MARK),
630
	PINMUX_GPIO(GPIO_FN_SCIF5_TXD,		SCIF5_TXD_MARK),
631
	PINMUX_GPIO(GPIO_FN_CE2B,		CE2B_MARK),
632
	PINMUX_GPIO(GPIO_FN_DRAK3,		DRAK3_MARK),
633
	PINMUX_GPIO(GPIO_FN_CE2A,		CE2A_MARK),
634
	PINMUX_GPIO(GPIO_FN_SCIF4_SCK,		SCIF4_SCK_MARK),
635
	PINMUX_GPIO(GPIO_FN_DRAK2,		DRAK2_MARK),
636
	PINMUX_GPIO(GPIO_FN_SSI3_WS,		SSI3_WS_MARK),
637
	PINMUX_GPIO(GPIO_FN_SCIF4_RXD,		SCIF4_RXD_MARK),
638
	PINMUX_GPIO(GPIO_FN_DRAK1,		DRAK1_MARK),
639
	PINMUX_GPIO(GPIO_FN_SSI3_SDATA,		SSI3_SDATA_MARK),
640
	PINMUX_GPIO(GPIO_FN_FSTATUS,		FSTATUS_MARK),
641
	PINMUX_GPIO(GPIO_FN_SCIF4_TXD,		SCIF4_TXD_MARK),
642
	PINMUX_GPIO(GPIO_FN_DRAK0,		DRAK0_MARK),
643
	PINMUX_GPIO(GPIO_FN_SSI3_SCK,		SSI3_SCK_MARK),
644
	PINMUX_GPIO(GPIO_FN_FSE,		FSE_MARK),
645
};
646

647
static struct pinmux_cfg_reg pinmux_config_regs[] = {
648
	{ PINMUX_CFG_REG("PACR", 0xffcc0000, 16, 2) {
649
		PA7_FN, PA7_OUT, PA7_IN, PA7_IN_PU,
650
		PA6_FN, PA6_OUT, PA6_IN, PA6_IN_PU,
651
		PA5_FN, PA5_OUT, PA5_IN, PA5_IN_PU,
652
		PA4_FN, PA4_OUT, PA4_IN, PA4_IN_PU,
653
		PA3_FN, PA3_OUT, PA3_IN, PA3_IN_PU,
654
		PA2_FN, PA2_OUT, PA2_IN, PA2_IN_PU,
655
		PA1_FN, PA1_OUT, PA1_IN, PA1_IN_PU,
656
		PA0_FN, PA0_OUT, PA0_IN, PA0_IN_PU }
657
	},
658
	{ PINMUX_CFG_REG("PBCR", 0xffcc0002, 16, 2) {
659
		PB7_FN, PB7_OUT, PB7_IN, PB7_IN_PU,
660
		PB6_FN, PB6_OUT, PB6_IN, PB6_IN_PU,
661
		PB5_FN, PB5_OUT, PB5_IN, PB5_IN_PU,
662
		PB4_FN, PB4_OUT, PB4_IN, PB4_IN_PU,
663
		PB3_FN, PB3_OUT, PB3_IN, PB3_IN_PU,
664
		PB2_FN, PB2_OUT, PB2_IN, PB2_IN_PU,
665
		PB1_FN, PB1_OUT, PB1_IN, PB1_IN_PU,
666
		PB0_FN, PB0_OUT, PB0_IN, PB0_IN_PU }
667
	},
668
	{ PINMUX_CFG_REG("PCCR", 0xffcc0004, 16, 2) {
669
		PC7_FN, PC7_OUT, PC7_IN, PC7_IN_PU,
670
		PC6_FN, PC6_OUT, PC6_IN, PC6_IN_PU,
671
		PC5_FN, PC5_OUT, PC5_IN, PC5_IN_PU,
672
		PC4_FN, PC4_OUT, PC4_IN, PC4_IN_PU,
673
		PC3_FN, PC3_OUT, PC3_IN, PC3_IN_PU,
674
		PC2_FN, PC2_OUT, PC2_IN, PC2_IN_PU,
675
		PC1_FN, PC1_OUT, PC1_IN, PC1_IN_PU,
676
		PC0_FN, PC0_OUT, PC0_IN, PC0_IN_PU }
677
	},
678
	{ PINMUX_CFG_REG("PDCR", 0xffcc0006, 16, 2) {
679
		PD7_FN, PD7_OUT, PD7_IN, PD7_IN_PU,
680
		PD6_FN, PD6_OUT, PD6_IN, PD6_IN_PU,
681
		PD5_FN, PD5_OUT, PD5_IN, PD5_IN_PU,
682
		PD4_FN, PD4_OUT, PD4_IN, PD4_IN_PU,
683
		PD3_FN, PD3_OUT, PD3_IN, PD3_IN_PU,
684
		PD2_FN, PD2_OUT, PD2_IN, PD2_IN_PU,
685
		PD1_FN, PD1_OUT, PD1_IN, PD1_IN_PU,
686
		PD0_FN, PD0_OUT, PD0_IN, PD0_IN_PU }
687
	},
688
	{ PINMUX_CFG_REG("PECR", 0xffcc0008, 16, 2) {
689
		PE7_FN, PE7_OUT, PE7_IN, PE7_IN_PU,
690
		PE6_FN, PE6_OUT, PE6_IN, PE6_IN_PU,
691
		0, 0, 0, 0,
692
		0, 0, 0, 0,
693
		0, 0, 0, 0,
694
		0, 0, 0, 0,
695
		0, 0, 0, 0,
696
		0, 0, 0, 0, }
697
	},
698
	{ PINMUX_CFG_REG("PFCR", 0xffcc000a, 16, 2) {
699
		PF7_FN, PF7_OUT, PF7_IN, PF7_IN_PU,
700
		PF6_FN, PF6_OUT, PF6_IN, PF6_IN_PU,
701
		PF5_FN, PF5_OUT, PF5_IN, PF5_IN_PU,
702
		PF4_FN, PF4_OUT, PF4_IN, PF4_IN_PU,
703
		PF3_FN, PF3_OUT, PF3_IN, PF3_IN_PU,
704
		PF2_FN, PF2_OUT, PF2_IN, PF2_IN_PU,
705
		PF1_FN, PF1_OUT, PF1_IN, PF1_IN_PU,
706
		PF0_FN, PF0_OUT, PF0_IN, PF0_IN_PU }
707
	},
708
	{ PINMUX_CFG_REG("PGCR", 0xffcc000c, 16, 2) {
709
		PG7_FN, PG7_OUT, PG7_IN, PG7_IN_PU,
710
		PG6_FN, PG6_OUT, PG6_IN, PG6_IN_PU,
711
		PG5_FN, PG5_OUT, PG5_IN, PG5_IN_PU,
712
		0, 0, 0, 0,
713
		0, 0, 0, 0,
714
		0, 0, 0, 0,
715
		0, 0, 0, 0,
716
		0, 0, 0, 0, }
717
	},
718
	{ PINMUX_CFG_REG("PHCR", 0xffcc000e, 16, 2) {
719
		PH7_FN, PH7_OUT, PH7_IN, PH7_IN_PU,
720
		PH6_FN, PH6_OUT, PH6_IN, PH6_IN_PU,
721
		PH5_FN, PH5_OUT, PH5_IN, PH5_IN_PU,
722
		PH4_FN, PH4_OUT, PH4_IN, PH4_IN_PU,
723
		PH3_FN, PH3_OUT, PH3_IN, PH3_IN_PU,
724
		PH2_FN, PH2_OUT, PH2_IN, PH2_IN_PU,
725
		PH1_FN, PH1_OUT, PH1_IN, PH1_IN_PU,
726
		PH0_FN, PH0_OUT, PH0_IN, PH0_IN_PU }
727
	},
728
	{ PINMUX_CFG_REG("PJCR", 0xffcc0010, 16, 2) {
729
		PJ7_FN, PJ7_OUT, PJ7_IN, PJ7_IN_PU,
730
		PJ6_FN, PJ6_OUT, PJ6_IN, PJ6_IN_PU,
731
		PJ5_FN, PJ5_OUT, PJ5_IN, PJ5_IN_PU,
732
		PJ4_FN, PJ4_OUT, PJ4_IN, PJ4_IN_PU,
733
		PJ3_FN, PJ3_OUT, PJ3_IN, PJ3_IN_PU,
734
		PJ2_FN, PJ2_OUT, PJ2_IN, PJ2_IN_PU,
735
		PJ1_FN, PJ1_OUT, PJ1_IN, PJ1_IN_PU,
736
		0, 0, 0, 0, }
737
	},
738
	{ PINMUX_CFG_REG("P1MSELR", 0xffcc0080, 16, 1) {
739
		0, 0,
740
		P1MSEL14_0, P1MSEL14_1,
741
		P1MSEL13_0, P1MSEL13_1,
742
		P1MSEL12_0, P1MSEL12_1,
743
		P1MSEL11_0, P1MSEL11_1,
744
		P1MSEL10_0, P1MSEL10_1,
745
		P1MSEL9_0,  P1MSEL9_1,
746
		P1MSEL8_0,  P1MSEL8_1,
747
		P1MSEL7_0,  P1MSEL7_1,
748
		P1MSEL6_0,  P1MSEL6_1,
749
		P1MSEL5_0,  P1MSEL5_1,
750
		P1MSEL4_0,  P1MSEL4_1,
751
		P1MSEL3_0,  P1MSEL3_1,
752
		P1MSEL2_0,  P1MSEL2_1,
753
		P1MSEL1_0,  P1MSEL1_1,
754
		P1MSEL0_0,  P1MSEL0_1 }
755
	},
756
	{ PINMUX_CFG_REG("P2MSELR", 0xffcc0082, 16, 1) {
757
		P2MSEL15_0, P2MSEL15_1,
758
		P2MSEL14_0, P2MSEL14_1,
759
		P2MSEL13_0, P2MSEL13_1,
760
		P2MSEL12_0, P2MSEL12_1,
761
		P2MSEL11_0, P2MSEL11_1,
762
		P2MSEL10_0, P2MSEL10_1,
763
		P2MSEL9_0,  P2MSEL9_1,
764
		P2MSEL8_0,  P2MSEL8_1,
765
		P2MSEL7_0,  P2MSEL7_1,
766
		P2MSEL6_0,  P2MSEL6_1,
767
		P2MSEL5_0,  P2MSEL5_1,
768
		P2MSEL4_0,  P2MSEL4_1,
769
		P2MSEL3_0,  P2MSEL3_1,
770
		P2MSEL2_0,  P2MSEL2_1,
771
		P2MSEL1_0,  P2MSEL1_1,
772
		P2MSEL0_0,  P2MSEL0_1 }
773
	},
774
	{}
775
};
776

777
static struct pinmux_data_reg pinmux_data_regs[] = {
778
	{ PINMUX_DATA_REG("PADR", 0xffcc0020, 8) {
779
		PA7_DATA, PA6_DATA, PA5_DATA, PA4_DATA,
780
		PA3_DATA, PA2_DATA, PA1_DATA, PA0_DATA }
781
	},
782
	{ PINMUX_DATA_REG("PBDR", 0xffcc0022, 8) {
783
		PB7_DATA, PB6_DATA, PB5_DATA, PB4_DATA,
784
		PB3_DATA, PB2_DATA, PB1_DATA, PB0_DATA }
785
	},
786
	{ PINMUX_DATA_REG("PCDR", 0xffcc0024, 8) {
787
		PC7_DATA, PC6_DATA, PC5_DATA, PC4_DATA,
788
		PC3_DATA, PC2_DATA, PC1_DATA, PC0_DATA }
789
	},
790
	{ PINMUX_DATA_REG("PDDR", 0xffcc0026, 8) {
791
		PD7_DATA, PD6_DATA, PD5_DATA, PD4_DATA,
792
		PD3_DATA, PD2_DATA, PD1_DATA, PD0_DATA }
793
	},
794
	{ PINMUX_DATA_REG("PEDR", 0xffcc0028, 8) {
795
		PE7_DATA, PE6_DATA,
796
		0, 0, 0, 0, 0, 0 }
797
	},
798
	{ PINMUX_DATA_REG("PFDR", 0xffcc002a, 8) {
799
		PF7_DATA, PF6_DATA, PF5_DATA, PF4_DATA,
800
		PF3_DATA, PF2_DATA, PF1_DATA, PF0_DATA }
801
	},
802
	{ PINMUX_DATA_REG("PGDR", 0xffcc002c, 8) {
803
		PG7_DATA, PG6_DATA, PG5_DATA, 0,
804
		0, 0, 0, 0 }
805
	},
806
	{ PINMUX_DATA_REG("PHDR", 0xffcc002e, 8) {
807
		PH7_DATA, PH6_DATA, PH5_DATA, PH4_DATA,
808
		PH3_DATA, PH2_DATA, PH1_DATA, PH0_DATA }
809
	},
810
	{ PINMUX_DATA_REG("PJDR", 0xffcc0030, 8) {
811
		PJ7_DATA, PJ6_DATA, PJ5_DATA, PJ4_DATA,
812
		PJ3_DATA, PJ2_DATA, PJ1_DATA, 0 }
813
	},
814
	{ },
815
};
816

817
static struct pinmux_info sh7786_pinmux_info = {
818
	.name = "sh7786_pfc",
819
	.reserved_id = PINMUX_RESERVED,
820
	.data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
821
	.input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
822
	.input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END },
823
	.output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
824
	.mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
825
	.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
826

827
	.first_gpio = GPIO_PA7,
828
	.last_gpio = GPIO_FN_FSE,
829

830
	.gpios = pinmux_gpios,
831
	.cfg_regs = pinmux_config_regs,
832
	.data_regs = pinmux_data_regs,
833

834
	.gpio_data = pinmux_data,
835
	.gpio_data_size = ARRAY_SIZE(pinmux_data),
836
};
837

838
static int __init plat_pinmux_setup(void)
839
{
840
	return register_pinmux(&sh7786_pinmux_info);
841
}
842

843
arch_initcall(plat_pinmux_setup);
844

845
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