CoCalc -- pinmux-shx3.c

GitHub Repository: awilliam/linux-vfio
Path: blob/master/arch/sh/kernel/cpu/sh4a/pinmux-shx3.c
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1
/*
2
 * SH-X3 prototype CPU pinmux
3
 *
4
 * Copyright (C) 2010  Paul Mundt
5
 *
6
 * This file is subject to the terms and conditions of the GNU General Public
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 * License.  See the file "COPYING" in the main directory of this archive
8
 * for more details.
9
 */
10
#include <linux/init.h>
11
#include <linux/kernel.h>
12
#include <linux/gpio.h>
13
#include <cpu/shx3.h>
14

15
enum {
16
	PINMUX_RESERVED = 0,
17

18
	PINMUX_DATA_BEGIN,
19
	PA7_DATA, PA6_DATA, PA5_DATA, PA4_DATA,
20
	PA3_DATA, PA2_DATA, PA1_DATA, PA0_DATA,
21
	PB7_DATA, PB6_DATA, PB5_DATA, PB4_DATA,
22
	PB3_DATA, PB2_DATA, PB1_DATA, PB0_DATA,
23
	PC7_DATA, PC6_DATA, PC5_DATA, PC4_DATA,
24
	PC3_DATA, PC2_DATA, PC1_DATA, PC0_DATA,
25
	PD7_DATA, PD6_DATA, PD5_DATA, PD4_DATA,
26
	PD3_DATA, PD2_DATA, PD1_DATA, PD0_DATA,
27
	PE7_DATA, PE6_DATA, PE5_DATA, PE4_DATA,
28
	PE3_DATA, PE2_DATA, PE1_DATA, PE0_DATA,
29
	PF7_DATA, PF6_DATA, PF5_DATA, PF4_DATA,
30
	PF3_DATA, PF2_DATA, PF1_DATA, PF0_DATA,
31
	PG7_DATA, PG6_DATA, PG5_DATA, PG4_DATA,
32
	PG3_DATA, PG2_DATA, PG1_DATA, PG0_DATA,
33

34
	PH5_DATA, PH4_DATA,
35
	PH3_DATA, PH2_DATA, PH1_DATA, PH0_DATA,
36
	PINMUX_DATA_END,
37

38
	PINMUX_INPUT_BEGIN,
39
	PA7_IN, PA6_IN, PA5_IN, PA4_IN,
40
	PA3_IN, PA2_IN, PA1_IN, PA0_IN,
41
	PB7_IN, PB6_IN, PB5_IN, PB4_IN,
42
	PB3_IN, PB2_IN, PB1_IN, PB0_IN,
43
	PC7_IN, PC6_IN, PC5_IN, PC4_IN,
44
	PC3_IN, PC2_IN, PC1_IN, PC0_IN,
45
	PD7_IN, PD6_IN, PD5_IN, PD4_IN,
46
	PD3_IN, PD2_IN, PD1_IN, PD0_IN,
47
	PE7_IN, PE6_IN, PE5_IN, PE4_IN,
48
	PE3_IN, PE2_IN, PE1_IN, PE0_IN,
49
	PF7_IN, PF6_IN, PF5_IN, PF4_IN,
50
	PF3_IN, PF2_IN, PF1_IN, PF0_IN,
51
	PG7_IN, PG6_IN, PG5_IN, PG4_IN,
52
	PG3_IN, PG2_IN, PG1_IN, PG0_IN,
53

54
	PH5_IN, PH4_IN,
55
	PH3_IN, PH2_IN, PH1_IN, PH0_IN,
56
	PINMUX_INPUT_END,
57

58
	PINMUX_INPUT_PULLUP_BEGIN,
59
	PA7_IN_PU, PA6_IN_PU, PA5_IN_PU, PA4_IN_PU,
60
	PA3_IN_PU, PA2_IN_PU, PA1_IN_PU, PA0_IN_PU,
61
	PB7_IN_PU, PB6_IN_PU, PB5_IN_PU, PB4_IN_PU,
62
	PB3_IN_PU, PB2_IN_PU, PB1_IN_PU, PB0_IN_PU,
63
	PC7_IN_PU, PC6_IN_PU, PC5_IN_PU, PC4_IN_PU,
64
	PC3_IN_PU, PC2_IN_PU, PC1_IN_PU, PC0_IN_PU,
65
	PD7_IN_PU, PD6_IN_PU, PD5_IN_PU, PD4_IN_PU,
66
	PD3_IN_PU, PD2_IN_PU, PD1_IN_PU, PD0_IN_PU,
67
	PE7_IN_PU, PE6_IN_PU, PE5_IN_PU, PE4_IN_PU,
68
	PE3_IN_PU, PE2_IN_PU, PE1_IN_PU, PE0_IN_PU,
69
	PF7_IN_PU, PF6_IN_PU, PF5_IN_PU, PF4_IN_PU,
70
	PF3_IN_PU, PF2_IN_PU, PF1_IN_PU, PF0_IN_PU,
71
	PG7_IN_PU, PG6_IN_PU, PG5_IN_PU, PG4_IN_PU,
72
	PG3_IN_PU, PG2_IN_PU, PG1_IN_PU, PG0_IN_PU,
73

74
	PH5_IN_PU, PH4_IN_PU,
75
	PH3_IN_PU, PH2_IN_PU, PH1_IN_PU, PH0_IN_PU,
76
	PINMUX_INPUT_PULLUP_END,
77

78
	PINMUX_OUTPUT_BEGIN,
79
	PA7_OUT, PA6_OUT, PA5_OUT, PA4_OUT,
80
	PA3_OUT, PA2_OUT, PA1_OUT, PA0_OUT,
81
	PB7_OUT, PB6_OUT, PB5_OUT, PB4_OUT,
82
	PB3_OUT, PB2_OUT, PB1_OUT, PB0_OUT,
83
	PC7_OUT, PC6_OUT, PC5_OUT, PC4_OUT,
84
	PC3_OUT, PC2_OUT, PC1_OUT, PC0_OUT,
85
	PD7_OUT, PD6_OUT, PD5_OUT, PD4_OUT,
86
	PD3_OUT, PD2_OUT, PD1_OUT, PD0_OUT,
87
	PE7_OUT, PE6_OUT, PE5_OUT, PE4_OUT,
88
	PE3_OUT, PE2_OUT, PE1_OUT, PE0_OUT,
89
	PF7_OUT, PF6_OUT, PF5_OUT, PF4_OUT,
90
	PF3_OUT, PF2_OUT, PF1_OUT, PF0_OUT,
91
	PG7_OUT, PG6_OUT, PG5_OUT, PG4_OUT,
92
	PG3_OUT, PG2_OUT, PG1_OUT, PG0_OUT,
93

94
	PH5_OUT, PH4_OUT,
95
	PH3_OUT, PH2_OUT, PH1_OUT, PH0_OUT,
96
	PINMUX_OUTPUT_END,
97

98
	PINMUX_FUNCTION_BEGIN,
99
	PA7_FN, PA6_FN, PA5_FN, PA4_FN,
100
	PA3_FN, PA2_FN, PA1_FN, PA0_FN,
101
	PB7_FN, PB6_FN, PB5_FN, PB4_FN,
102
	PB3_FN, PB2_FN, PB1_FN, PB0_FN,
103
	PC7_FN, PC6_FN, PC5_FN, PC4_FN,
104
	PC3_FN, PC2_FN, PC1_FN, PC0_FN,
105
	PD7_FN, PD6_FN, PD5_FN, PD4_FN,
106
	PD3_FN, PD2_FN, PD1_FN, PD0_FN,
107
	PE7_FN, PE6_FN, PE5_FN, PE4_FN,
108
	PE3_FN, PE2_FN, PE1_FN, PE0_FN,
109
	PF7_FN, PF6_FN, PF5_FN, PF4_FN,
110
	PF3_FN, PF2_FN, PF1_FN, PF0_FN,
111
	PG7_FN, PG6_FN, PG5_FN, PG4_FN,
112
	PG3_FN, PG2_FN, PG1_FN, PG0_FN,
113

114
	PH5_FN, PH4_FN,
115
	PH3_FN, PH2_FN, PH1_FN, PH0_FN,
116
	PINMUX_FUNCTION_END,
117

118
	PINMUX_MARK_BEGIN,
119

120
	D31_MARK, D30_MARK, D29_MARK, D28_MARK, D27_MARK, D26_MARK,
121
	D25_MARK, D24_MARK, D23_MARK, D22_MARK, D21_MARK, D20_MARK,
122
	D19_MARK, D18_MARK, D17_MARK, D16_MARK,
123

124
	BACK_MARK, BREQ_MARK,
125
	WE3_MARK, WE2_MARK,
126
	CS6_MARK, CS5_MARK, CS4_MARK,
127
	CLKOUTENB_MARK,
128

129
	DACK3_MARK, DACK2_MARK, DACK1_MARK, DACK0_MARK,
130
	DREQ3_MARK, DREQ2_MARK, DREQ1_MARK, DREQ0_MARK,
131

132
	IRQ3_MARK, IRQ2_MARK, IRQ1_MARK, IRQ0_MARK,
133

134
	DRAK3_MARK, DRAK2_MARK, DRAK1_MARK, DRAK0_MARK,
135

136
	SCK3_MARK, SCK2_MARK, SCK1_MARK, SCK0_MARK,
137
	IRL3_MARK, IRL2_MARK, IRL1_MARK, IRL0_MARK,
138
	TXD3_MARK, TXD2_MARK, TXD1_MARK, TXD0_MARK,
139
	RXD3_MARK, RXD2_MARK, RXD1_MARK, RXD0_MARK,
140

141
	CE2B_MARK, CE2A_MARK, IOIS16_MARK,
142
	STATUS1_MARK, STATUS0_MARK,
143

144
	IRQOUT_MARK,
145

146
	PINMUX_MARK_END,
147
};
148

149
static pinmux_enum_t shx3_pinmux_data[] = {
150

151
	/* PA GPIO */
152
	PINMUX_DATA(PA7_DATA, PA7_IN, PA7_OUT, PA7_IN_PU),
153
	PINMUX_DATA(PA6_DATA, PA6_IN, PA6_OUT, PA6_IN_PU),
154
	PINMUX_DATA(PA5_DATA, PA5_IN, PA5_OUT, PA5_IN_PU),
155
	PINMUX_DATA(PA4_DATA, PA4_IN, PA4_OUT, PA4_IN_PU),
156
	PINMUX_DATA(PA3_DATA, PA3_IN, PA3_OUT, PA3_IN_PU),
157
	PINMUX_DATA(PA2_DATA, PA2_IN, PA2_OUT, PA2_IN_PU),
158
	PINMUX_DATA(PA1_DATA, PA1_IN, PA1_OUT, PA1_IN_PU),
159
	PINMUX_DATA(PA0_DATA, PA0_IN, PA0_OUT, PA0_IN_PU),
160

161
	/* PB GPIO */
162
	PINMUX_DATA(PB7_DATA, PB7_IN, PB7_OUT, PB7_IN_PU),
163
	PINMUX_DATA(PB6_DATA, PB6_IN, PB6_OUT, PB6_IN_PU),
164
	PINMUX_DATA(PB5_DATA, PB5_IN, PB5_OUT, PB5_IN_PU),
165
	PINMUX_DATA(PB4_DATA, PB4_IN, PB4_OUT, PB4_IN_PU),
166
	PINMUX_DATA(PB3_DATA, PB3_IN, PB3_OUT, PB3_IN_PU),
167
	PINMUX_DATA(PB2_DATA, PB2_IN, PB2_OUT, PB2_IN_PU),
168
	PINMUX_DATA(PB1_DATA, PB1_IN, PB1_OUT, PB1_IN_PU),
169
	PINMUX_DATA(PB0_DATA, PB0_IN, PB0_OUT, PB0_IN_PU),
170

171
	/* PC GPIO */
172
	PINMUX_DATA(PC7_DATA, PC7_IN, PC7_OUT, PC7_IN_PU),
173
	PINMUX_DATA(PC6_DATA, PC6_IN, PC6_OUT, PC6_IN_PU),
174
	PINMUX_DATA(PC5_DATA, PC5_IN, PC5_OUT, PC5_IN_PU),
175
	PINMUX_DATA(PC4_DATA, PC4_IN, PC4_OUT, PC4_IN_PU),
176
	PINMUX_DATA(PC3_DATA, PC3_IN, PC3_OUT, PC3_IN_PU),
177
	PINMUX_DATA(PC2_DATA, PC2_IN, PC2_OUT, PC2_IN_PU),
178
	PINMUX_DATA(PC1_DATA, PC1_IN, PC1_OUT, PC1_IN_PU),
179
	PINMUX_DATA(PC0_DATA, PC0_IN, PC0_OUT, PC0_IN_PU),
180

181
	/* PD GPIO */
182
	PINMUX_DATA(PD7_DATA, PD7_IN, PD7_OUT, PD7_IN_PU),
183
	PINMUX_DATA(PD6_DATA, PD6_IN, PD6_OUT, PD6_IN_PU),
184
	PINMUX_DATA(PD5_DATA, PD5_IN, PD5_OUT, PD5_IN_PU),
185
	PINMUX_DATA(PD4_DATA, PD4_IN, PD4_OUT, PD4_IN_PU),
186
	PINMUX_DATA(PD3_DATA, PD3_IN, PD3_OUT, PD3_IN_PU),
187
	PINMUX_DATA(PD2_DATA, PD2_IN, PD2_OUT, PD2_IN_PU),
188
	PINMUX_DATA(PD1_DATA, PD1_IN, PD1_OUT, PD1_IN_PU),
189
	PINMUX_DATA(PD0_DATA, PD0_IN, PD0_OUT, PD0_IN_PU),
190

191
	/* PE GPIO */
192
	PINMUX_DATA(PE7_DATA, PE7_IN, PE7_OUT, PE7_IN_PU),
193
	PINMUX_DATA(PE6_DATA, PE6_IN, PE6_OUT, PE6_IN_PU),
194
	PINMUX_DATA(PE5_DATA, PE5_IN, PE5_OUT, PE5_IN_PU),
195
	PINMUX_DATA(PE4_DATA, PE4_IN, PE4_OUT, PE4_IN_PU),
196
	PINMUX_DATA(PE3_DATA, PE3_IN, PE3_OUT, PE3_IN_PU),
197
	PINMUX_DATA(PE2_DATA, PE2_IN, PE2_OUT, PE2_IN_PU),
198
	PINMUX_DATA(PE1_DATA, PE1_IN, PE1_OUT, PE1_IN_PU),
199
	PINMUX_DATA(PE0_DATA, PE0_IN, PE0_OUT, PE0_IN_PU),
200

201
	/* PF GPIO */
202
	PINMUX_DATA(PF7_DATA, PF7_IN, PF7_OUT, PF7_IN_PU),
203
	PINMUX_DATA(PF6_DATA, PF6_IN, PF6_OUT, PF6_IN_PU),
204
	PINMUX_DATA(PF5_DATA, PF5_IN, PF5_OUT, PF5_IN_PU),
205
	PINMUX_DATA(PF4_DATA, PF4_IN, PF4_OUT, PF4_IN_PU),
206
	PINMUX_DATA(PF3_DATA, PF3_IN, PF3_OUT, PF3_IN_PU),
207
	PINMUX_DATA(PF2_DATA, PF2_IN, PF2_OUT, PF2_IN_PU),
208
	PINMUX_DATA(PF1_DATA, PF1_IN, PF1_OUT, PF1_IN_PU),
209
	PINMUX_DATA(PF0_DATA, PF0_IN, PF0_OUT, PF0_IN_PU),
210

211
	/* PG GPIO */
212
	PINMUX_DATA(PG7_DATA, PG7_IN, PG7_OUT, PG7_IN_PU),
213
	PINMUX_DATA(PG6_DATA, PG6_IN, PG6_OUT, PG6_IN_PU),
214
	PINMUX_DATA(PG5_DATA, PG5_IN, PG5_OUT, PG5_IN_PU),
215
	PINMUX_DATA(PG4_DATA, PG4_IN, PG4_OUT, PG4_IN_PU),
216
	PINMUX_DATA(PG3_DATA, PG3_IN, PG3_OUT, PG3_IN_PU),
217
	PINMUX_DATA(PG2_DATA, PG2_IN, PG2_OUT, PG2_IN_PU),
218
	PINMUX_DATA(PG1_DATA, PG1_IN, PG1_OUT, PG1_IN_PU),
219
	PINMUX_DATA(PG0_DATA, PG0_IN, PG0_OUT, PG0_IN_PU),
220

221
	/* PH GPIO */
222
	PINMUX_DATA(PH5_DATA, PH5_IN, PH5_OUT, PH5_IN_PU),
223
	PINMUX_DATA(PH4_DATA, PH4_IN, PH4_OUT, PH4_IN_PU),
224
	PINMUX_DATA(PH3_DATA, PH3_IN, PH3_OUT, PH3_IN_PU),
225
	PINMUX_DATA(PH2_DATA, PH2_IN, PH2_OUT, PH2_IN_PU),
226
	PINMUX_DATA(PH1_DATA, PH1_IN, PH1_OUT, PH1_IN_PU),
227
	PINMUX_DATA(PH0_DATA, PH0_IN, PH0_OUT, PH0_IN_PU),
228

229
	/* PA FN */
230
	PINMUX_DATA(D31_MARK, PA7_FN),
231
	PINMUX_DATA(D30_MARK, PA6_FN),
232
	PINMUX_DATA(D29_MARK, PA5_FN),
233
	PINMUX_DATA(D28_MARK, PA4_FN),
234
	PINMUX_DATA(D27_MARK, PA3_FN),
235
	PINMUX_DATA(D26_MARK, PA2_FN),
236
	PINMUX_DATA(D25_MARK, PA1_FN),
237
	PINMUX_DATA(D24_MARK, PA0_FN),
238

239
	/* PB FN */
240
	PINMUX_DATA(D23_MARK, PB7_FN),
241
	PINMUX_DATA(D22_MARK, PB6_FN),
242
	PINMUX_DATA(D21_MARK, PB5_FN),
243
	PINMUX_DATA(D20_MARK, PB4_FN),
244
	PINMUX_DATA(D19_MARK, PB3_FN),
245
	PINMUX_DATA(D18_MARK, PB2_FN),
246
	PINMUX_DATA(D17_MARK, PB1_FN),
247
	PINMUX_DATA(D16_MARK, PB0_FN),
248

249
	/* PC FN */
250
	PINMUX_DATA(BACK_MARK,		PC7_FN),
251
	PINMUX_DATA(BREQ_MARK,		PC6_FN),
252
	PINMUX_DATA(WE3_MARK,		PC5_FN),
253
	PINMUX_DATA(WE2_MARK,		PC4_FN),
254
	PINMUX_DATA(CS6_MARK,		PC3_FN),
255
	PINMUX_DATA(CS5_MARK,		PC2_FN),
256
	PINMUX_DATA(CS4_MARK,		PC1_FN),
257
	PINMUX_DATA(CLKOUTENB_MARK,	PC0_FN),
258

259
	/* PD FN */
260
	PINMUX_DATA(DACK3_MARK,	PD7_FN),
261
	PINMUX_DATA(DACK2_MARK, PD6_FN),
262
	PINMUX_DATA(DACK1_MARK, PD5_FN),
263
	PINMUX_DATA(DACK0_MARK, PD4_FN),
264
	PINMUX_DATA(DREQ3_MARK, PD3_FN),
265
	PINMUX_DATA(DREQ2_MARK, PD2_FN),
266
	PINMUX_DATA(DREQ1_MARK, PD1_FN),
267
	PINMUX_DATA(DREQ0_MARK, PD0_FN),
268

269
	/* PE FN */
270
	PINMUX_DATA(IRQ3_MARK,	PE7_FN),
271
	PINMUX_DATA(IRQ2_MARK,	PE6_FN),
272
	PINMUX_DATA(IRQ1_MARK,	PE5_FN),
273
	PINMUX_DATA(IRQ0_MARK,	PE4_FN),
274
	PINMUX_DATA(DRAK3_MARK, PE3_FN),
275
	PINMUX_DATA(DRAK2_MARK, PE2_FN),
276
	PINMUX_DATA(DRAK1_MARK, PE1_FN),
277
	PINMUX_DATA(DRAK0_MARK, PE0_FN),
278

279
	/* PF FN */
280
	PINMUX_DATA(SCK3_MARK, PF7_FN),
281
	PINMUX_DATA(SCK2_MARK, PF6_FN),
282
	PINMUX_DATA(SCK1_MARK, PF5_FN),
283
	PINMUX_DATA(SCK0_MARK, PF4_FN),
284
	PINMUX_DATA(IRL3_MARK, PF3_FN),
285
	PINMUX_DATA(IRL2_MARK, PF2_FN),
286
	PINMUX_DATA(IRL1_MARK, PF1_FN),
287
	PINMUX_DATA(IRL0_MARK, PF0_FN),
288

289
	/* PG FN */
290
	PINMUX_DATA(TXD3_MARK, PG7_FN),
291
	PINMUX_DATA(TXD2_MARK, PG6_FN),
292
	PINMUX_DATA(TXD1_MARK, PG5_FN),
293
	PINMUX_DATA(TXD0_MARK, PG4_FN),
294
	PINMUX_DATA(RXD3_MARK, PG3_FN),
295
	PINMUX_DATA(RXD2_MARK, PG2_FN),
296
	PINMUX_DATA(RXD1_MARK, PG1_FN),
297
	PINMUX_DATA(RXD0_MARK, PG0_FN),
298

299
	/* PH FN */
300
	PINMUX_DATA(CE2B_MARK,		PH5_FN),
301
	PINMUX_DATA(CE2A_MARK,		PH4_FN),
302
	PINMUX_DATA(IOIS16_MARK,	PH3_FN),
303
	PINMUX_DATA(STATUS1_MARK,	PH2_FN),
304
	PINMUX_DATA(STATUS0_MARK,	PH1_FN),
305
	PINMUX_DATA(IRQOUT_MARK,	PH0_FN),
306
};
307

308
static struct pinmux_gpio shx3_pinmux_gpios[] = {
309
	/* PA */
310
	PINMUX_GPIO(GPIO_PA7, PA7_DATA),
311
	PINMUX_GPIO(GPIO_PA6, PA6_DATA),
312
	PINMUX_GPIO(GPIO_PA5, PA5_DATA),
313
	PINMUX_GPIO(GPIO_PA4, PA4_DATA),
314
	PINMUX_GPIO(GPIO_PA3, PA3_DATA),
315
	PINMUX_GPIO(GPIO_PA2, PA2_DATA),
316
	PINMUX_GPIO(GPIO_PA1, PA1_DATA),
317
	PINMUX_GPIO(GPIO_PA0, PA0_DATA),
318

319
	/* PB */
320
	PINMUX_GPIO(GPIO_PB7, PB7_DATA),
321
	PINMUX_GPIO(GPIO_PB6, PB6_DATA),
322
	PINMUX_GPIO(GPIO_PB5, PB5_DATA),
323
	PINMUX_GPIO(GPIO_PB4, PB4_DATA),
324
	PINMUX_GPIO(GPIO_PB3, PB3_DATA),
325
	PINMUX_GPIO(GPIO_PB2, PB2_DATA),
326
	PINMUX_GPIO(GPIO_PB1, PB1_DATA),
327
	PINMUX_GPIO(GPIO_PB0, PB0_DATA),
328

329
	/* PC */
330
	PINMUX_GPIO(GPIO_PC7, PC7_DATA),
331
	PINMUX_GPIO(GPIO_PC6, PC6_DATA),
332
	PINMUX_GPIO(GPIO_PC5, PC5_DATA),
333
	PINMUX_GPIO(GPIO_PC4, PC4_DATA),
334
	PINMUX_GPIO(GPIO_PC3, PC3_DATA),
335
	PINMUX_GPIO(GPIO_PC2, PC2_DATA),
336
	PINMUX_GPIO(GPIO_PC1, PC1_DATA),
337
	PINMUX_GPIO(GPIO_PC0, PC0_DATA),
338

339
	/* PD */
340
	PINMUX_GPIO(GPIO_PD7, PD7_DATA),
341
	PINMUX_GPIO(GPIO_PD6, PD6_DATA),
342
	PINMUX_GPIO(GPIO_PD5, PD5_DATA),
343
	PINMUX_GPIO(GPIO_PD4, PD4_DATA),
344
	PINMUX_GPIO(GPIO_PD3, PD3_DATA),
345
	PINMUX_GPIO(GPIO_PD2, PD2_DATA),
346
	PINMUX_GPIO(GPIO_PD1, PD1_DATA),
347
	PINMUX_GPIO(GPIO_PD0, PD0_DATA),
348

349
	/* PE */
350
	PINMUX_GPIO(GPIO_PE7, PE7_DATA),
351
	PINMUX_GPIO(GPIO_PE6, PE6_DATA),
352
	PINMUX_GPIO(GPIO_PE5, PE5_DATA),
353
	PINMUX_GPIO(GPIO_PE4, PE4_DATA),
354
	PINMUX_GPIO(GPIO_PE3, PE3_DATA),
355
	PINMUX_GPIO(GPIO_PE2, PE2_DATA),
356
	PINMUX_GPIO(GPIO_PE1, PE1_DATA),
357
	PINMUX_GPIO(GPIO_PE0, PE0_DATA),
358

359
	/* PF */
360
	PINMUX_GPIO(GPIO_PF7, PF7_DATA),
361
	PINMUX_GPIO(GPIO_PF6, PF6_DATA),
362
	PINMUX_GPIO(GPIO_PF5, PF5_DATA),
363
	PINMUX_GPIO(GPIO_PF4, PF4_DATA),
364
	PINMUX_GPIO(GPIO_PF3, PF3_DATA),
365
	PINMUX_GPIO(GPIO_PF2, PF2_DATA),
366
	PINMUX_GPIO(GPIO_PF1, PF1_DATA),
367
	PINMUX_GPIO(GPIO_PF0, PF0_DATA),
368

369
	/* PG */
370
	PINMUX_GPIO(GPIO_PG7, PG7_DATA),
371
	PINMUX_GPIO(GPIO_PG6, PG6_DATA),
372
	PINMUX_GPIO(GPIO_PG5, PG5_DATA),
373
	PINMUX_GPIO(GPIO_PG4, PG4_DATA),
374
	PINMUX_GPIO(GPIO_PG3, PG3_DATA),
375
	PINMUX_GPIO(GPIO_PG2, PG2_DATA),
376
	PINMUX_GPIO(GPIO_PG1, PG1_DATA),
377
	PINMUX_GPIO(GPIO_PG0, PG0_DATA),
378

379
	/* PH */
380
	PINMUX_GPIO(GPIO_PH5, PH5_DATA),
381
	PINMUX_GPIO(GPIO_PH4, PH4_DATA),
382
	PINMUX_GPIO(GPIO_PH3, PH3_DATA),
383
	PINMUX_GPIO(GPIO_PH2, PH2_DATA),
384
	PINMUX_GPIO(GPIO_PH1, PH1_DATA),
385
	PINMUX_GPIO(GPIO_PH0, PH0_DATA),
386

387
	/* FN */
388
	PINMUX_GPIO(GPIO_FN_D31,	D31_MARK),
389
	PINMUX_GPIO(GPIO_FN_D30,	D30_MARK),
390
	PINMUX_GPIO(GPIO_FN_D29,	D29_MARK),
391
	PINMUX_GPIO(GPIO_FN_D28,	D28_MARK),
392
	PINMUX_GPIO(GPIO_FN_D27,	D27_MARK),
393
	PINMUX_GPIO(GPIO_FN_D26,	D26_MARK),
394
	PINMUX_GPIO(GPIO_FN_D25,	D25_MARK),
395
	PINMUX_GPIO(GPIO_FN_D24,	D24_MARK),
396
	PINMUX_GPIO(GPIO_FN_D23,	D23_MARK),
397
	PINMUX_GPIO(GPIO_FN_D22,	D22_MARK),
398
	PINMUX_GPIO(GPIO_FN_D21,	D21_MARK),
399
	PINMUX_GPIO(GPIO_FN_D20,	D20_MARK),
400
	PINMUX_GPIO(GPIO_FN_D19,	D19_MARK),
401
	PINMUX_GPIO(GPIO_FN_D18,	D18_MARK),
402
	PINMUX_GPIO(GPIO_FN_D17,	D17_MARK),
403
	PINMUX_GPIO(GPIO_FN_D16,	D16_MARK),
404
	PINMUX_GPIO(GPIO_FN_BACK,	BACK_MARK),
405
	PINMUX_GPIO(GPIO_FN_BREQ,	BREQ_MARK),
406
	PINMUX_GPIO(GPIO_FN_WE3,	WE3_MARK),
407
	PINMUX_GPIO(GPIO_FN_WE2,	WE2_MARK),
408
	PINMUX_GPIO(GPIO_FN_CS6,	CS6_MARK),
409
	PINMUX_GPIO(GPIO_FN_CS5,	CS5_MARK),
410
	PINMUX_GPIO(GPIO_FN_CS4,	CS4_MARK),
411
	PINMUX_GPIO(GPIO_FN_CLKOUTENB,	CLKOUTENB_MARK),
412
	PINMUX_GPIO(GPIO_FN_DACK3,	DACK3_MARK),
413
	PINMUX_GPIO(GPIO_FN_DACK2,	DACK2_MARK),
414
	PINMUX_GPIO(GPIO_FN_DACK1,	DACK1_MARK),
415
	PINMUX_GPIO(GPIO_FN_DACK0,	DACK0_MARK),
416
	PINMUX_GPIO(GPIO_FN_DREQ3,	DREQ3_MARK),
417
	PINMUX_GPIO(GPIO_FN_DREQ2,	DREQ2_MARK),
418
	PINMUX_GPIO(GPIO_FN_DREQ1,	DREQ1_MARK),
419
	PINMUX_GPIO(GPIO_FN_DREQ0,	DREQ0_MARK),
420
	PINMUX_GPIO(GPIO_FN_IRQ3,	IRQ3_MARK),
421
	PINMUX_GPIO(GPIO_FN_IRQ2,	IRQ2_MARK),
422
	PINMUX_GPIO(GPIO_FN_IRQ1,	IRQ1_MARK),
423
	PINMUX_GPIO(GPIO_FN_IRQ0,	IRQ0_MARK),
424
	PINMUX_GPIO(GPIO_FN_DRAK3,	DRAK3_MARK),
425
	PINMUX_GPIO(GPIO_FN_DRAK2,	DRAK2_MARK),
426
	PINMUX_GPIO(GPIO_FN_DRAK1,	DRAK1_MARK),
427
	PINMUX_GPIO(GPIO_FN_DRAK0,	DRAK0_MARK),
428
	PINMUX_GPIO(GPIO_FN_SCK3,	SCK3_MARK),
429
	PINMUX_GPIO(GPIO_FN_SCK2,	SCK2_MARK),
430
	PINMUX_GPIO(GPIO_FN_SCK1,	SCK1_MARK),
431
	PINMUX_GPIO(GPIO_FN_SCK0,	SCK0_MARK),
432
	PINMUX_GPIO(GPIO_FN_IRL3,	IRL3_MARK),
433
	PINMUX_GPIO(GPIO_FN_IRL2,	IRL2_MARK),
434
	PINMUX_GPIO(GPIO_FN_IRL1,	IRL1_MARK),
435
	PINMUX_GPIO(GPIO_FN_IRL0,	IRL0_MARK),
436
	PINMUX_GPIO(GPIO_FN_TXD3,	TXD3_MARK),
437
	PINMUX_GPIO(GPIO_FN_TXD2,	TXD2_MARK),
438
	PINMUX_GPIO(GPIO_FN_TXD1,	TXD1_MARK),
439
	PINMUX_GPIO(GPIO_FN_TXD0,	TXD0_MARK),
440
	PINMUX_GPIO(GPIO_FN_RXD3,	RXD3_MARK),
441
	PINMUX_GPIO(GPIO_FN_RXD2,	RXD2_MARK),
442
	PINMUX_GPIO(GPIO_FN_RXD1,	RXD1_MARK),
443
	PINMUX_GPIO(GPIO_FN_RXD0,	RXD0_MARK),
444
	PINMUX_GPIO(GPIO_FN_CE2B,	CE2B_MARK),
445
	PINMUX_GPIO(GPIO_FN_CE2A,	CE2A_MARK),
446
	PINMUX_GPIO(GPIO_FN_IOIS16,	IOIS16_MARK),
447
	PINMUX_GPIO(GPIO_FN_STATUS1,	STATUS1_MARK),
448
	PINMUX_GPIO(GPIO_FN_STATUS0,	STATUS0_MARK),
449
	PINMUX_GPIO(GPIO_FN_IRQOUT,	IRQOUT_MARK),
450
};
451

452
static struct pinmux_cfg_reg shx3_pinmux_config_regs[] = {
453
	{ PINMUX_CFG_REG("PABCR", 0xffc70000, 32, 2) {
454
		PA7_FN, PA7_OUT, PA7_IN, PA7_IN_PU,
455
		PA6_FN, PA6_OUT, PA6_IN, PA6_IN_PU,
456
		PA5_FN, PA5_OUT, PA5_IN, PA5_IN_PU,
457
		PA4_FN, PA4_OUT, PA4_IN, PA4_IN_PU,
458
		PA3_FN, PA3_OUT, PA3_IN, PA3_IN_PU,
459
		PA2_FN, PA2_OUT, PA2_IN, PA2_IN_PU,
460
		PA1_FN, PA1_OUT, PA1_IN, PA1_IN_PU,
461
		PA0_FN, PA0_OUT, PA0_IN, PA0_IN_PU,
462
		PB7_FN, PB7_OUT, PB7_IN, PB7_IN_PU,
463
		PB6_FN, PB6_OUT, PB6_IN, PB6_IN_PU,
464
		PB5_FN, PB5_OUT, PB5_IN, PB5_IN_PU,
465
		PB4_FN, PB4_OUT, PB4_IN, PB4_IN_PU,
466
		PB3_FN, PB3_OUT, PB3_IN, PB3_IN_PU,
467
		PB2_FN, PB2_OUT, PB2_IN, PB2_IN_PU,
468
		PB1_FN, PB1_OUT, PB1_IN, PB1_IN_PU,
469
		PB0_FN, PB0_OUT, PB0_IN, PB0_IN_PU, },
470
	},
471
	{ PINMUX_CFG_REG("PCDCR", 0xffc70004, 32, 2) {
472
		PC7_FN, PC7_OUT, PC7_IN, PC7_IN_PU,
473
		PC6_FN, PC6_OUT, PC6_IN, PC6_IN_PU,
474
		PC5_FN, PC5_OUT, PC5_IN, PC5_IN_PU,
475
		PC4_FN, PC4_OUT, PC4_IN, PC4_IN_PU,
476
		PC3_FN, PC3_OUT, PC3_IN, PC3_IN_PU,
477
		PC2_FN, PC2_OUT, PC2_IN, PC2_IN_PU,
478
		PC1_FN, PC1_OUT, PC1_IN, PC1_IN_PU,
479
		PC0_FN, PC0_OUT, PC0_IN, PC0_IN_PU,
480
		PD7_FN, PD7_OUT, PD7_IN, PD7_IN_PU,
481
		PD6_FN, PD6_OUT, PD6_IN, PD6_IN_PU,
482
		PD5_FN, PD5_OUT, PD5_IN, PD5_IN_PU,
483
		PD4_FN, PD4_OUT, PD4_IN, PD4_IN_PU,
484
		PD3_FN, PD3_OUT, PD3_IN, PD3_IN_PU,
485
		PD2_FN, PD2_OUT, PD2_IN, PD2_IN_PU,
486
		PD1_FN, PD1_OUT, PD1_IN, PD1_IN_PU,
487
		PD0_FN, PD0_OUT, PD0_IN, PD0_IN_PU, },
488
	},
489
	{ PINMUX_CFG_REG("PEFCR", 0xffc70008, 32, 2) {
490
		PE7_FN, PE7_OUT, PE7_IN, PE7_IN_PU,
491
		PE6_FN, PE6_OUT, PE6_IN, PE6_IN_PU,
492
		PE5_FN, PE5_OUT, PE5_IN, PE5_IN_PU,
493
		PE4_FN, PE4_OUT, PE4_IN, PE4_IN_PU,
494
		PE3_FN, PE3_OUT, PE3_IN, PE3_IN_PU,
495
		PE2_FN, PE2_OUT, PE2_IN, PE2_IN_PU,
496
		PE1_FN, PE1_OUT, PE1_IN, PE1_IN_PU,
497
		PE0_FN, PE0_OUT, PE0_IN, PE0_IN_PU,
498
		PF7_FN, PF7_OUT, PF7_IN, PF7_IN_PU,
499
		PF6_FN, PF6_OUT, PF6_IN, PF6_IN_PU,
500
		PF5_FN, PF5_OUT, PF5_IN, PF5_IN_PU,
501
		PF4_FN, PF4_OUT, PF4_IN, PF4_IN_PU,
502
		PF3_FN, PF3_OUT, PF3_IN, PF3_IN_PU,
503
		PF2_FN, PF2_OUT, PF2_IN, PF2_IN_PU,
504
		PF1_FN, PF1_OUT, PF1_IN, PF1_IN_PU,
505
		PF0_FN, PF0_OUT, PF0_IN, PF0_IN_PU, },
506
	},
507
	{ PINMUX_CFG_REG("PGHCR", 0xffc7000c, 32, 2) {
508
		PG7_FN, PG7_OUT, PG7_IN, PG7_IN_PU,
509
		PG6_FN, PG6_OUT, PG6_IN, PG6_IN_PU,
510
		PG5_FN, PG5_OUT, PG5_IN, PG5_IN_PU,
511
		PG4_FN, PG4_OUT, PG4_IN, PG4_IN_PU,
512
		PG3_FN, PG3_OUT, PG3_IN, PG3_IN_PU,
513
		PG2_FN, PG2_OUT, PG2_IN, PG2_IN_PU,
514
		PG1_FN, PG1_OUT, PG1_IN, PG1_IN_PU,
515
		PG0_FN, PG0_OUT, PG0_IN, PG0_IN_PU,
516
		0, 0, 0, 0,
517
		0, 0, 0, 0,
518
		PH5_FN, PH5_OUT, PH5_IN, PH5_IN_PU,
519
		PH4_FN, PH4_OUT, PH4_IN, PH4_IN_PU,
520
		PH3_FN, PH3_OUT, PH3_IN, PH3_IN_PU,
521
		PH2_FN, PH2_OUT, PH2_IN, PH2_IN_PU,
522
		PH1_FN, PH1_OUT, PH1_IN, PH1_IN_PU,
523
		PH0_FN, PH0_OUT, PH0_IN, PH0_IN_PU, },
524
	},
525
	{ },
526
};
527

528
static struct pinmux_data_reg shx3_pinmux_data_regs[] = {
529
	{ PINMUX_DATA_REG("PABDR", 0xffc70010, 32) {
530
		0, 0, 0, 0, 0, 0, 0, 0,
531
		PA7_DATA, PA6_DATA, PA5_DATA, PA4_DATA,
532
		PA3_DATA, PA2_DATA, PA1_DATA, PA0_DATA,
533
		0, 0, 0, 0, 0, 0, 0, 0,
534
		PB7_DATA, PB6_DATA, PB5_DATA, PB4_DATA,
535
		PB3_DATA, PB2_DATA, PB1_DATA, PB0_DATA, },
536
	},
537
	{ PINMUX_DATA_REG("PCDDR", 0xffc70014, 32) {
538
		0, 0, 0, 0, 0, 0, 0, 0,
539
		PC7_DATA, PC6_DATA, PC5_DATA, PC4_DATA,
540
		PC3_DATA, PC2_DATA, PC1_DATA, PC0_DATA,
541
		0, 0, 0, 0, 0, 0, 0, 0,
542
		PD7_DATA, PD6_DATA, PD5_DATA, PD4_DATA,
543
		PD3_DATA, PD2_DATA, PD1_DATA, PD0_DATA, },
544
	},
545
	{ PINMUX_DATA_REG("PEFDR", 0xffc70018, 32) {
546
		0, 0, 0, 0, 0, 0, 0, 0,
547
		PE7_DATA, PE6_DATA, PE5_DATA, PE4_DATA,
548
		PE3_DATA, PE2_DATA, PE1_DATA, PE0_DATA,
549
		0, 0, 0, 0, 0, 0, 0, 0,
550
		PF7_DATA, PF6_DATA, PF5_DATA, PF4_DATA,
551
		PF3_DATA, PF2_DATA, PF1_DATA, PF0_DATA, },
552
	},
553
	{ PINMUX_DATA_REG("PGHDR", 0xffc7001c, 32) {
554
		0, 0, 0, 0, 0, 0, 0, 0,
555
		PG7_DATA, PG6_DATA, PG5_DATA, PG4_DATA,
556
		PG3_DATA, PG2_DATA, PG1_DATA, PG0_DATA,
557
		0, 0, 0, 0, 0, 0, 0, 0,
558
		0, 0, PH5_DATA, PH4_DATA,
559
		PH3_DATA, PH2_DATA, PH1_DATA, PH0_DATA, },
560
	},
561
	{ },
562
};
563

564
static struct pinmux_info shx3_pinmux_info = {
565
	.name		= "shx3_pfc",
566
	.reserved_id	= PINMUX_RESERVED,
567
	.data		= { PINMUX_DATA_BEGIN,	   PINMUX_DATA_END },
568
	.input		= { PINMUX_INPUT_BEGIN,	   PINMUX_INPUT_END },
569
	.input_pu	= { PINMUX_INPUT_PULLUP_BEGIN,
570
			    PINMUX_INPUT_PULLUP_END },
571
	.output		= { PINMUX_OUTPUT_BEGIN,   PINMUX_OUTPUT_END },
572
	.mark		= { PINMUX_MARK_BEGIN,     PINMUX_MARK_END },
573
	.function	= { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
574
	.first_gpio	= GPIO_PA7,
575
	.last_gpio	= GPIO_FN_IRQOUT,
576
	.gpios		= shx3_pinmux_gpios,
577
	.gpio_data	= shx3_pinmux_data,
578
	.gpio_data_size	= ARRAY_SIZE(shx3_pinmux_data),
579
	.cfg_regs	= shx3_pinmux_config_regs,
580
	.data_regs	= shx3_pinmux_data_regs,
581
};
582

583
static int __init shx3_pinmux_setup(void)
584
{
585
	return register_pinmux(&shx3_pinmux_info);
586
}
587
arch_initcall(shx3_pinmux_setup);
588

589
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