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awilliam
GitHub Repository: awilliam/linux-vfio
 Path: blob/master/arch/sh/lib64/udivdi3.S
10817 views
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	.section	.text..SHmedia32,"ax"

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	.align	2

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	.global	__udivdi3

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__udivdi3:

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	shlri r3,1,r4

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	nsb r4,r22

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	shlld r3,r22,r6

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	shlri r6,49,r5

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	movi 0xffffffffffffbaf1,r21 /* .l shift count 17.  */

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	sub r21,r5,r1

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	mmulfx.w r1,r1,r4

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	mshflo.w r1,r63,r1

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	sub r63,r22,r20 // r63 == 64 % 64

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	mmulfx.w r5,r4,r4

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	pta large_divisor,tr0

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	addi r20,32,r9

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	msub.w r1,r4,r1

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	madd.w r1,r1,r1

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	mmulfx.w r1,r1,r4

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	shlri r6,32,r7

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	bgt/u r9,r63,tr0 // large_divisor

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	mmulfx.w r5,r4,r4

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	shlri r2,32+14,r19

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	addi r22,-31,r0

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	msub.w r1,r4,r1

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	mulu.l r1,r7,r4

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	addi r1,-3,r5

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	mulu.l r5,r19,r5

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	sub r63,r4,r4 // Negate to make sure r1 ends up <= 1/r2

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	shlri r4,2,r4 /* chop off leading %0000000000000000 001.00000000000 - or, as

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	                 the case may be, %0000000000000000 000.11111111111, still */

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	muls.l r1,r4,r4 /* leaving at least one sign bit.  */

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	mulu.l r5,r3,r8

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	mshalds.l r1,r21,r1

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	shari r4,26,r4

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	shlld r8,r0,r8

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	add r1,r4,r1 // 31 bit unsigned reciprocal now in r1 (msb equiv. 0.5)

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	sub r2,r8,r2

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	/* Can do second step of 64 : 32 div now, using r1 and the rest in r2.  */

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	shlri r2,22,r21

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	mulu.l r21,r1,r21

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	shlld r5,r0,r8

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	addi r20,30-22,r0

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	shlrd r21,r0,r21

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	mulu.l r21,r3,r5

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	add r8,r21,r8

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	mcmpgt.l r21,r63,r21 // See Note 1

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	addi r20,30,r0

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	mshfhi.l r63,r21,r21

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	sub r2,r5,r2

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	andc r2,r21,r2

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	/* small divisor: need a third divide step */

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	mulu.l r2,r1,r7

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	ptabs r18,tr0

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	addi r2,1,r2

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	shlrd r7,r0,r7

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	mulu.l r7,r3,r5

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	add r8,r7,r8

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	sub r2,r3,r2

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	cmpgt r2,r5,r5

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	add r8,r5,r2

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	/* could test r3 here to check for divide by zero.  */

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	blink tr0,r63

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large_divisor:

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	mmulfx.w r5,r4,r4

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	shlrd r2,r9,r25

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	shlri r25,32,r8

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	msub.w r1,r4,r1

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	mulu.l r1,r7,r4

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	addi r1,-3,r5

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	mulu.l r5,r8,r5

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	sub r63,r4,r4 // Negate to make sure r1 ends up <= 1/r2

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	shlri r4,2,r4 /* chop off leading %0000000000000000 001.00000000000 - or, as

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	                 the case may be, %0000000000000000 000.11111111111, still */

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	muls.l r1,r4,r4 /* leaving at least one sign bit.  */

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	shlri r5,14-1,r8

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	mulu.l r8,r7,r5

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	mshalds.l r1,r21,r1

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	shari r4,26,r4

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	add r1,r4,r1 // 31 bit unsigned reciprocal now in r1 (msb equiv. 0.5)

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	sub r25,r5,r25

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	/* Can do second step of 64 : 32 div now, using r1 and the rest in r25.  */

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	shlri r25,22,r21

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	mulu.l r21,r1,r21

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	pta no_lo_adj,tr0

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	addi r22,32,r0

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	shlri r21,40,r21

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	mulu.l r21,r7,r5

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	add r8,r21,r8

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	shlld r2,r0,r2

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	sub r25,r5,r25

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	bgtu/u r7,r25,tr0 // no_lo_adj

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	addi r8,1,r8

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	sub r25,r7,r25

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no_lo_adj:

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	mextr4 r2,r25,r2

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	/* large_divisor: only needs a few adjustments.  */

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	mulu.l r8,r6,r5

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	ptabs r18,tr0

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	/* bubble */

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	cmpgtu r5,r2,r5

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	sub r8,r5,r2

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	blink tr0,r63

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/* Note 1: To shift the result of the second divide stage so that the result

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   always fits into 32 bits, yet we still reduce the rest sufficiently

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   would require a lot of instructions to do the shifts just right.  Using

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   the full 64 bit shift result to multiply with the divisor would require

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   four extra instructions for the upper 32 bits (shift / mulu / shift / sub).

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   Fortunately, if the upper 32 bits of the shift result are nonzero, we

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   know that the rest after taking this partial result into account will

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   fit into 32 bits.  So we just clear the upper 32 bits of the rest if the

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   upper 32 bits of the partial result are nonzero.  */

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