Path: blob/master/arch/tile/include/asm/homecache.h
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/*1* Copyright 2010 Tilera Corporation. All Rights Reserved.2*3* This program is free software; you can redistribute it and/or4* modify it under the terms of the GNU General Public License5* as published by the Free Software Foundation, version 2.6*7* This program is distributed in the hope that it will be useful, but8* WITHOUT ANY WARRANTY; without even the implied warranty of9* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or10* NON INFRINGEMENT. See the GNU General Public License for11* more details.12*13* Handle issues around the Tile "home cache" model of coherence.14*/1516#ifndef _ASM_TILE_HOMECACHE_H17#define _ASM_TILE_HOMECACHE_H1819#include <asm/page.h>20#include <linux/cpumask.h>2122struct page;23struct task_struct;24struct vm_area_struct;25struct zone;2627/*28* Coherence point for the page is its memory controller.29* It is not present in any cache (L1 or L2).30*/31#define PAGE_HOME_UNCACHED -13233/*34* Is this page immutable (unwritable) and thus able to be cached more35* widely than would otherwise be possible? On tile64 this means we36* mark the PTE to cache locally; on tilepro it means we have "nc" set.37*/38#define PAGE_HOME_IMMUTABLE -23940/*41* Each cpu considers its own cache to be the home for the page,42* which makes it incoherent.43*/44#define PAGE_HOME_INCOHERENT -34546#if CHIP_HAS_CBOX_HOME_MAP()47/* Home for the page is distributed via hash-for-home. */48#define PAGE_HOME_HASH -449#endif5051/* Homing is unknown or unspecified. Not valid for page_home(). */52#define PAGE_HOME_UNKNOWN -55354/* Home on the current cpu. Not valid for page_home(). */55#define PAGE_HOME_HERE -65657/* Support wrapper to use instead of explicit hv_flush_remote(). */58extern void flush_remote(unsigned long cache_pfn, unsigned long cache_length,59const struct cpumask *cache_cpumask,60HV_VirtAddr tlb_va, unsigned long tlb_length,61unsigned long tlb_pgsize,62const struct cpumask *tlb_cpumask,63HV_Remote_ASID *asids, int asidcount);6465/* Set homing-related bits in a PTE (can also pass a pgprot_t). */66extern pte_t pte_set_home(pte_t pte, int home);6768/* Do a cache eviction on the specified cpus. */69extern void homecache_evict(const struct cpumask *mask);7071/*72* Change a kernel page's homecache. It must not be mapped in user space.73* If !CONFIG_HOMECACHE, only usable on LOWMEM, and can only be called when74* no other cpu can reference the page, and causes a full-chip cache/TLB flush.75*/76extern void homecache_change_page_home(struct page *, int order, int home);7778/*79* Flush a page out of whatever cache(s) it is in.80* This is more than just finv, since it properly handles waiting81* for the data to reach memory on tilepro, but it can be quite82* heavyweight, particularly on hash-for-home memory.83*/84extern void homecache_flush_cache(struct page *, int order);8586/*87* Allocate a page with the given GFP flags, home, and optionally88* node. These routines are actually just wrappers around the normal89* alloc_pages() / alloc_pages_node() functions, which set and clear90* a per-cpu variable to communicate with homecache_new_kernel_page().91* If !CONFIG_HOMECACHE, uses homecache_change_page_home().92*/93extern struct page *homecache_alloc_pages(gfp_t gfp_mask,94unsigned int order, int home);95extern struct page *homecache_alloc_pages_node(int nid, gfp_t gfp_mask,96unsigned int order, int home);97#define homecache_alloc_page(gfp_mask, home) \98homecache_alloc_pages(gfp_mask, 0, home)99100/*101* These routines are just pass-throughs to free_pages() when102* we support full homecaching. If !CONFIG_HOMECACHE, then these103* routines use homecache_change_page_home() to reset the home104* back to the default before returning the page to the allocator.105*/106void homecache_free_pages(unsigned long addr, unsigned int order);107#define homecache_free_page(page) \108homecache_free_pages((page), 0)109110111112/*113* Report the page home for LOWMEM pages by examining their kernel PTE,114* or for highmem pages as the default home.115*/116extern int page_home(struct page *);117118#define homecache_migrate_kthread() do {} while (0)119120#define homecache_kpte_lock() 0121#define homecache_kpte_unlock(flags) do {} while (0)122123124#endif /* _ASM_TILE_HOMECACHE_H */125126127