/*1* Copyright 2010 Tilera Corporation. All Rights Reserved.2*3* This program is free software; you can redistribute it and/or4* modify it under the terms of the GNU General Public License5* as published by the Free Software Foundation, version 2.6*7* This program is distributed in the hope that it will be useful, but8* WITHOUT ANY WARRANTY; without even the implied warranty of9* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or10* NON INFRINGEMENT. See the GNU General Public License for11* more details.12*/1314#ifndef _ASM_TILE_IRQ_H15#define _ASM_TILE_IRQ_H1617#include <linux/hardirq.h>1819/* The hypervisor interface provides 32 IRQs. */20#define NR_IRQS 322122/* IRQ numbers used for linux IPIs. */23#define IRQ_RESCHEDULE 12425#define irq_canonicalize(irq) (irq)2627void ack_bad_irq(unsigned int irq);2829/*30* Different ways of handling interrupts. Tile interrupts are always31* per-cpu; there is no global interrupt controller to implement32* enable/disable. Most onboard devices can send their interrupts to33* many tiles at the same time, and Tile-specific drivers know how to34* deal with this.35*36* However, generic devices (usually PCIE based, sometimes GPIO)37* expect that interrupts will fire on a single core at a time and38* that the irq can be enabled or disabled from any core at any time.39* We implement this by directing such interrupts to a single core.40*41* One added wrinkle is that PCI interrupts can be either42* hardware-cleared (legacy interrupts) or software cleared (MSI).43* Other generic device systems (GPIO) are always software-cleared.44*45* The enums below are used by drivers for onboard devices, including46* the internals of PCI root complex and GPIO. They allow the driver47* to tell the generic irq code what kind of interrupt is mapped to a48* particular IRQ number.49*/50enum {51/* per-cpu interrupt; use enable/disable_percpu_irq() to mask */52TILE_IRQ_PERCPU,53/* global interrupt, hardware responsible for clearing. */54TILE_IRQ_HW_CLEAR,55/* global interrupt, software responsible for clearing. */56TILE_IRQ_SW_CLEAR,57};585960/*61* Paravirtualized drivers should call this when they dynamically62* allocate a new IRQ or discover an IRQ that was pre-allocated by the63* hypervisor for use with their particular device. This gives the64* IRQ subsystem an opportunity to do interrupt-type-specific65* initialization.66*67* ISSUE: We should modify this API so that registering anything68* except percpu interrupts also requires providing callback methods69* for enabling and disabling the interrupt. This would allow the70* generic IRQ code to proxy enable/disable_irq() calls back into the71* PCI subsystem, which in turn could enable or disable the interrupt72* at the PCI shim.73*/74void tile_irq_activate(unsigned int irq, int tile_irq_type);7576/*77* For onboard, non-PCI (e.g. TILE_IRQ_PERCPU) devices, drivers know78* how to use enable/disable_percpu_irq() to manage interrupts on each79* core. We can't use the generic enable/disable_irq() because they80* use a single reference count per irq, rather than per cpu per irq.81*/82void enable_percpu_irq(unsigned int irq);83void disable_percpu_irq(unsigned int irq);848586void setup_irq_regs(void);8788#endif /* _ASM_TILE_IRQ_H */899091