Path: blob/master/arch/unicore32/include/mach/regs-dmac.h
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/*1* PKUnity Direct Memory Access Controller (DMAC)2*/34/*5* Interrupt Status Reg DMAC_ISR.6*/7#define DMAC_ISR (PKUNITY_DMAC_BASE + 0x0020)8/*9* Interrupt Transfer Complete Status Reg DMAC_ITCSR.10*/11#define DMAC_ITCSR (PKUNITY_DMAC_BASE + 0x0050)12/*13* Interrupt Transfer Complete Clear Reg DMAC_ITCCR.14*/15#define DMAC_ITCCR (PKUNITY_DMAC_BASE + 0x0060)16/*17* Interrupt Error Status Reg DMAC_IESR.18*/19#define DMAC_IESR (PKUNITY_DMAC_BASE + 0x0080)20/*21* Interrupt Error Clear Reg DMAC_IECR.22*/23#define DMAC_IECR (PKUNITY_DMAC_BASE + 0x0090)24/*25* Enable Channels Reg DMAC_ENCH.26*/27#define DMAC_ENCH (PKUNITY_DMAC_BASE + 0x00B0)2829/*30* DMA control reg. Space [byte]31*/32#define DMASp 0x000001003334/*35* Source Addr DMAC_SRCADDR(ch).36*/37#define DMAC_SRCADDR(ch) (PKUNITY_DMAC_BASE + (ch)*DMASp + 0x00)38/*39* Destination Addr DMAC_DESTADDR(ch).40*/41#define DMAC_DESTADDR(ch) (PKUNITY_DMAC_BASE + (ch)*DMASp + 0x04)42/*43* Control Reg DMAC_CONTROL(ch).44*/45#define DMAC_CONTROL(ch) (PKUNITY_DMAC_BASE + (ch)*DMASp + 0x0C)46/*47* Configuration Reg DMAC_CONFIG(ch).48*/49#define DMAC_CONFIG(ch) (PKUNITY_DMAC_BASE + (ch)*DMASp + 0x10)5051#define DMAC_IR_MASK FMASK(6, 0)52/*53* select channel (ch)54*/55#define DMAC_CHANNEL(ch) FIELD(1, 1, (ch))5657#define DMAC_CONTROL_SIZE_BYTE(v) (FIELD((v), 12, 14) | \58FIELD(0, 3, 9) | FIELD(0, 3, 6))59#define DMAC_CONTROL_SIZE_HWORD(v) (FIELD((v) >> 1, 12, 14) | \60FIELD(1, 3, 9) | FIELD(1, 3, 6))61#define DMAC_CONTROL_SIZE_WORD(v) (FIELD((v) >> 2, 12, 14) | \62FIELD(2, 3, 9) | FIELD(2, 3, 6))63#define DMAC_CONTROL_DI FIELD(1, 1, 13)64#define DMAC_CONTROL_SI FIELD(1, 1, 12)65#define DMAC_CONTROL_BURST_1BYTE (FIELD(0, 3, 3) | FIELD(0, 3, 0))66#define DMAC_CONTROL_BURST_4BYTE (FIELD(3, 3, 3) | FIELD(3, 3, 0))67#define DMAC_CONTROL_BURST_8BYTE (FIELD(5, 3, 3) | FIELD(5, 3, 0))68#define DMAC_CONTROL_BURST_16BYTE (FIELD(7, 3, 3) | FIELD(7, 3, 0))6970#define DMAC_CONFIG_UART0_WR (FIELD(2, 4, 11) | FIELD(1, 2, 1))71#define DMAC_CONFIG_UART0_RD (FIELD(2, 4, 7) | FIELD(2, 2, 1))72#define DMAC_CONFIG_UART1_WR (FIELD(3, 4, 11) | FIELD(1, 2, 1))73#define DMAC_CONFIG_UART1RD (FIELD(3, 4, 7) | FIELD(2, 2, 1))74#define DMAC_CONFIG_AC97WR (FIELD(4, 4, 11) | FIELD(1, 2, 1))75#define DMAC_CONFIG_AC97RD (FIELD(4, 4, 7) | FIELD(2, 2, 1))76#define DMAC_CONFIG_MMCWR (FIELD(7, 4, 11) | FIELD(1, 2, 1))77#define DMAC_CONFIG_MMCRD (FIELD(7, 4, 7) | FIELD(2, 2, 1))78#define DMAC_CONFIG_MASKITC FIELD(1, 1, 4)79#define DMAC_CONFIG_MASKIE FIELD(1, 1, 3)80#define DMAC_CONFIG_EN FIELD(1, 1, 0)818283