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awilliam
GitHub Repository: awilliam/linux-vfio
 Path: blob/master/arch/unicore32/include/mach/regs-ost.h
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/*

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 * PKUnity Operating System Timer (OST) Registers

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 */

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/*

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 * Match Reg 0 OST_OSMR0

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 */

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#define OST_OSMR0	(PKUNITY_OST_BASE + 0x0000)

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/*

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 * Match Reg 1 OST_OSMR1

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 */

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#define OST_OSMR1	(PKUNITY_OST_BASE + 0x0004)

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/*

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 * Match Reg 2 OST_OSMR2

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 */

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#define OST_OSMR2	(PKUNITY_OST_BASE + 0x0008)

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/*

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 * Match Reg 3 OST_OSMR3

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 */

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#define OST_OSMR3	(PKUNITY_OST_BASE + 0x000C)

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/*

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 * Counter Reg OST_OSCR

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 */

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#define OST_OSCR	(PKUNITY_OST_BASE + 0x0010)

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/*

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 * Status Reg OST_OSSR

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 */

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#define OST_OSSR	(PKUNITY_OST_BASE + 0x0014)

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/*

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 * Watchdog Enable Reg OST_OWER

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 */

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#define OST_OWER	(PKUNITY_OST_BASE + 0x0018)

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/*

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 * Interrupt Enable Reg OST_OIER

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 */

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#define OST_OIER	(PKUNITY_OST_BASE + 0x001C)

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/*

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 * PWM Pulse Width Control Reg OST_PWMPWCR

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 */

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#define OST_PWMPWCR	(PKUNITY_OST_BASE + 0x0080)

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/*

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 * PWM Duty Cycle Control Reg OST_PWMDCCR

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 */

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#define OST_PWMDCCR	(PKUNITY_OST_BASE + 0x0084)

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/*

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 * PWM Period Control Reg OST_PWMPCR

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 */

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#define OST_PWMPCR	(PKUNITY_OST_BASE + 0x0088)

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/*

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 * Match detected 0 OST_OSSR_M0

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 */

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#define OST_OSSR_M0		FIELD(1, 1, 0)

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/*

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 * Match detected 1 OST_OSSR_M1

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 */

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#define OST_OSSR_M1		FIELD(1, 1, 1)

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/*

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 * Match detected 2 OST_OSSR_M2

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 */

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#define OST_OSSR_M2		FIELD(1, 1, 2)

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/*

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 * Match detected 3 OST_OSSR_M3

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 */

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#define OST_OSSR_M3		FIELD(1, 1, 3)

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/*

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 * Interrupt enable 0 OST_OIER_E0

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 */

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#define OST_OIER_E0		FIELD(1, 1, 0)

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/*

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 * Interrupt enable 1 OST_OIER_E1

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 */

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#define OST_OIER_E1		FIELD(1, 1, 1)

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/*

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 * Interrupt enable 2 OST_OIER_E2

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 */

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#define OST_OIER_E2		FIELD(1, 1, 2)

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/*

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 * Interrupt enable 3 OST_OIER_E3

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 */

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#define OST_OIER_E3		FIELD(1, 1, 3)

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/*

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 * Watchdog Match Enable OST_OWER_WME

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 */

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#define OST_OWER_WME		FIELD(1, 1, 0)

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/*

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 * PWM Full Duty Cycle OST_PWMDCCR_FDCYCLE

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 */

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#define OST_PWMDCCR_FDCYCLE	FIELD(1, 1, 10)

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