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awilliam
GitHub Repository: awilliam/linux-vfio
 Path: blob/master/arch/unicore32/mm/proc-ucv2.S
10817 views
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/*

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 * linux/arch/unicore32/mm/proc-ucv2.S

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 *

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 * Code specific to PKUnity SoC and UniCore ISA

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 *

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 * Copyright (C) 2001-2010 GUAN Xue-tao

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 *

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 * This program is free software; you can redistribute it and/or modify

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 * it under the terms of the GNU General Public License version 2 as

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 * published by the Free Software Foundation.

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 */

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#include <linux/init.h>

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#include <linux/linkage.h>

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#include <asm/assembler.h>

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#include <asm/hwcap.h>

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#include <asm/pgtable-hwdef.h>

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#include <asm/pgtable.h>

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#include "proc-macros.S"

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ENTRY(cpu_proc_fin)

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	stm.w	(lr), [sp-]

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	mov	ip, #PSR_R_BIT | PSR_I_BIT | PRIV_MODE

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	mov.a	asr, ip

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	b.l	__cpuc_flush_kern_all

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	ldm.w	(pc), [sp]+

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/*

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 *	cpu_reset(loc)

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 *

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 *	Perform a soft reset of the system.  Put the CPU into the

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 *	same state as it would be if it had been reset, and branch

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 *	to what would be the reset vector.

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 *

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 *	- loc   - location to jump to for soft reset

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 */

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	.align	5

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ENTRY(cpu_reset)

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	mov	ip, #0

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	movc	p0.c5, ip, #28			@ Cache invalidate all

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	nop8

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	movc	p0.c6, ip, #6			@ TLB invalidate all

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	nop8

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	movc	ip, p0.c1, #0			@ ctrl register

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	or	ip, ip, #0x2000			@ vector base address

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	andn	ip, ip, #0x000f			@ ............idam

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	movc	p0.c1, ip, #0			@ disable caches and mmu

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	nop

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	mov	pc, r0				@ jump to loc

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	nop8

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/*

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 *	cpu_do_idle()

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 *

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 *	Idle the processor (eg, wait for interrupt).

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 *

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 *	IRQs are already disabled.

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 */

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ENTRY(cpu_do_idle)

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	mov	r0, #0				@ PCI address

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	.rept	8

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	ldw	r1, [r0]

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	.endr

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	mov	pc, lr

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ENTRY(cpu_dcache_clean_area)

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#ifndef CONFIG_CPU_DCACHE_LINE_DISABLE

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	csub.a	r1, #MAX_AREA_SIZE

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	bsg	101f

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	mov	r9, #PAGE_SZ

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	sub	r9, r9, #1			@ PAGE_MASK

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1:	va2pa	r0, r10, r11, r12, r13		@ r10 is PA

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	b	3f

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2:	cand.a	r0, r9

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	beq	1b

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3:	movc	p0.c5, r10, #11			@ clean D entry

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	nop8

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	add	r0, r0, #CACHE_LINESIZE

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	add	r10, r10, #CACHE_LINESIZE

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	sub.a	r1, r1, #CACHE_LINESIZE

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	bua	2b

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	mov	pc, lr

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#endif

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101:	mov	ip, #0

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	movc	p0.c5, ip, #10			@ Dcache clean all

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	nop8

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	mov	pc, lr

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/*

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 *	cpu_do_switch_mm(pgd_phys)

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 *

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 *	Set the translation table base pointer to be pgd_phys

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 *

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 *	- pgd_phys - physical address of new pgd

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 *

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 *	It is assumed that:

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 *	- we are not using split page tables

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 */

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	.align	5

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ENTRY(cpu_do_switch_mm)

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	movc	p0.c2, r0, #0			@ update page table ptr

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	nop8

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	movc	p0.c6, ip, #6			@ TLB invalidate all

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	nop8

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	mov	pc, lr

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/*

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 *	cpu_set_pte(ptep, pte)

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 *

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 *	Set a level 2 translation table entry.

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 *

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 *	- ptep  - pointer to level 2 translation table entry

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 *	- pte   - PTE value to store

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 */

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	.align	5

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ENTRY(cpu_set_pte)

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	stw	r1, [r0]

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#ifndef CONFIG_CPU_DCACHE_LINE_DISABLE

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	sub	r2, r0, #PAGE_OFFSET

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	movc	p0.c5, r2, #11				@ Dcache clean line

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	nop8

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#else

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	mov	ip, #0

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	movc	p0.c5, ip, #10				@ Dcache clean all

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	nop8

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	@dcacheline_flush	r0, r2, ip

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#endif

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	mov	pc, lr

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