Path: blob/master/arch/x86/kernel/cpu/mcheck/mce_amd.c
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/*1* (c) 2005, 2006 Advanced Micro Devices, Inc.2* Your use of this code is subject to the terms and conditions of the3* GNU general public license version 2. See "COPYING" or4* http://www.gnu.org/licenses/gpl.html5*6* Written by Jacob Shin - AMD, Inc.7*8* Support : [email protected]9*10* April 200611* - added support for AMD Family 0x10 processors12*13* All MC4_MISCi registers are shared between multi-cores14*/15#include <linux/interrupt.h>16#include <linux/notifier.h>17#include <linux/kobject.h>18#include <linux/percpu.h>19#include <linux/sysdev.h>20#include <linux/errno.h>21#include <linux/sched.h>22#include <linux/sysfs.h>23#include <linux/slab.h>24#include <linux/init.h>25#include <linux/cpu.h>26#include <linux/smp.h>2728#include <asm/apic.h>29#include <asm/idle.h>30#include <asm/mce.h>31#include <asm/msr.h>3233#define NR_BANKS 634#define NR_BLOCKS 935#define THRESHOLD_MAX 0xFFF36#define INT_TYPE_APIC 0x0002000037#define MASK_VALID_HI 0x8000000038#define MASK_CNTP_HI 0x4000000039#define MASK_LOCKED_HI 0x2000000040#define MASK_LVTOFF_HI 0x00F0000041#define MASK_COUNT_EN_HI 0x0008000042#define MASK_INT_TYPE_HI 0x0006000043#define MASK_OVERFLOW_HI 0x0001000044#define MASK_ERR_COUNT_HI 0x00000FFF45#define MASK_BLKPTR_LO 0xFF00000046#define MCG_XBLK_ADDR 0xC00004004748struct threshold_block {49unsigned int block;50unsigned int bank;51unsigned int cpu;52u32 address;53u16 interrupt_enable;54u16 threshold_limit;55struct kobject kobj;56struct list_head miscj;57};5859struct threshold_bank {60struct kobject *kobj;61struct threshold_block *blocks;62cpumask_var_t cpus;63};64static DEFINE_PER_CPU(struct threshold_bank * [NR_BANKS], threshold_banks);6566#ifdef CONFIG_SMP67static unsigned char shared_bank[NR_BANKS] = {680, 0, 0, 0, 169};70#endif7172static DEFINE_PER_CPU(unsigned char, bank_map); /* see which banks are on */7374static void amd_threshold_interrupt(void);7576/*77* CPU Initialization78*/7980struct thresh_restart {81struct threshold_block *b;82int reset;83int set_lvt_off;84int lvt_off;85u16 old_limit;86};8788static int lvt_off_valid(struct threshold_block *b, int apic, u32 lo, u32 hi)89{90int msr = (hi & MASK_LVTOFF_HI) >> 20;9192if (apic < 0) {93pr_err(FW_BUG "cpu %d, failed to setup threshold interrupt "94"for bank %d, block %d (MSR%08X=0x%x%08x)\n", b->cpu,95b->bank, b->block, b->address, hi, lo);96return 0;97}9899if (apic != msr) {100pr_err(FW_BUG "cpu %d, invalid threshold interrupt offset %d "101"for bank %d, block %d (MSR%08X=0x%x%08x)\n",102b->cpu, apic, b->bank, b->block, b->address, hi, lo);103return 0;104}105106return 1;107};108109/* must be called with correct cpu affinity */110/* Called via smp_call_function_single() */111static void threshold_restart_bank(void *_tr)112{113struct thresh_restart *tr = _tr;114u32 hi, lo;115116rdmsr(tr->b->address, lo, hi);117118if (tr->b->threshold_limit < (hi & THRESHOLD_MAX))119tr->reset = 1; /* limit cannot be lower than err count */120121if (tr->reset) { /* reset err count and overflow bit */122hi =123(hi & ~(MASK_ERR_COUNT_HI | MASK_OVERFLOW_HI)) |124(THRESHOLD_MAX - tr->b->threshold_limit);125} else if (tr->old_limit) { /* change limit w/o reset */126int new_count = (hi & THRESHOLD_MAX) +127(tr->old_limit - tr->b->threshold_limit);128129hi = (hi & ~MASK_ERR_COUNT_HI) |130(new_count & THRESHOLD_MAX);131}132133if (tr->set_lvt_off) {134if (lvt_off_valid(tr->b, tr->lvt_off, lo, hi)) {135/* set new lvt offset */136hi &= ~MASK_LVTOFF_HI;137hi |= tr->lvt_off << 20;138}139}140141tr->b->interrupt_enable ?142(hi = (hi & ~MASK_INT_TYPE_HI) | INT_TYPE_APIC) :143(hi &= ~MASK_INT_TYPE_HI);144145hi |= MASK_COUNT_EN_HI;146wrmsr(tr->b->address, lo, hi);147}148149static void mce_threshold_block_init(struct threshold_block *b, int offset)150{151struct thresh_restart tr = {152.b = b,153.set_lvt_off = 1,154.lvt_off = offset,155};156157b->threshold_limit = THRESHOLD_MAX;158threshold_restart_bank(&tr);159};160161static int setup_APIC_mce(int reserved, int new)162{163if (reserved < 0 && !setup_APIC_eilvt(new, THRESHOLD_APIC_VECTOR,164APIC_EILVT_MSG_FIX, 0))165return new;166167return reserved;168}169170/* cpu init entry point, called from mce.c with preempt off */171void mce_amd_feature_init(struct cpuinfo_x86 *c)172{173struct threshold_block b;174unsigned int cpu = smp_processor_id();175u32 low = 0, high = 0, address = 0;176unsigned int bank, block;177int offset = -1;178179for (bank = 0; bank < NR_BANKS; ++bank) {180for (block = 0; block < NR_BLOCKS; ++block) {181if (block == 0)182address = MSR_IA32_MC0_MISC + bank * 4;183else if (block == 1) {184address = (low & MASK_BLKPTR_LO) >> 21;185if (!address)186break;187188address += MCG_XBLK_ADDR;189} else190++address;191192if (rdmsr_safe(address, &low, &high))193break;194195if (!(high & MASK_VALID_HI))196continue;197198if (!(high & MASK_CNTP_HI) ||199(high & MASK_LOCKED_HI))200continue;201202if (!block)203per_cpu(bank_map, cpu) |= (1 << bank);204#ifdef CONFIG_SMP205if (shared_bank[bank] && c->cpu_core_id)206break;207#endif208offset = setup_APIC_mce(offset,209(high & MASK_LVTOFF_HI) >> 20);210211memset(&b, 0, sizeof(b));212b.cpu = cpu;213b.bank = bank;214b.block = block;215b.address = address;216217mce_threshold_block_init(&b, offset);218mce_threshold_vector = amd_threshold_interrupt;219}220}221}222223/*224* APIC Interrupt Handler225*/226227/*228* threshold interrupt handler will service THRESHOLD_APIC_VECTOR.229* the interrupt goes off when error_count reaches threshold_limit.230* the handler will simply log mcelog w/ software defined bank number.231*/232static void amd_threshold_interrupt(void)233{234u32 low = 0, high = 0, address = 0;235unsigned int bank, block;236struct mce m;237238mce_setup(&m);239240/* assume first bank caused it */241for (bank = 0; bank < NR_BANKS; ++bank) {242if (!(per_cpu(bank_map, m.cpu) & (1 << bank)))243continue;244for (block = 0; block < NR_BLOCKS; ++block) {245if (block == 0) {246address = MSR_IA32_MC0_MISC + bank * 4;247} else if (block == 1) {248address = (low & MASK_BLKPTR_LO) >> 21;249if (!address)250break;251address += MCG_XBLK_ADDR;252} else {253++address;254}255256if (rdmsr_safe(address, &low, &high))257break;258259if (!(high & MASK_VALID_HI)) {260if (block)261continue;262else263break;264}265266if (!(high & MASK_CNTP_HI) ||267(high & MASK_LOCKED_HI))268continue;269270/*271* Log the machine check that caused the threshold272* event.273*/274machine_check_poll(MCP_TIMESTAMP,275&__get_cpu_var(mce_poll_banks));276277if (high & MASK_OVERFLOW_HI) {278rdmsrl(address, m.misc);279rdmsrl(MSR_IA32_MC0_STATUS + bank * 4,280m.status);281m.bank = K8_MCE_THRESHOLD_BASE282+ bank * NR_BLOCKS283+ block;284mce_log(&m);285return;286}287}288}289}290291/*292* Sysfs Interface293*/294295struct threshold_attr {296struct attribute attr;297ssize_t (*show) (struct threshold_block *, char *);298ssize_t (*store) (struct threshold_block *, const char *, size_t count);299};300301#define SHOW_FIELDS(name) \302static ssize_t show_ ## name(struct threshold_block *b, char *buf) \303{ \304return sprintf(buf, "%lx\n", (unsigned long) b->name); \305}306SHOW_FIELDS(interrupt_enable)307SHOW_FIELDS(threshold_limit)308309static ssize_t310store_interrupt_enable(struct threshold_block *b, const char *buf, size_t size)311{312struct thresh_restart tr;313unsigned long new;314315if (strict_strtoul(buf, 0, &new) < 0)316return -EINVAL;317318b->interrupt_enable = !!new;319320memset(&tr, 0, sizeof(tr));321tr.b = b;322323smp_call_function_single(b->cpu, threshold_restart_bank, &tr, 1);324325return size;326}327328static ssize_t329store_threshold_limit(struct threshold_block *b, const char *buf, size_t size)330{331struct thresh_restart tr;332unsigned long new;333334if (strict_strtoul(buf, 0, &new) < 0)335return -EINVAL;336337if (new > THRESHOLD_MAX)338new = THRESHOLD_MAX;339if (new < 1)340new = 1;341342memset(&tr, 0, sizeof(tr));343tr.old_limit = b->threshold_limit;344b->threshold_limit = new;345tr.b = b;346347smp_call_function_single(b->cpu, threshold_restart_bank, &tr, 1);348349return size;350}351352struct threshold_block_cross_cpu {353struct threshold_block *tb;354long retval;355};356357static void local_error_count_handler(void *_tbcc)358{359struct threshold_block_cross_cpu *tbcc = _tbcc;360struct threshold_block *b = tbcc->tb;361u32 low, high;362363rdmsr(b->address, low, high);364tbcc->retval = (high & 0xFFF) - (THRESHOLD_MAX - b->threshold_limit);365}366367static ssize_t show_error_count(struct threshold_block *b, char *buf)368{369struct threshold_block_cross_cpu tbcc = { .tb = b, };370371smp_call_function_single(b->cpu, local_error_count_handler, &tbcc, 1);372return sprintf(buf, "%lx\n", tbcc.retval);373}374375static ssize_t store_error_count(struct threshold_block *b,376const char *buf, size_t count)377{378struct thresh_restart tr = { .b = b, .reset = 1, .old_limit = 0 };379380smp_call_function_single(b->cpu, threshold_restart_bank, &tr, 1);381return 1;382}383384#define RW_ATTR(val) \385static struct threshold_attr val = { \386.attr = {.name = __stringify(val), .mode = 0644 }, \387.show = show_## val, \388.store = store_## val, \389};390391RW_ATTR(interrupt_enable);392RW_ATTR(threshold_limit);393RW_ATTR(error_count);394395static struct attribute *default_attrs[] = {396&interrupt_enable.attr,397&threshold_limit.attr,398&error_count.attr,399NULL400};401402#define to_block(k) container_of(k, struct threshold_block, kobj)403#define to_attr(a) container_of(a, struct threshold_attr, attr)404405static ssize_t show(struct kobject *kobj, struct attribute *attr, char *buf)406{407struct threshold_block *b = to_block(kobj);408struct threshold_attr *a = to_attr(attr);409ssize_t ret;410411ret = a->show ? a->show(b, buf) : -EIO;412413return ret;414}415416static ssize_t store(struct kobject *kobj, struct attribute *attr,417const char *buf, size_t count)418{419struct threshold_block *b = to_block(kobj);420struct threshold_attr *a = to_attr(attr);421ssize_t ret;422423ret = a->store ? a->store(b, buf, count) : -EIO;424425return ret;426}427428static const struct sysfs_ops threshold_ops = {429.show = show,430.store = store,431};432433static struct kobj_type threshold_ktype = {434.sysfs_ops = &threshold_ops,435.default_attrs = default_attrs,436};437438static __cpuinit int allocate_threshold_blocks(unsigned int cpu,439unsigned int bank,440unsigned int block,441u32 address)442{443struct threshold_block *b = NULL;444u32 low, high;445int err;446447if ((bank >= NR_BANKS) || (block >= NR_BLOCKS))448return 0;449450if (rdmsr_safe_on_cpu(cpu, address, &low, &high))451return 0;452453if (!(high & MASK_VALID_HI)) {454if (block)455goto recurse;456else457return 0;458}459460if (!(high & MASK_CNTP_HI) ||461(high & MASK_LOCKED_HI))462goto recurse;463464b = kzalloc(sizeof(struct threshold_block), GFP_KERNEL);465if (!b)466return -ENOMEM;467468b->block = block;469b->bank = bank;470b->cpu = cpu;471b->address = address;472b->interrupt_enable = 0;473b->threshold_limit = THRESHOLD_MAX;474475INIT_LIST_HEAD(&b->miscj);476477if (per_cpu(threshold_banks, cpu)[bank]->blocks) {478list_add(&b->miscj,479&per_cpu(threshold_banks, cpu)[bank]->blocks->miscj);480} else {481per_cpu(threshold_banks, cpu)[bank]->blocks = b;482}483484err = kobject_init_and_add(&b->kobj, &threshold_ktype,485per_cpu(threshold_banks, cpu)[bank]->kobj,486"misc%i", block);487if (err)488goto out_free;489recurse:490if (!block) {491address = (low & MASK_BLKPTR_LO) >> 21;492if (!address)493return 0;494address += MCG_XBLK_ADDR;495} else {496++address;497}498499err = allocate_threshold_blocks(cpu, bank, ++block, address);500if (err)501goto out_free;502503if (b)504kobject_uevent(&b->kobj, KOBJ_ADD);505506return err;507508out_free:509if (b) {510kobject_put(&b->kobj);511list_del(&b->miscj);512kfree(b);513}514return err;515}516517static __cpuinit long518local_allocate_threshold_blocks(int cpu, unsigned int bank)519{520return allocate_threshold_blocks(cpu, bank, 0,521MSR_IA32_MC0_MISC + bank * 4);522}523524/* symlinks sibling shared banks to first core. first core owns dir/files. */525static __cpuinit int threshold_create_bank(unsigned int cpu, unsigned int bank)526{527int i, err = 0;528struct threshold_bank *b = NULL;529char name[32];530531sprintf(name, "threshold_bank%i", bank);532533#ifdef CONFIG_SMP534if (cpu_data(cpu).cpu_core_id && shared_bank[bank]) { /* symlink */535i = cpumask_first(cpu_llc_shared_mask(cpu));536537/* first core not up yet */538if (cpu_data(i).cpu_core_id)539goto out;540541/* already linked */542if (per_cpu(threshold_banks, cpu)[bank])543goto out;544545b = per_cpu(threshold_banks, i)[bank];546547if (!b)548goto out;549550err = sysfs_create_link(&per_cpu(mce_dev, cpu).kobj,551b->kobj, name);552if (err)553goto out;554555cpumask_copy(b->cpus, cpu_llc_shared_mask(cpu));556per_cpu(threshold_banks, cpu)[bank] = b;557558goto out;559}560#endif561562b = kzalloc(sizeof(struct threshold_bank), GFP_KERNEL);563if (!b) {564err = -ENOMEM;565goto out;566}567if (!zalloc_cpumask_var(&b->cpus, GFP_KERNEL)) {568kfree(b);569err = -ENOMEM;570goto out;571}572573b->kobj = kobject_create_and_add(name, &per_cpu(mce_dev, cpu).kobj);574if (!b->kobj)575goto out_free;576577#ifndef CONFIG_SMP578cpumask_setall(b->cpus);579#else580cpumask_set_cpu(cpu, b->cpus);581#endif582583per_cpu(threshold_banks, cpu)[bank] = b;584585err = local_allocate_threshold_blocks(cpu, bank);586if (err)587goto out_free;588589for_each_cpu(i, b->cpus) {590if (i == cpu)591continue;592593err = sysfs_create_link(&per_cpu(mce_dev, i).kobj,594b->kobj, name);595if (err)596goto out;597598per_cpu(threshold_banks, i)[bank] = b;599}600601goto out;602603out_free:604per_cpu(threshold_banks, cpu)[bank] = NULL;605free_cpumask_var(b->cpus);606kfree(b);607out:608return err;609}610611/* create dir/files for all valid threshold banks */612static __cpuinit int threshold_create_device(unsigned int cpu)613{614unsigned int bank;615int err = 0;616617for (bank = 0; bank < NR_BANKS; ++bank) {618if (!(per_cpu(bank_map, cpu) & (1 << bank)))619continue;620err = threshold_create_bank(cpu, bank);621if (err)622return err;623}624625return err;626}627628/*629* let's be hotplug friendly.630* in case of multiple core processors, the first core always takes ownership631* of shared sysfs dir/files, and rest of the cores will be symlinked to it.632*/633634static void deallocate_threshold_block(unsigned int cpu,635unsigned int bank)636{637struct threshold_block *pos = NULL;638struct threshold_block *tmp = NULL;639struct threshold_bank *head = per_cpu(threshold_banks, cpu)[bank];640641if (!head)642return;643644list_for_each_entry_safe(pos, tmp, &head->blocks->miscj, miscj) {645kobject_put(&pos->kobj);646list_del(&pos->miscj);647kfree(pos);648}649650kfree(per_cpu(threshold_banks, cpu)[bank]->blocks);651per_cpu(threshold_banks, cpu)[bank]->blocks = NULL;652}653654static void threshold_remove_bank(unsigned int cpu, int bank)655{656struct threshold_bank *b;657char name[32];658int i = 0;659660b = per_cpu(threshold_banks, cpu)[bank];661if (!b)662return;663if (!b->blocks)664goto free_out;665666sprintf(name, "threshold_bank%i", bank);667668#ifdef CONFIG_SMP669/* sibling symlink */670if (shared_bank[bank] && b->blocks->cpu != cpu) {671sysfs_remove_link(&per_cpu(mce_dev, cpu).kobj, name);672per_cpu(threshold_banks, cpu)[bank] = NULL;673674return;675}676#endif677678/* remove all sibling symlinks before unregistering */679for_each_cpu(i, b->cpus) {680if (i == cpu)681continue;682683sysfs_remove_link(&per_cpu(mce_dev, i).kobj, name);684per_cpu(threshold_banks, i)[bank] = NULL;685}686687deallocate_threshold_block(cpu, bank);688689free_out:690kobject_del(b->kobj);691kobject_put(b->kobj);692free_cpumask_var(b->cpus);693kfree(b);694per_cpu(threshold_banks, cpu)[bank] = NULL;695}696697static void threshold_remove_device(unsigned int cpu)698{699unsigned int bank;700701for (bank = 0; bank < NR_BANKS; ++bank) {702if (!(per_cpu(bank_map, cpu) & (1 << bank)))703continue;704threshold_remove_bank(cpu, bank);705}706}707708/* get notified when a cpu comes on/off */709static void __cpuinit710amd_64_threshold_cpu_callback(unsigned long action, unsigned int cpu)711{712switch (action) {713case CPU_ONLINE:714case CPU_ONLINE_FROZEN:715threshold_create_device(cpu);716break;717case CPU_DEAD:718case CPU_DEAD_FROZEN:719threshold_remove_device(cpu);720break;721default:722break;723}724}725726static __init int threshold_init_device(void)727{728unsigned lcpu = 0;729730/* to hit CPUs online before the notifier is up */731for_each_online_cpu(lcpu) {732int err = threshold_create_device(lcpu);733734if (err)735return err;736}737threshold_cpu_callback = amd_64_threshold_cpu_callback;738739return 0;740}741device_initcall(threshold_init_device);742743744