Path: blob/master/arch/x86/kernel/cpu/mtrr/cleanup.c
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/*1* MTRR (Memory Type Range Register) cleanup2*3* Copyright (C) 2009 Yinghai Lu4*5* This library is free software; you can redistribute it and/or6* modify it under the terms of the GNU Library General Public7* License as published by the Free Software Foundation; either8* version 2 of the License, or (at your option) any later version.9*10* This library is distributed in the hope that it will be useful,11* but WITHOUT ANY WARRANTY; without even the implied warranty of12* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU13* Library General Public License for more details.14*15* You should have received a copy of the GNU Library General Public16* License along with this library; if not, write to the Free17* Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.18*/19#include <linux/module.h>20#include <linux/init.h>21#include <linux/pci.h>22#include <linux/smp.h>23#include <linux/cpu.h>24#include <linux/mutex.h>25#include <linux/uaccess.h>26#include <linux/kvm_para.h>27#include <linux/range.h>2829#include <asm/processor.h>30#include <asm/e820.h>31#include <asm/mtrr.h>32#include <asm/msr.h>3334#include "mtrr.h"3536struct var_mtrr_range_state {37unsigned long base_pfn;38unsigned long size_pfn;39mtrr_type type;40};4142struct var_mtrr_state {43unsigned long range_startk;44unsigned long range_sizek;45unsigned long chunk_sizek;46unsigned long gran_sizek;47unsigned int reg;48};4950/* Should be related to MTRR_VAR_RANGES nums */51#define RANGE_NUM 2565253static struct range __initdata range[RANGE_NUM];54static int __initdata nr_range;5556static struct var_mtrr_range_state __initdata range_state[RANGE_NUM];5758static int __initdata debug_print;59#define Dprintk(x...) do { if (debug_print) printk(KERN_DEBUG x); } while (0)6061#define BIOS_BUG_MSG KERN_WARNING \62"WARNING: BIOS bug: VAR MTRR %d contains strange UC entry under 1M, check with your system vendor!\n"6364static int __init65x86_get_mtrr_mem_range(struct range *range, int nr_range,66unsigned long extra_remove_base,67unsigned long extra_remove_size)68{69unsigned long base, size;70mtrr_type type;71int i;7273for (i = 0; i < num_var_ranges; i++) {74type = range_state[i].type;75if (type != MTRR_TYPE_WRBACK)76continue;77base = range_state[i].base_pfn;78size = range_state[i].size_pfn;79nr_range = add_range_with_merge(range, RANGE_NUM, nr_range,80base, base + size);81}82if (debug_print) {83printk(KERN_DEBUG "After WB checking\n");84for (i = 0; i < nr_range; i++)85printk(KERN_DEBUG "MTRR MAP PFN: %016llx - %016llx\n",86range[i].start, range[i].end);87}8889/* Take out UC ranges: */90for (i = 0; i < num_var_ranges; i++) {91type = range_state[i].type;92if (type != MTRR_TYPE_UNCACHABLE &&93type != MTRR_TYPE_WRPROT)94continue;95size = range_state[i].size_pfn;96if (!size)97continue;98base = range_state[i].base_pfn;99if (base < (1<<(20-PAGE_SHIFT)) && mtrr_state.have_fixed &&100(mtrr_state.enabled & 1)) {101/* Var MTRR contains UC entry below 1M? Skip it: */102printk(BIOS_BUG_MSG, i);103if (base + size <= (1<<(20-PAGE_SHIFT)))104continue;105size -= (1<<(20-PAGE_SHIFT)) - base;106base = 1<<(20-PAGE_SHIFT);107}108subtract_range(range, RANGE_NUM, base, base + size);109}110if (extra_remove_size)111subtract_range(range, RANGE_NUM, extra_remove_base,112extra_remove_base + extra_remove_size);113114if (debug_print) {115printk(KERN_DEBUG "After UC checking\n");116for (i = 0; i < RANGE_NUM; i++) {117if (!range[i].end)118continue;119printk(KERN_DEBUG "MTRR MAP PFN: %016llx - %016llx\n",120range[i].start, range[i].end);121}122}123124/* sort the ranges */125nr_range = clean_sort_range(range, RANGE_NUM);126if (debug_print) {127printk(KERN_DEBUG "After sorting\n");128for (i = 0; i < nr_range; i++)129printk(KERN_DEBUG "MTRR MAP PFN: %016llx - %016llx\n",130range[i].start, range[i].end);131}132133return nr_range;134}135136#ifdef CONFIG_MTRR_SANITIZER137138static unsigned long __init sum_ranges(struct range *range, int nr_range)139{140unsigned long sum = 0;141int i;142143for (i = 0; i < nr_range; i++)144sum += range[i].end - range[i].start;145146return sum;147}148149static int enable_mtrr_cleanup __initdata =150CONFIG_MTRR_SANITIZER_ENABLE_DEFAULT;151152static int __init disable_mtrr_cleanup_setup(char *str)153{154enable_mtrr_cleanup = 0;155return 0;156}157early_param("disable_mtrr_cleanup", disable_mtrr_cleanup_setup);158159static int __init enable_mtrr_cleanup_setup(char *str)160{161enable_mtrr_cleanup = 1;162return 0;163}164early_param("enable_mtrr_cleanup", enable_mtrr_cleanup_setup);165166static int __init mtrr_cleanup_debug_setup(char *str)167{168debug_print = 1;169return 0;170}171early_param("mtrr_cleanup_debug", mtrr_cleanup_debug_setup);172173static void __init174set_var_mtrr(unsigned int reg, unsigned long basek, unsigned long sizek,175unsigned char type, unsigned int address_bits)176{177u32 base_lo, base_hi, mask_lo, mask_hi;178u64 base, mask;179180if (!sizek) {181fill_mtrr_var_range(reg, 0, 0, 0, 0);182return;183}184185mask = (1ULL << address_bits) - 1;186mask &= ~((((u64)sizek) << 10) - 1);187188base = ((u64)basek) << 10;189190base |= type;191mask |= 0x800;192193base_lo = base & ((1ULL<<32) - 1);194base_hi = base >> 32;195196mask_lo = mask & ((1ULL<<32) - 1);197mask_hi = mask >> 32;198199fill_mtrr_var_range(reg, base_lo, base_hi, mask_lo, mask_hi);200}201202static void __init203save_var_mtrr(unsigned int reg, unsigned long basek, unsigned long sizek,204unsigned char type)205{206range_state[reg].base_pfn = basek >> (PAGE_SHIFT - 10);207range_state[reg].size_pfn = sizek >> (PAGE_SHIFT - 10);208range_state[reg].type = type;209}210211static void __init set_var_mtrr_all(unsigned int address_bits)212{213unsigned long basek, sizek;214unsigned char type;215unsigned int reg;216217for (reg = 0; reg < num_var_ranges; reg++) {218basek = range_state[reg].base_pfn << (PAGE_SHIFT - 10);219sizek = range_state[reg].size_pfn << (PAGE_SHIFT - 10);220type = range_state[reg].type;221222set_var_mtrr(reg, basek, sizek, type, address_bits);223}224}225226static unsigned long to_size_factor(unsigned long sizek, char *factorp)227{228unsigned long base = sizek;229char factor;230231if (base & ((1<<10) - 1)) {232/* Not MB-aligned: */233factor = 'K';234} else if (base & ((1<<20) - 1)) {235factor = 'M';236base >>= 10;237} else {238factor = 'G';239base >>= 20;240}241242*factorp = factor;243244return base;245}246247static unsigned int __init248range_to_mtrr(unsigned int reg, unsigned long range_startk,249unsigned long range_sizek, unsigned char type)250{251if (!range_sizek || (reg >= num_var_ranges))252return reg;253254while (range_sizek) {255unsigned long max_align, align;256unsigned long sizek;257258/* Compute the maximum size with which we can make a range: */259if (range_startk)260max_align = ffs(range_startk) - 1;261else262max_align = 32;263264align = fls(range_sizek) - 1;265if (align > max_align)266align = max_align;267268sizek = 1 << align;269if (debug_print) {270char start_factor = 'K', size_factor = 'K';271unsigned long start_base, size_base;272273start_base = to_size_factor(range_startk, &start_factor);274size_base = to_size_factor(sizek, &size_factor);275276Dprintk("Setting variable MTRR %d, "277"base: %ld%cB, range: %ld%cB, type %s\n",278reg, start_base, start_factor,279size_base, size_factor,280(type == MTRR_TYPE_UNCACHABLE) ? "UC" :281((type == MTRR_TYPE_WRBACK) ? "WB" : "Other")282);283}284save_var_mtrr(reg++, range_startk, sizek, type);285range_startk += sizek;286range_sizek -= sizek;287if (reg >= num_var_ranges)288break;289}290return reg;291}292293static unsigned __init294range_to_mtrr_with_hole(struct var_mtrr_state *state, unsigned long basek,295unsigned long sizek)296{297unsigned long hole_basek, hole_sizek;298unsigned long second_basek, second_sizek;299unsigned long range0_basek, range0_sizek;300unsigned long range_basek, range_sizek;301unsigned long chunk_sizek;302unsigned long gran_sizek;303304hole_basek = 0;305hole_sizek = 0;306second_basek = 0;307second_sizek = 0;308chunk_sizek = state->chunk_sizek;309gran_sizek = state->gran_sizek;310311/* Align with gran size, prevent small block used up MTRRs: */312range_basek = ALIGN(state->range_startk, gran_sizek);313if ((range_basek > basek) && basek)314return second_sizek;315316state->range_sizek -= (range_basek - state->range_startk);317range_sizek = ALIGN(state->range_sizek, gran_sizek);318319while (range_sizek > state->range_sizek) {320range_sizek -= gran_sizek;321if (!range_sizek)322return 0;323}324state->range_sizek = range_sizek;325326/* Try to append some small hole: */327range0_basek = state->range_startk;328range0_sizek = ALIGN(state->range_sizek, chunk_sizek);329330/* No increase: */331if (range0_sizek == state->range_sizek) {332Dprintk("rangeX: %016lx - %016lx\n",333range0_basek<<10,334(range0_basek + state->range_sizek)<<10);335state->reg = range_to_mtrr(state->reg, range0_basek,336state->range_sizek, MTRR_TYPE_WRBACK);337return 0;338}339340/* Only cut back when it is not the last: */341if (sizek) {342while (range0_basek + range0_sizek > (basek + sizek)) {343if (range0_sizek >= chunk_sizek)344range0_sizek -= chunk_sizek;345else346range0_sizek = 0;347348if (!range0_sizek)349break;350}351}352353second_try:354range_basek = range0_basek + range0_sizek;355356/* One hole in the middle: */357if (range_basek > basek && range_basek <= (basek + sizek))358second_sizek = range_basek - basek;359360if (range0_sizek > state->range_sizek) {361362/* One hole in middle or at the end: */363hole_sizek = range0_sizek - state->range_sizek - second_sizek;364365/* Hole size should be less than half of range0 size: */366if (hole_sizek >= (range0_sizek >> 1) &&367range0_sizek >= chunk_sizek) {368range0_sizek -= chunk_sizek;369second_sizek = 0;370hole_sizek = 0;371372goto second_try;373}374}375376if (range0_sizek) {377Dprintk("range0: %016lx - %016lx\n",378range0_basek<<10,379(range0_basek + range0_sizek)<<10);380state->reg = range_to_mtrr(state->reg, range0_basek,381range0_sizek, MTRR_TYPE_WRBACK);382}383384if (range0_sizek < state->range_sizek) {385/* Need to handle left over range: */386range_sizek = state->range_sizek - range0_sizek;387388Dprintk("range: %016lx - %016lx\n",389range_basek<<10,390(range_basek + range_sizek)<<10);391392state->reg = range_to_mtrr(state->reg, range_basek,393range_sizek, MTRR_TYPE_WRBACK);394}395396if (hole_sizek) {397hole_basek = range_basek - hole_sizek - second_sizek;398Dprintk("hole: %016lx - %016lx\n",399hole_basek<<10,400(hole_basek + hole_sizek)<<10);401state->reg = range_to_mtrr(state->reg, hole_basek,402hole_sizek, MTRR_TYPE_UNCACHABLE);403}404405return second_sizek;406}407408static void __init409set_var_mtrr_range(struct var_mtrr_state *state, unsigned long base_pfn,410unsigned long size_pfn)411{412unsigned long basek, sizek;413unsigned long second_sizek = 0;414415if (state->reg >= num_var_ranges)416return;417418basek = base_pfn << (PAGE_SHIFT - 10);419sizek = size_pfn << (PAGE_SHIFT - 10);420421/* See if I can merge with the last range: */422if ((basek <= 1024) ||423(state->range_startk + state->range_sizek == basek)) {424unsigned long endk = basek + sizek;425state->range_sizek = endk - state->range_startk;426return;427}428/* Write the range mtrrs: */429if (state->range_sizek != 0)430second_sizek = range_to_mtrr_with_hole(state, basek, sizek);431432/* Allocate an msr: */433state->range_startk = basek + second_sizek;434state->range_sizek = sizek - second_sizek;435}436437/* Mininum size of mtrr block that can take hole: */438static u64 mtrr_chunk_size __initdata = (256ULL<<20);439440static int __init parse_mtrr_chunk_size_opt(char *p)441{442if (!p)443return -EINVAL;444mtrr_chunk_size = memparse(p, &p);445return 0;446}447early_param("mtrr_chunk_size", parse_mtrr_chunk_size_opt);448449/* Granularity of mtrr of block: */450static u64 mtrr_gran_size __initdata;451452static int __init parse_mtrr_gran_size_opt(char *p)453{454if (!p)455return -EINVAL;456mtrr_gran_size = memparse(p, &p);457return 0;458}459early_param("mtrr_gran_size", parse_mtrr_gran_size_opt);460461static unsigned long nr_mtrr_spare_reg __initdata =462CONFIG_MTRR_SANITIZER_SPARE_REG_NR_DEFAULT;463464static int __init parse_mtrr_spare_reg(char *arg)465{466if (arg)467nr_mtrr_spare_reg = simple_strtoul(arg, NULL, 0);468return 0;469}470early_param("mtrr_spare_reg_nr", parse_mtrr_spare_reg);471472static int __init473x86_setup_var_mtrrs(struct range *range, int nr_range,474u64 chunk_size, u64 gran_size)475{476struct var_mtrr_state var_state;477int num_reg;478int i;479480var_state.range_startk = 0;481var_state.range_sizek = 0;482var_state.reg = 0;483var_state.chunk_sizek = chunk_size >> 10;484var_state.gran_sizek = gran_size >> 10;485486memset(range_state, 0, sizeof(range_state));487488/* Write the range: */489for (i = 0; i < nr_range; i++) {490set_var_mtrr_range(&var_state, range[i].start,491range[i].end - range[i].start);492}493494/* Write the last range: */495if (var_state.range_sizek != 0)496range_to_mtrr_with_hole(&var_state, 0, 0);497498num_reg = var_state.reg;499/* Clear out the extra MTRR's: */500while (var_state.reg < num_var_ranges) {501save_var_mtrr(var_state.reg, 0, 0, 0);502var_state.reg++;503}504505return num_reg;506}507508struct mtrr_cleanup_result {509unsigned long gran_sizek;510unsigned long chunk_sizek;511unsigned long lose_cover_sizek;512unsigned int num_reg;513int bad;514};515516/*517* gran_size: 64K, 128K, 256K, 512K, 1M, 2M, ..., 2G518* chunk size: gran_size, ..., 2G519* so we need (1+16)*8520*/521#define NUM_RESULT 136522#define PSHIFT (PAGE_SHIFT - 10)523524static struct mtrr_cleanup_result __initdata result[NUM_RESULT];525static unsigned long __initdata min_loss_pfn[RANGE_NUM];526527static void __init print_out_mtrr_range_state(void)528{529char start_factor = 'K', size_factor = 'K';530unsigned long start_base, size_base;531mtrr_type type;532int i;533534for (i = 0; i < num_var_ranges; i++) {535536size_base = range_state[i].size_pfn << (PAGE_SHIFT - 10);537if (!size_base)538continue;539540size_base = to_size_factor(size_base, &size_factor),541start_base = range_state[i].base_pfn << (PAGE_SHIFT - 10);542start_base = to_size_factor(start_base, &start_factor),543type = range_state[i].type;544545printk(KERN_DEBUG "reg %d, base: %ld%cB, range: %ld%cB, type %s\n",546i, start_base, start_factor,547size_base, size_factor,548(type == MTRR_TYPE_UNCACHABLE) ? "UC" :549((type == MTRR_TYPE_WRPROT) ? "WP" :550((type == MTRR_TYPE_WRBACK) ? "WB" : "Other"))551);552}553}554555static int __init mtrr_need_cleanup(void)556{557int i;558mtrr_type type;559unsigned long size;560/* Extra one for all 0: */561int num[MTRR_NUM_TYPES + 1];562563/* Check entries number: */564memset(num, 0, sizeof(num));565for (i = 0; i < num_var_ranges; i++) {566type = range_state[i].type;567size = range_state[i].size_pfn;568if (type >= MTRR_NUM_TYPES)569continue;570if (!size)571type = MTRR_NUM_TYPES;572num[type]++;573}574575/* Check if we got UC entries: */576if (!num[MTRR_TYPE_UNCACHABLE])577return 0;578579/* Check if we only had WB and UC */580if (num[MTRR_TYPE_WRBACK] + num[MTRR_TYPE_UNCACHABLE] !=581num_var_ranges - num[MTRR_NUM_TYPES])582return 0;583584return 1;585}586587static unsigned long __initdata range_sums;588589static void __init590mtrr_calc_range_state(u64 chunk_size, u64 gran_size,591unsigned long x_remove_base,592unsigned long x_remove_size, int i)593{594static struct range range_new[RANGE_NUM];595unsigned long range_sums_new;596static int nr_range_new;597int num_reg;598599/* Convert ranges to var ranges state: */600num_reg = x86_setup_var_mtrrs(range, nr_range, chunk_size, gran_size);601602/* We got new setting in range_state, check it: */603memset(range_new, 0, sizeof(range_new));604nr_range_new = x86_get_mtrr_mem_range(range_new, 0,605x_remove_base, x_remove_size);606range_sums_new = sum_ranges(range_new, nr_range_new);607608result[i].chunk_sizek = chunk_size >> 10;609result[i].gran_sizek = gran_size >> 10;610result[i].num_reg = num_reg;611612if (range_sums < range_sums_new) {613result[i].lose_cover_sizek = (range_sums_new - range_sums) << PSHIFT;614result[i].bad = 1;615} else {616result[i].lose_cover_sizek = (range_sums - range_sums_new) << PSHIFT;617}618619/* Double check it: */620if (!result[i].bad && !result[i].lose_cover_sizek) {621if (nr_range_new != nr_range || memcmp(range, range_new, sizeof(range)))622result[i].bad = 1;623}624625if (!result[i].bad && (range_sums - range_sums_new < min_loss_pfn[num_reg]))626min_loss_pfn[num_reg] = range_sums - range_sums_new;627}628629static void __init mtrr_print_out_one_result(int i)630{631unsigned long gran_base, chunk_base, lose_base;632char gran_factor, chunk_factor, lose_factor;633634gran_base = to_size_factor(result[i].gran_sizek, &gran_factor);635chunk_base = to_size_factor(result[i].chunk_sizek, &chunk_factor);636lose_base = to_size_factor(result[i].lose_cover_sizek, &lose_factor);637638pr_info("%sgran_size: %ld%c \tchunk_size: %ld%c \t",639result[i].bad ? "*BAD*" : " ",640gran_base, gran_factor, chunk_base, chunk_factor);641pr_cont("num_reg: %d \tlose cover RAM: %s%ld%c\n",642result[i].num_reg, result[i].bad ? "-" : "",643lose_base, lose_factor);644}645646static int __init mtrr_search_optimal_index(void)647{648int num_reg_good;649int index_good;650int i;651652if (nr_mtrr_spare_reg >= num_var_ranges)653nr_mtrr_spare_reg = num_var_ranges - 1;654655num_reg_good = -1;656for (i = num_var_ranges - nr_mtrr_spare_reg; i > 0; i--) {657if (!min_loss_pfn[i])658num_reg_good = i;659}660661index_good = -1;662if (num_reg_good != -1) {663for (i = 0; i < NUM_RESULT; i++) {664if (!result[i].bad &&665result[i].num_reg == num_reg_good &&666!result[i].lose_cover_sizek) {667index_good = i;668break;669}670}671}672673return index_good;674}675676int __init mtrr_cleanup(unsigned address_bits)677{678unsigned long x_remove_base, x_remove_size;679unsigned long base, size, def, dummy;680u64 chunk_size, gran_size;681mtrr_type type;682int index_good;683int i;684685if (!is_cpu(INTEL) || enable_mtrr_cleanup < 1)686return 0;687688rdmsr(MSR_MTRRdefType, def, dummy);689def &= 0xff;690if (def != MTRR_TYPE_UNCACHABLE)691return 0;692693/* Get it and store it aside: */694memset(range_state, 0, sizeof(range_state));695for (i = 0; i < num_var_ranges; i++) {696mtrr_if->get(i, &base, &size, &type);697range_state[i].base_pfn = base;698range_state[i].size_pfn = size;699range_state[i].type = type;700}701702/* Check if we need handle it and can handle it: */703if (!mtrr_need_cleanup())704return 0;705706/* Print original var MTRRs at first, for debugging: */707printk(KERN_DEBUG "original variable MTRRs\n");708print_out_mtrr_range_state();709710memset(range, 0, sizeof(range));711x_remove_size = 0;712x_remove_base = 1 << (32 - PAGE_SHIFT);713if (mtrr_tom2)714x_remove_size = (mtrr_tom2 >> PAGE_SHIFT) - x_remove_base;715716nr_range = x86_get_mtrr_mem_range(range, 0, x_remove_base, x_remove_size);717/*718* [0, 1M) should always be covered by var mtrr with WB719* and fixed mtrrs should take effect before var mtrr for it:720*/721nr_range = add_range_with_merge(range, RANGE_NUM, nr_range, 0,7221ULL<<(20 - PAGE_SHIFT));723/* Sort the ranges: */724sort_range(range, nr_range);725726range_sums = sum_ranges(range, nr_range);727printk(KERN_INFO "total RAM covered: %ldM\n",728range_sums >> (20 - PAGE_SHIFT));729730if (mtrr_chunk_size && mtrr_gran_size) {731i = 0;732mtrr_calc_range_state(mtrr_chunk_size, mtrr_gran_size,733x_remove_base, x_remove_size, i);734735mtrr_print_out_one_result(i);736737if (!result[i].bad) {738set_var_mtrr_all(address_bits);739printk(KERN_DEBUG "New variable MTRRs\n");740print_out_mtrr_range_state();741return 1;742}743printk(KERN_INFO "invalid mtrr_gran_size or mtrr_chunk_size, "744"will find optimal one\n");745}746747i = 0;748memset(min_loss_pfn, 0xff, sizeof(min_loss_pfn));749memset(result, 0, sizeof(result));750for (gran_size = (1ULL<<16); gran_size < (1ULL<<32); gran_size <<= 1) {751752for (chunk_size = gran_size; chunk_size < (1ULL<<32);753chunk_size <<= 1) {754755if (i >= NUM_RESULT)756continue;757758mtrr_calc_range_state(chunk_size, gran_size,759x_remove_base, x_remove_size, i);760if (debug_print) {761mtrr_print_out_one_result(i);762printk(KERN_INFO "\n");763}764765i++;766}767}768769/* Try to find the optimal index: */770index_good = mtrr_search_optimal_index();771772if (index_good != -1) {773printk(KERN_INFO "Found optimal setting for mtrr clean up\n");774i = index_good;775mtrr_print_out_one_result(i);776777/* Convert ranges to var ranges state: */778chunk_size = result[i].chunk_sizek;779chunk_size <<= 10;780gran_size = result[i].gran_sizek;781gran_size <<= 10;782x86_setup_var_mtrrs(range, nr_range, chunk_size, gran_size);783set_var_mtrr_all(address_bits);784printk(KERN_DEBUG "New variable MTRRs\n");785print_out_mtrr_range_state();786return 1;787} else {788/* print out all */789for (i = 0; i < NUM_RESULT; i++)790mtrr_print_out_one_result(i);791}792793printk(KERN_INFO "mtrr_cleanup: can not find optimal value\n");794printk(KERN_INFO "please specify mtrr_gran_size/mtrr_chunk_size\n");795796return 0;797}798#else799int __init mtrr_cleanup(unsigned address_bits)800{801return 0;802}803#endif804805static int disable_mtrr_trim;806807static int __init disable_mtrr_trim_setup(char *str)808{809disable_mtrr_trim = 1;810return 0;811}812early_param("disable_mtrr_trim", disable_mtrr_trim_setup);813814/*815* Newer AMD K8s and later CPUs have a special magic MSR way to force WB816* for memory >4GB. Check for that here.817* Note this won't check if the MTRRs < 4GB where the magic bit doesn't818* apply to are wrong, but so far we don't know of any such case in the wild.819*/820#define Tom2Enabled (1U << 21)821#define Tom2ForceMemTypeWB (1U << 22)822823int __init amd_special_default_mtrr(void)824{825u32 l, h;826827if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD)828return 0;829if (boot_cpu_data.x86 < 0xf)830return 0;831/* In case some hypervisor doesn't pass SYSCFG through: */832if (rdmsr_safe(MSR_K8_SYSCFG, &l, &h) < 0)833return 0;834/*835* Memory between 4GB and top of mem is forced WB by this magic bit.836* Reserved before K8RevF, but should be zero there.837*/838if ((l & (Tom2Enabled | Tom2ForceMemTypeWB)) ==839(Tom2Enabled | Tom2ForceMemTypeWB))840return 1;841return 0;842}843844static u64 __init845real_trim_memory(unsigned long start_pfn, unsigned long limit_pfn)846{847u64 trim_start, trim_size;848849trim_start = start_pfn;850trim_start <<= PAGE_SHIFT;851852trim_size = limit_pfn;853trim_size <<= PAGE_SHIFT;854trim_size -= trim_start;855856return e820_update_range(trim_start, trim_size, E820_RAM, E820_RESERVED);857}858859/**860* mtrr_trim_uncached_memory - trim RAM not covered by MTRRs861* @end_pfn: ending page frame number862*863* Some buggy BIOSes don't setup the MTRRs properly for systems with certain864* memory configurations. This routine checks that the highest MTRR matches865* the end of memory, to make sure the MTRRs having a write back type cover866* all of the memory the kernel is intending to use. If not, it'll trim any867* memory off the end by adjusting end_pfn, removing it from the kernel's868* allocation pools, warning the user with an obnoxious message.869*/870int __init mtrr_trim_uncached_memory(unsigned long end_pfn)871{872unsigned long i, base, size, highest_pfn = 0, def, dummy;873mtrr_type type;874u64 total_trim_size;875/* extra one for all 0 */876int num[MTRR_NUM_TYPES + 1];877878/*879* Make sure we only trim uncachable memory on machines that880* support the Intel MTRR architecture:881*/882if (!is_cpu(INTEL) || disable_mtrr_trim)883return 0;884885rdmsr(MSR_MTRRdefType, def, dummy);886def &= 0xff;887if (def != MTRR_TYPE_UNCACHABLE)888return 0;889890/* Get it and store it aside: */891memset(range_state, 0, sizeof(range_state));892for (i = 0; i < num_var_ranges; i++) {893mtrr_if->get(i, &base, &size, &type);894range_state[i].base_pfn = base;895range_state[i].size_pfn = size;896range_state[i].type = type;897}898899/* Find highest cached pfn: */900for (i = 0; i < num_var_ranges; i++) {901type = range_state[i].type;902if (type != MTRR_TYPE_WRBACK)903continue;904base = range_state[i].base_pfn;905size = range_state[i].size_pfn;906if (highest_pfn < base + size)907highest_pfn = base + size;908}909910/* kvm/qemu doesn't have mtrr set right, don't trim them all: */911if (!highest_pfn) {912printk(KERN_INFO "CPU MTRRs all blank - virtualized system.\n");913return 0;914}915916/* Check entries number: */917memset(num, 0, sizeof(num));918for (i = 0; i < num_var_ranges; i++) {919type = range_state[i].type;920if (type >= MTRR_NUM_TYPES)921continue;922size = range_state[i].size_pfn;923if (!size)924type = MTRR_NUM_TYPES;925num[type]++;926}927928/* No entry for WB? */929if (!num[MTRR_TYPE_WRBACK])930return 0;931932/* Check if we only had WB and UC: */933if (num[MTRR_TYPE_WRBACK] + num[MTRR_TYPE_UNCACHABLE] !=934num_var_ranges - num[MTRR_NUM_TYPES])935return 0;936937memset(range, 0, sizeof(range));938nr_range = 0;939if (mtrr_tom2) {940range[nr_range].start = (1ULL<<(32 - PAGE_SHIFT));941range[nr_range].end = mtrr_tom2 >> PAGE_SHIFT;942if (highest_pfn < range[nr_range].end)943highest_pfn = range[nr_range].end;944nr_range++;945}946nr_range = x86_get_mtrr_mem_range(range, nr_range, 0, 0);947948/* Check the head: */949total_trim_size = 0;950if (range[0].start)951total_trim_size += real_trim_memory(0, range[0].start);952953/* Check the holes: */954for (i = 0; i < nr_range - 1; i++) {955if (range[i].end < range[i+1].start)956total_trim_size += real_trim_memory(range[i].end,957range[i+1].start);958}959960/* Check the top: */961i = nr_range - 1;962if (range[i].end < end_pfn)963total_trim_size += real_trim_memory(range[i].end,964end_pfn);965966if (total_trim_size) {967pr_warning("WARNING: BIOS bug: CPU MTRRs don't cover all of memory, losing %lluMB of RAM.\n", total_trim_size >> 20);968969if (!changed_by_mtrr_cleanup)970WARN_ON(1);971972pr_info("update e820 for mtrr\n");973update_e820();974975return 1;976}977978return 0;979}980981982