CoCalc -- hardware.h

GitHub Repository: awilliam/linux-vfio
Path: blob/master/arch/xtensa/variants/s6000/include/variant/hardware.h
¹⁰⁸²¹ views
1
#ifndef __XTENSA_S6000_HARDWARE_H
2
#define __XTENSA_S6000_HARDWARE_H
3

4
#define S6_SCLK			1843200
5

6
#define S6_MEM_REG              0x20000000
7
#define S6_MEM_EFI              0x33F00000
8
#define S6_MEM_PCIE_DATARAM1    0x34000000
9
#define S6_MEM_XLMI             0x37F80000
10
#define S6_MEM_PIF_DATARAM1     0x37FFC000
11
#define S6_MEM_GMAC             0x38000000
12
#define S6_MEM_I2S              0x3A000000
13
#define S6_MEM_EGIB             0x3C000000
14
#define S6_MEM_PCIE_CFG         0x3E000000
15
#define S6_MEM_PIF_DATARAM      0x3FFE0000
16
#define S6_MEM_XLMI_DATARAM     0x3FFF0000
17
#define S6_MEM_DDR              0x40000000
18
#define S6_MEM_PCIE_APER        0xC0000000
19
#define S6_MEM_AUX              0xF0000000
20

21
/* Device addresses */
22

23
#define S6_REG_SCB              S6_MEM_REG
24
#define S6_REG_NB               (S6_REG_SCB + 0x10000)
25
#define S6_REG_LMSDMA           (S6_REG_SCB + 0x20000)
26
#define S6_REG_NI               (S6_REG_SCB + 0x30000)
27
#define S6_REG_NIDMA            (S6_REG_SCB + 0x40000)
28
#define S6_REG_NS               (S6_REG_SCB + 0x50000)
29
#define S6_REG_DDR              (S6_REG_SCB + 0x60000)
30
#define S6_REG_GREG1            (S6_REG_SCB + 0x70000)
31
#define S6_REG_DP               (S6_REG_SCB + 0x80000)
32
#define S6_REG_DPDMA            (S6_REG_SCB + 0x90000)
33
#define S6_REG_EGIB             (S6_REG_SCB + 0xA0000)
34
#define S6_REG_PCIE             (S6_REG_SCB + 0xB0000)
35
#define S6_REG_I2S              (S6_REG_SCB + 0xC0000)
36
#define S6_REG_GMAC             (S6_REG_SCB + 0xD0000)
37
#define S6_REG_HIFDMA           (S6_REG_SCB + 0xE0000)
38
#define S6_REG_GREG2            (S6_REG_SCB + 0xF0000)
39

40
#define S6_REG_APB              S6_REG_SCB
41
#define S6_REG_UART             (S6_REG_APB + 0x0000)
42
#define S6_REG_INTC             (S6_REG_APB + 0x2000)
43
#define S6_REG_SPI              (S6_REG_APB + 0x3000)
44
#define S6_REG_I2C              (S6_REG_APB + 0x4000)
45
#define S6_REG_GPIO             (S6_REG_APB + 0x8000)
46

47
/* Global register block */
48

49
#define S6_GREG1_PLL_LOCKCLEAR	0x000
50
#define S6_GREG1_PLL_LOCK_SYS		0
51
#define S6_GREG1_PLL_LOCK_IO		1
52
#define S6_GREG1_PLL_LOCK_AIM		2
53
#define S6_GREG1_PLL_LOCK_DP0		3
54
#define S6_GREG1_PLL_LOCK_DP2		4
55
#define S6_GREG1_PLL_LOCK_DDR		5
56
#define S6_GREG1_PLL_LOCKSTAT	0x004
57
#define S6_GREG1_PLL_LOCKSTAT_CURLOCK	0
58
#define S6_GREG1_PLL_LOCKSTAT_EVERUNLCK	8
59
#define S6_GREG1_PLLSEL		0x010
60
#define S6_GREG1_PLLSEL_AIM		0
61
#define S6_GREG1_PLLSEL_AIM_DDR2		0
62
#define S6_GREG1_PLLSEL_AIM_300MHZ		1
63
#define S6_GREG1_PLLSEL_AIM_240MHZ		2
64
#define S6_GREG1_PLLSEL_AIM_200MHZ		3
65
#define S6_GREG1_PLLSEL_AIM_150MHZ		4
66
#define S6_GREG1_PLLSEL_AIM_120MHZ		5
67
#define S6_GREG1_PLLSEL_AIM_40MHZ		6
68
#define S6_GREG1_PLLSEL_AIM_PLLAIMREF		7
69
#define S6_GREG1_PLLSEL_AIM_MASK		7
70
#define S6_GREG1_PLLSEL_DDR		8
71
#define S6_GREG1_PLLSEL_DDR_HS			0
72
#define S6_GREG1_PLLSEL_DDR_333MHZ		1
73
#define S6_GREG1_PLLSEL_DDR_250MHZ		2
74
#define S6_GREG1_PLLSEL_DDR_200MHZ		3
75
#define S6_GREG1_PLLSEL_DDR_167MHZ		4
76
#define S6_GREG1_PLLSEL_DDR_100MHZ		5
77
#define S6_GREG1_PLLSEL_DDR_33MHZ		6
78
#define S6_GREG1_PLLSEL_DDR_PLLIOREF		7
79
#define S6_GREG1_PLLSEL_DDR_MASK		7
80
#define S6_GREG1_PLLSEL_GMAC		16
81
#define S6_GREG1_PLLSEL_GMAC_125MHZ		0
82
#define S6_GREG1_PLLSEL_GMAC_25MHZ		1
83
#define S6_GREG1_PLLSEL_GMAC_2500KHZ		2
84
#define S6_GREG1_PLLSEL_GMAC_EXTERN		3
85
#define S6_GREG1_PLLSEL_GMAC_MASK		3
86
#define S6_GREG1_PLLSEL_GMII		18
87
#define S6_GREG1_PLLSEL_GMII_111MHZ		0
88
#define S6_GREG1_PLLSEL_GMII_IOREF		1
89
#define S6_GREG1_PLLSEL_GMII_NONE		2
90
#define S6_GREG1_PLLSEL_GMII_125MHZ		3
91
#define S6_GREG1_PLLSEL_GMII_MASK		3
92
#define S6_GREG1_SYSUNLOCKCNT	0x020
93
#define S6_GREG1_IOUNLOCKCNT	0x024
94
#define S6_GREG1_AIMUNLOCKCNT	0x028
95
#define S6_GREG1_DP0UNLOCKCNT	0x02C
96
#define S6_GREG1_DP2UNLOCKCNT	0x030
97
#define S6_GREG1_DDRUNLOCKCNT	0x034
98
#define S6_GREG1_CLKBAL0	0x040
99
#define S6_GREG1_CLKBAL0_LSGB		0
100
#define S6_GREG1_CLKBAL0_LSPX		8
101
#define S6_GREG1_CLKBAL0_MEMDO		16
102
#define S6_GREG1_CLKBAL0_HSXT1		24
103
#define S6_GREG1_CLKBAL1	0x044
104
#define S6_GREG1_CLKBAL1_HSISEF		0
105
#define S6_GREG1_CLKBAL1_HSNI		8
106
#define S6_GREG1_CLKBAL1_HSNS		16
107
#define S6_GREG1_CLKBAL1_HSISEFCFG	24
108
#define S6_GREG1_CLKBAL2	0x048
109
#define S6_GREG1_CLKBAL2_LSNB		0
110
#define S6_GREG1_CLKBAL2_LSSB		8
111
#define S6_GREG1_CLKBAL2_LSREST		24
112
#define S6_GREG1_CLKBAL3	0x04C
113
#define S6_GREG1_CLKBAL3_ISEFXAD	0
114
#define S6_GREG1_CLKBAL3_ISEFLMS	8
115
#define S6_GREG1_CLKBAL3_ISEFISEF	16
116
#define S6_GREG1_CLKBAL3_DDRDD		24
117
#define S6_GREG1_CLKBAL4	0x050
118
#define S6_GREG1_CLKBAL4_DDRDP		0
119
#define S6_GREG1_CLKBAL4_DDRDO		8
120
#define S6_GREG1_CLKBAL4_DDRNB		16
121
#define S6_GREG1_CLKBAL4_DDRLMS		24
122
#define S6_GREG1_BLOCKENA	0x100
123
#define S6_GREG1_BLOCK_DDR		0
124
#define S6_GREG1_BLOCK_DP		1
125
#define S6_GREG1_BLOCK_NSNI		2
126
#define S6_GREG1_BLOCK_PCIE		3
127
#define S6_GREG1_BLOCK_GMAC		4
128
#define S6_GREG1_BLOCK_I2S		5
129
#define S6_GREG1_BLOCK_EGIB		6
130
#define S6_GREG1_BLOCK_SB		7
131
#define S6_GREG1_BLOCK_XT1		8
132
#define S6_GREG1_CLKGATE	0x104
133
#define S6_GREG1_BGATE_AIMNORTH		9
134
#define S6_GREG1_BGATE_AIMEAST		10
135
#define S6_GREG1_BGATE_AIMWEST		11
136
#define S6_GREG1_BGATE_AIMSOUTH		12
137
#define S6_GREG1_CHIPRES	0x108
138
#define S6_GREG1_CHIPRES_SOFTRES	0
139
#define S6_GREG1_CHIPRES_LOSTLOCK	1
140
#define S6_GREG1_RESETCAUSE	0x10C
141
#define S6_GREG1_RESETCAUSE_RESETN	0
142
#define S6_GREG1_RESETCAUSE_GLOBAL	1
143
#define S6_GREG1_RESETCAUSE_WDOGTIMER	2
144
#define S6_GREG1_RESETCAUSE_SWCHIP	3
145
#define S6_GREG1_RESETCAUSE_PLLSYSLOSS	4
146
#define S6_GREG1_RESETCAUSE_PCIE	5
147
#define S6_GREG1_RESETCAUSE_CREATEDGLOB	6
148
#define S6_GREG1_REFCLOCKCNT	0x110
149
#define S6_GREG1_RESETTIMER	0x114
150
#define S6_GREG1_NMITIMER	0x118
151
#define S6_GREG1_GLOBAL_TIMER	0x11C
152
#define S6_GREG1_TIMER0		0x180
153
#define S6_GREG1_TIMER1		0x184
154
#define S6_GREG1_UARTCLOCKSEL	0x204
155
#define S6_GREG1_CHIPVERSPACKG	0x208
156
#define S6_GREG1_CHIPVERSPACKG_CHIPVID	0
157
#define S6_GREG1_CHIPVERSPACKG_PACKSEL	8
158
#define S6_GREG1_ONDIETERMCTRL	0x20C
159
#define S6_GREG1_ONDIETERMCTRL_WEST	0
160
#define S6_GREG1_ONDIETERMCTRL_NORTH	2
161
#define S6_GREG1_ONDIETERMCTRL_EAST	4
162
#define S6_GREG1_ONDIETERMCTRL_SOUTH	6
163
#define S6_GREG1_ONDIETERMCTRL_NONE		0
164
#define S6_GREG1_ONDIETERMCTRL_75OHM		2
165
#define S6_GREG1_ONDIETERMCTRL_MASK		3
166
#define S6_GREG1_BOOT_CFG0	0x210
167
#define S6_GREG1_BOOT_CFG0_AIMSTRONG	1
168
#define S6_GREG1_BOOT_CFG0_MINIBOOTDL	2
169
#define S6_GREG1_BOOT_CFG0_OCDGPIO8SET	5
170
#define S6_GREG1_BOOT_CFG0_OCDGPIOENA	6
171
#define S6_GREG1_BOOT_CFG0_DOWNSTREAM	7
172
#define S6_GREG1_BOOT_CFG0_PLLSYSDIV	8
173
#define S6_GREG1_BOOT_CFG0_PLLSYSDIV_300MHZ	1
174
#define S6_GREG1_BOOT_CFG0_PLLSYSDIV_240MHZ	2
175
#define S6_GREG1_BOOT_CFG0_PLLSYSDIV_200MHZ	3
176
#define S6_GREG1_BOOT_CFG0_PLLSYSDIV_150MHZ	4
177
#define S6_GREG1_BOOT_CFG0_PLLSYSDIV_120MHZ	5
178
#define S6_GREG1_BOOT_CFG0_PLLSYSDIV_40MHZ	6
179
#define S6_GREG1_BOOT_CFG0_PLLSYSDIV_MASK	7
180
#define S6_GREG1_BOOT_CFG0_BALHSLMS	12
181
#define S6_GREG1_BOOT_CFG0_BALHSNB	18
182
#define S6_GREG1_BOOT_CFG0_BALHSXAD	24
183
#define S6_GREG1_BOOT_CFG1	0x214
184
#define S6_GREG1_BOOT_CFG1_PCIE1LANE	1
185
#define S6_GREG1_BOOT_CFG1_MPLLPRESCALE	2
186
#define S6_GREG1_BOOT_CFG1_MPLLNCY	4
187
#define S6_GREG1_BOOT_CFG1_MPLLNCY5	9
188
#define S6_GREG1_BOOT_CFG1_BALHSREST	14
189
#define S6_GREG1_BOOT_CFG1_BALHSPSMEMS	20
190
#define S6_GREG1_BOOT_CFG1_BALLSGI	26
191
#define S6_GREG1_BOOT_CFG2	0x218
192
#define S6_GREG1_BOOT_CFG2_PEID		0
193
#define S6_GREG1_BOOT_CFG3	0x21C
194
#define S6_GREG1_DRAMBUSYHOLDOF	0x220
195
#define S6_GREG1_DRAMBUSYHOLDOF_XT0	0
196
#define S6_GREG1_DRAMBUSYHOLDOF_XT1	4
197
#define S6_GREG1_DRAMBUSYHOLDOF_XT_MASK		7
198
#define S6_GREG1_PCIEBAR1SIZE	0x224
199
#define S6_GREG1_PCIEBAR2SIZE	0x228
200
#define S6_GREG1_PCIEVENDOR	0x22C
201
#define S6_GREG1_PCIEDEVICE	0x230
202
#define S6_GREG1_PCIEREV	0x234
203
#define S6_GREG1_PCIECLASS	0x238
204
#define S6_GREG1_XT1DCACHEMISS	0x240
205
#define S6_GREG1_XT1ICACHEMISS	0x244
206
#define S6_GREG1_HWSEMAPHORE(n)	(0x400 + 4 * (n))
207
#define S6_GREG1_HWSEMAPHORE_NB		16
208

209
/* peripheral interrupt numbers */
210

211
#define S6_INTC_GPIO(n)			(n)		/* 0..3 */
212
#define S6_INTC_I2C			4
213
#define S6_INTC_SPI			5
214
#define S6_INTC_NB_ERR			6
215
#define S6_INTC_DMA_LMSERR		7
216
#define S6_INTC_DMA_LMSLOWWMRK(n)	(8 + (n))	/* 0..11 */
217
#define S6_INTC_DMA_LMSPENDCNT(n)	(20 + (n))	/* 0..11 */
218
#define S6_INTC_DMA HOSTLOWWMRK(n)	(32 + (n))	/* 0..6 */
219
#define S6_INTC_DMA_HOSTPENDCNT(n)	(39 + (n))	/* 0..6 */
220
#define S6_INTC_DMA_HOSTERR		46
221
#define S6_INTC_UART(n)			(47 + (n))	/* 0..1 */
222
#define S6_INTC_XAD			49
223
#define S6_INTC_NI_ERR			50
224
#define S6_INTC_NI_INFIFOFULL		51
225
#define S6_INTC_DMA_NIERR		52
226
#define S6_INTC_DMA_NILOWWMRK(n)	(53 + (n))	/* 0..3 */
227
#define S6_INTC_DMA_NIPENDCNT(n)	(57 + (n))	/* 0..3 */
228
#define S6_INTC_DDR			61
229
#define S6_INTC_NS_ERR			62
230
#define S6_INTC_EFI_CFGERR		63
231
#define S6_INTC_EFI_ISEFTEST		64
232
#define S6_INTC_EFI_WRITEERR		65
233
#define S6_INTC_NMI_TIMER		66
234
#define S6_INTC_PLLLOCK_SYS		67
235
#define S6_INTC_PLLLOCK_IO		68
236
#define S6_INTC_PLLLOCK_AIM		69
237
#define S6_INTC_PLLLOCK_DP0		70
238
#define S6_INTC_PLLLOCK_DP2		71
239
#define S6_INTC_I2S_ERR			72
240
#define S6_INTC_GMAC_STAT		73
241
#define S6_INTC_GMAC_ERR		74
242
#define S6_INTC_GIB_ERR			75
243
#define S6_INTC_PCIE_ERR		76
244
#define S6_INTC_PCIE_MSI(n)		(77 + (n))	/* 0..3 */
245
#define S6_INTC_PCIE_INTA		81
246
#define S6_INTC_PCIE_INTB		82
247
#define S6_INTC_PCIE_INTC		83
248
#define S6_INTC_PCIE_INTD		84
249
#define S6_INTC_SW(n)			(85 + (n))	/* 0..9 */
250
#define S6_INTC_SW_ENABLE(n)		(85 + 256 + (n))
251
#define S6_INTC_DMA_DP_ERR		95
252
#define S6_INTC_DMA_DPLOWWMRK(n)	(96 + (n))	/* 0..3 */
253
#define S6_INTC_DMA_DPPENDCNT(n)	(100 + (n))	/* 0..3 */
254
#define S6_INTC_DMA_DPTERMCNT(n)	(104 + (n))	/* 0..3 */
255
#define S6_INTC_TIMER0			108
256
#define S6_INTC_TIMER1			109
257
#define S6_INTC_DMA_HOSTTERMCNT(n)	(110 + (n))	/* 0..6 */
258

259
#endif /* __XTENSA_S6000_HARDWARE_H */
260

261
Product

Resources

Company
