CoCalc -- tie-asm.h

GitHub Repository: awilliam/linux-vfio
Path: blob/master/arch/xtensa/variants/s6000/include/variant/tie-asm.h
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/*
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 * This header file contains assembly-language definitions (assembly
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 * macros, etc.) for this specific Xtensa processor's TIE extensions
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 * and options.  It is customized to this Xtensa processor configuration.
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 *
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 * This file is subject to the terms and conditions of the GNU General Public
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 * License.  See the file "COPYING" in the main directory of this archive
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 * for more details.
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 *
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 * Copyright (C) 1999-2008 Tensilica Inc.
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 */
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#ifndef _XTENSA_CORE_TIE_ASM_H
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#define _XTENSA_CORE_TIE_ASM_H
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/*  Selection parameter values for save-area save/restore macros:  */
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/*  Option vs. TIE:  */
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#define XTHAL_SAS_TIE	0x0001	/* custom extension or coprocessor */
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#define XTHAL_SAS_OPT	0x0002	/* optional (and not a coprocessor) */
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/*  Whether used automatically by compiler:  */
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#define XTHAL_SAS_NOCC	0x0004	/* not used by compiler w/o special opts/code */
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#define XTHAL_SAS_CC	0x0008	/* used by compiler without special opts/code */
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/*  ABI handling across function calls:  */
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#define XTHAL_SAS_CALR	0x0010	/* caller-saved */
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#define XTHAL_SAS_CALE	0x0020	/* callee-saved */
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#define XTHAL_SAS_GLOB	0x0040	/* global across function calls (in thread) */
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/*  Misc  */
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#define XTHAL_SAS_ALL	0xFFFF	/* include all default NCP contents */
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/* Macro to save all non-coprocessor (extra) custom TIE and optional state
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 * (not including zero-overhead loop registers).
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 * Save area ptr (clobbered):  ptr  (16 byte aligned)
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 * Scratch regs  (clobbered):  at1..at4  (only first XCHAL_NCP_NUM_ATMPS needed)
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 */
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	.macro xchal_ncp_store  ptr at1 at2 at3 at4  continue=0 ofs=-1 select=XTHAL_SAS_ALL
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	xchal_sa_start	\continue, \ofs
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	.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~\select
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	xchal_sa_align	\ptr, 0, 1024-4, 4, 4
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	rsr	\at1, BR		// boolean option
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	s32i	\at1, \ptr, .Lxchal_ofs_ + 0
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	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 4
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	.endif
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	.endm	// xchal_ncp_store
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/* Macro to save all non-coprocessor (extra) custom TIE and optional state
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 * (not including zero-overhead loop registers).
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 * Save area ptr (clobbered):  ptr  (16 byte aligned)
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 * Scratch regs  (clobbered):  at1..at4  (only first XCHAL_NCP_NUM_ATMPS needed)
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 */
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	.macro xchal_ncp_load  ptr at1 at2 at3 at4  continue=0 ofs=-1 select=XTHAL_SAS_ALL
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	xchal_sa_start	\continue, \ofs
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	.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~\select
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	xchal_sa_align	\ptr, 0, 1024-4, 4, 4
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	l32i	\at1, \ptr, .Lxchal_ofs_ + 0
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	wsr	\at1, BR		// boolean option
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	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 4
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	.endif
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	.endm	// xchal_ncp_load
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#define XCHAL_NCP_NUM_ATMPS	1
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/* Macro to save the state of TIE coprocessor FPU.
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 * Save area ptr (clobbered):  ptr  (16 byte aligned)
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 * Scratch regs  (clobbered):  at1..at4  (only first XCHAL_CP0_NUM_ATMPS needed)
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 */
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#define xchal_cp_FPU_store	xchal_cp0_store
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/* #define xchal_cp_FPU_store_a2	xchal_cp0_store a2 a3 a4 a5 a6 */
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	.macro	xchal_cp0_store  ptr at1 at2 at3 at4  continue=0 ofs=-1 select=XTHAL_SAS_ALL
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	xchal_sa_start \continue, \ofs
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	.ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~\select
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	xchal_sa_align	\ptr, 0, 0, 1, 16
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	rur232	\at1		// FCR
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	s32i	\at1, \ptr, 0
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	rur233	\at1		// FSR
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	s32i	\at1, \ptr, 4
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	SSI f0, \ptr,  8
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	SSI f1, \ptr,  12
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	SSI f2, \ptr,  16
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	SSI f3, \ptr,  20
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	SSI f4, \ptr,  24
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	SSI f5, \ptr,  28
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	SSI f6, \ptr,  32
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	SSI f7, \ptr,  36
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	SSI f8, \ptr,  40
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	SSI f9, \ptr,  44
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	SSI f10, \ptr,  48
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	SSI f11, \ptr,  52
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	SSI f12, \ptr,  56
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	SSI f13, \ptr,  60
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	SSI f14, \ptr,  64
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	SSI f15, \ptr,  68
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	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 72
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	.endif
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	.endm	// xchal_cp0_store
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/* Macro to restore the state of TIE coprocessor FPU.
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 * Save area ptr (clobbered):  ptr  (16 byte aligned)
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 * Scratch regs  (clobbered):  at1..at4  (only first XCHAL_CP0_NUM_ATMPS needed)
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 */
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#define xchal_cp_FPU_load	xchal_cp0_load
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/* #define xchal_cp_FPU_load_a2	xchal_cp0_load a2 a3 a4 a5 a6 */
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	.macro	xchal_cp0_load  ptr at1 at2 at3 at4  continue=0 ofs=-1 select=XTHAL_SAS_ALL
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	xchal_sa_start \continue, \ofs
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	.ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~\select
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	xchal_sa_align	\ptr, 0, 0, 1, 16
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	l32i	\at1, \ptr, 0
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	wur232	\at1		// FCR
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	l32i	\at1, \ptr, 4
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	wur233	\at1		// FSR
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	LSI f0, \ptr,  8
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	LSI f1, \ptr,  12
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	LSI f2, \ptr,  16
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	LSI f3, \ptr,  20
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	LSI f4, \ptr,  24
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	LSI f5, \ptr,  28
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	LSI f6, \ptr,  32
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	LSI f7, \ptr,  36
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	LSI f8, \ptr,  40
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	LSI f9, \ptr,  44
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	LSI f10, \ptr,  48
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	LSI f11, \ptr,  52
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	LSI f12, \ptr,  56
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	LSI f13, \ptr,  60
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	LSI f14, \ptr,  64
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	LSI f15, \ptr,  68
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	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 72
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	.endif
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	.endm	// xchal_cp0_load
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#define XCHAL_CP0_NUM_ATMPS	1
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/* Macro to save the state of TIE coprocessor XAD.
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 * Save area ptr (clobbered):  ptr  (16 byte aligned)
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 * Scratch regs  (clobbered):  at1..at4  (only first XCHAL_CP6_NUM_ATMPS needed)
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 */
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#define xchal_cp_XAD_store	xchal_cp6_store
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/* #define xchal_cp_XAD_store_a2	xchal_cp6_store a2 a3 a4 a5 a6 */
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	.macro	xchal_cp6_store  ptr at1 at2 at3 at4  continue=0 ofs=-1 select=XTHAL_SAS_ALL
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	xchal_sa_start \continue, \ofs
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	.ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~\select
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	xchal_sa_align	\ptr, 0, 0, 1, 16
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	rur0	\at1		// LDCBHI
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	s32i	\at1, \ptr, 0
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	rur1	\at1		// LDCBLO
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	s32i	\at1, \ptr, 4
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	rur2	\at1		// STCBHI
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	s32i	\at1, \ptr, 8
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	rur3	\at1		// STCBLO
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	s32i	\at1, \ptr, 12
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	rur8	\at1		// LDBRBASE
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	s32i	\at1, \ptr, 16
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	rur9	\at1		// LDBROFF
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	s32i	\at1, \ptr, 20
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	rur10	\at1		// LDBRINC
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	s32i	\at1, \ptr, 24
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	rur11	\at1		// STBRBASE
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	s32i	\at1, \ptr, 28
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	rur12	\at1		// STBROFF
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	s32i	\at1, \ptr, 32
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	rur13	\at1		// STBRINC
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	s32i	\at1, \ptr, 36
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	rur24	\at1		// SCRATCH0
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	s32i	\at1, \ptr, 40
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	rur25	\at1		// SCRATCH1
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	s32i	\at1, \ptr, 44
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	rur26	\at1		// SCRATCH2
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	s32i	\at1, \ptr, 48
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	rur27	\at1		// SCRATCH3
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	s32i	\at1, \ptr, 52
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	WRAS128I wra0, \ptr,  64
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	WRAS128I wra1, \ptr,  80
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	WRAS128I wra2, \ptr,  96
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	WRAS128I wra3, \ptr,  112
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	WRAS128I wra4, \ptr,  128
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	WRAS128I wra5, \ptr,  144
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	WRAS128I wra6, \ptr,  160
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	WRAS128I wra7, \ptr,  176
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	WRAS128I wra8, \ptr,  192
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	WRAS128I wra9, \ptr,  208
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	WRAS128I wra10, \ptr,  224
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	WRAS128I wra11, \ptr,  240
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	WRAS128I wra12, \ptr,  256
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	WRAS128I wra13, \ptr,  272
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	WRAS128I wra14, \ptr,  288
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	WRAS128I wra15, \ptr,  304
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	WRBS128I wrb0, \ptr,  320
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	WRBS128I wrb1, \ptr,  336
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	WRBS128I wrb2, \ptr,  352
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	WRBS128I wrb3, \ptr,  368
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	WRBS128I wrb4, \ptr,  384
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	WRBS128I wrb5, \ptr,  400
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	WRBS128I wrb6, \ptr,  416
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	WRBS128I wrb7, \ptr,  432
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	WRBS128I wrb8, \ptr,  448
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	WRBS128I wrb9, \ptr,  464
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	WRBS128I wrb10, \ptr,  480
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	WRBS128I wrb11, \ptr,  496
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	WRBS128I wrb12, \ptr,  512
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	WRBS128I wrb13, \ptr,  528
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	WRBS128I wrb14, \ptr,  544
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	WRBS128I wrb15, \ptr,  560
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	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 576
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	.endif
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	.endm	// xchal_cp6_store
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/* Macro to restore the state of TIE coprocessor XAD.
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 * Save area ptr (clobbered):  ptr  (16 byte aligned)
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 * Scratch regs  (clobbered):  at1..at4  (only first XCHAL_CP6_NUM_ATMPS needed)
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 */
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#define xchal_cp_XAD_load	xchal_cp6_load
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/* #define xchal_cp_XAD_load_a2	xchal_cp6_load a2 a3 a4 a5 a6 */
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	.macro	xchal_cp6_load  ptr at1 at2 at3 at4  continue=0 ofs=-1 select=XTHAL_SAS_ALL
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	xchal_sa_start \continue, \ofs
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	.ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~\select
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	xchal_sa_align	\ptr, 0, 0, 1, 16
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	l32i	\at1, \ptr, 0
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	wur0	\at1		// LDCBHI
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	l32i	\at1, \ptr, 4
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	wur1	\at1		// LDCBLO
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	l32i	\at1, \ptr, 8
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	wur2	\at1		// STCBHI
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	l32i	\at1, \ptr, 12
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	wur3	\at1		// STCBLO
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	l32i	\at1, \ptr, 16
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	wur8	\at1		// LDBRBASE
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	l32i	\at1, \ptr, 20
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	wur9	\at1		// LDBROFF
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	l32i	\at1, \ptr, 24
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	wur10	\at1		// LDBRINC
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	l32i	\at1, \ptr, 28
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	wur11	\at1		// STBRBASE
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	l32i	\at1, \ptr, 32
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	wur12	\at1		// STBROFF
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	l32i	\at1, \ptr, 36
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	wur13	\at1		// STBRINC
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	l32i	\at1, \ptr, 40
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	wur24	\at1		// SCRATCH0
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	l32i	\at1, \ptr, 44
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	wur25	\at1		// SCRATCH1
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	l32i	\at1, \ptr, 48
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	wur26	\at1		// SCRATCH2
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	l32i	\at1, \ptr, 52
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	wur27	\at1		// SCRATCH3
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	WRBL128I wrb0, \ptr,  320
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	WRBL128I wrb1, \ptr,  336
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	WRBL128I wrb2, \ptr,  352
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	WRBL128I wrb3, \ptr,  368
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	WRBL128I wrb4, \ptr,  384
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	WRBL128I wrb5, \ptr,  400
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	WRBL128I wrb6, \ptr,  416
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	WRBL128I wrb7, \ptr,  432
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	WRBL128I wrb8, \ptr,  448
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	WRBL128I wrb9, \ptr,  464
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	WRBL128I wrb10, \ptr,  480
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	WRBL128I wrb11, \ptr,  496
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	WRBL128I wrb12, \ptr,  512
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	WRBL128I wrb13, \ptr,  528
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	WRBL128I wrb14, \ptr,  544
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	WRBL128I wrb15, \ptr,  560
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	WRAL128I wra0, \ptr,  64
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	WRAL128I wra1, \ptr,  80
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	WRAL128I wra2, \ptr,  96
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	WRAL128I wra3, \ptr,  112
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	WRAL128I wra4, \ptr,  128
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	WRAL128I wra5, \ptr,  144
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	WRAL128I wra6, \ptr,  160
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	WRAL128I wra7, \ptr,  176
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	WRAL128I wra8, \ptr,  192
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	WRAL128I wra9, \ptr,  208
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	WRAL128I wra10, \ptr,  224
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	WRAL128I wra11, \ptr,  240
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	WRAL128I wra12, \ptr,  256
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	WRAL128I wra13, \ptr,  272
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	WRAL128I wra14, \ptr,  288
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	WRAL128I wra15, \ptr,  304
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	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 576
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	.endif
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	.endm	// xchal_cp6_load
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#define XCHAL_CP6_NUM_ATMPS	1
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#define XCHAL_SA_NUM_ATMPS	1
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	/*  Empty macros for unconfigured coprocessors:  */
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	.macro xchal_cp1_store	p a b c d continue=0 ofs=-1 select=-1 ; .endm
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	.macro xchal_cp1_load	p a b c d continue=0 ofs=-1 select=-1 ; .endm
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	.macro xchal_cp2_store	p a b c d continue=0 ofs=-1 select=-1 ; .endm
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	.macro xchal_cp2_load	p a b c d continue=0 ofs=-1 select=-1 ; .endm
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	.macro xchal_cp3_store	p a b c d continue=0 ofs=-1 select=-1 ; .endm
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	.macro xchal_cp3_load	p a b c d continue=0 ofs=-1 select=-1 ; .endm
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	.macro xchal_cp4_store	p a b c d continue=0 ofs=-1 select=-1 ; .endm
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	.macro xchal_cp4_load	p a b c d continue=0 ofs=-1 select=-1 ; .endm
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	.macro xchal_cp5_store	p a b c d continue=0 ofs=-1 select=-1 ; .endm
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	.macro xchal_cp5_load	p a b c d continue=0 ofs=-1 select=-1 ; .endm
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	.macro xchal_cp7_store	p a b c d continue=0 ofs=-1 select=-1 ; .endm
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	.macro xchal_cp7_load	p a b c d continue=0 ofs=-1 select=-1 ; .endm
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#endif /*_XTENSA_CORE_TIE_ASM_H*/
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