CoCalc -- mpc85xx

GitHub Repository: awilliam/linux-vfio
Path: blob/master/drivers/edac/mpc85xx_edac.h
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/*
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 * Freescale MPC85xx Memory Controller kenel module
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 * Author: Dave Jiang <[email protected]>
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 *
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 * 2006-2007 (c) MontaVista Software, Inc. This file is licensed under
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 * the terms of the GNU General Public License version 2. This program
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 * is licensed "as is" without any warranty of any kind, whether express
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 * or implied.
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 *
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 */
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#ifndef _MPC85XX_EDAC_H_
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#define _MPC85XX_EDAC_H_
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#define MPC85XX_REVISION " Ver: 2.0.0"
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#define EDAC_MOD_STR	"MPC85xx_edac"
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#define mpc85xx_printk(level, fmt, arg...) \
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	edac_printk(level, "MPC85xx", fmt, ##arg)
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#define mpc85xx_mc_printk(mci, level, fmt, arg...) \
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	edac_mc_chipset_printk(mci, level, "MPC85xx", fmt, ##arg)
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/*
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 * DRAM error defines
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 */
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/* DDR_SDRAM_CFG */
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#define MPC85XX_MC_DDR_SDRAM_CFG	0x0110
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#define MPC85XX_MC_CS_BNDS_0		0x0000
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#define MPC85XX_MC_CS_BNDS_1		0x0008
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#define MPC85XX_MC_CS_BNDS_2		0x0010
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#define MPC85XX_MC_CS_BNDS_3		0x0018
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#define MPC85XX_MC_CS_BNDS_OFS		0x0008
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#define MPC85XX_MC_DATA_ERR_INJECT_HI	0x0e00
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#define MPC85XX_MC_DATA_ERR_INJECT_LO	0x0e04
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#define MPC85XX_MC_ECC_ERR_INJECT	0x0e08
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#define MPC85XX_MC_CAPTURE_DATA_HI	0x0e20
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#define MPC85XX_MC_CAPTURE_DATA_LO	0x0e24
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#define MPC85XX_MC_CAPTURE_ECC		0x0e28
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#define MPC85XX_MC_ERR_DETECT		0x0e40
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#define MPC85XX_MC_ERR_DISABLE		0x0e44
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#define MPC85XX_MC_ERR_INT_EN		0x0e48
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#define MPC85XX_MC_CAPTURE_ATRIBUTES	0x0e4c
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#define MPC85XX_MC_CAPTURE_ADDRESS	0x0e50
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#define MPC85XX_MC_ERR_SBE		0x0e58
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#define DSC_MEM_EN	0x80000000
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#define DSC_ECC_EN	0x20000000
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#define DSC_RD_EN	0x10000000
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#define DSC_DBW_MASK	0x00180000
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#define DSC_DBW_32	0x00080000
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#define DSC_DBW_64	0x00000000
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#define DSC_SDTYPE_MASK		0x07000000
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#define DSC_SDTYPE_DDR		0x02000000
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#define DSC_SDTYPE_DDR2		0x03000000
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#define DSC_SDTYPE_DDR3		0x07000000
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#define DSC_X32_EN	0x00000020
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/* Err_Int_En */
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#define DDR_EIE_MSEE	0x1	/* memory select */
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#define DDR_EIE_SBEE	0x4	/* single-bit ECC error */
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#define DDR_EIE_MBEE	0x8	/* multi-bit ECC error */
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/* Err_Detect */
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#define DDR_EDE_MSE		0x1	/* memory select */
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#define DDR_EDE_SBE		0x4	/* single-bit ECC error */
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#define DDR_EDE_MBE		0x8	/* multi-bit ECC error */
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#define DDR_EDE_MME		0x80000000	/* multiple memory errors */
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/* Err_Disable */
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#define DDR_EDI_MSED	0x1	/* memory select disable */
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#define	DDR_EDI_SBED	0x4	/* single-bit ECC error disable */
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#define	DDR_EDI_MBED	0x8	/* multi-bit ECC error disable */
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/*
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 * L2 Err defines
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 */
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#define MPC85XX_L2_ERRINJHI	0x0000
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#define MPC85XX_L2_ERRINJLO	0x0004
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#define MPC85XX_L2_ERRINJCTL	0x0008
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#define MPC85XX_L2_CAPTDATAHI	0x0020
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#define MPC85XX_L2_CAPTDATALO	0x0024
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#define MPC85XX_L2_CAPTECC	0x0028
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#define MPC85XX_L2_ERRDET	0x0040
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#define MPC85XX_L2_ERRDIS	0x0044
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#define MPC85XX_L2_ERRINTEN	0x0048
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#define MPC85XX_L2_ERRATTR	0x004c
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#define MPC85XX_L2_ERRADDR	0x0050
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#define MPC85XX_L2_ERRCTL	0x0058
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/* Error Interrupt Enable */
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#define L2_EIE_L2CFGINTEN	0x1
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#define L2_EIE_SBECCINTEN	0x4
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#define L2_EIE_MBECCINTEN	0x8
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#define L2_EIE_TPARINTEN	0x10
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#define L2_EIE_MASK	(L2_EIE_L2CFGINTEN | L2_EIE_SBECCINTEN | \
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			L2_EIE_MBECCINTEN | L2_EIE_TPARINTEN)
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/* Error Detect */
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#define L2_EDE_L2CFGERR		0x1
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#define L2_EDE_SBECCERR		0x4
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#define L2_EDE_MBECCERR		0x8
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#define L2_EDE_TPARERR		0x10
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#define L2_EDE_MULL2ERR		0x80000000
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#define L2_EDE_CE_MASK	L2_EDE_SBECCERR
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#define L2_EDE_UE_MASK	(L2_EDE_L2CFGERR | L2_EDE_MBECCERR | \
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			L2_EDE_TPARERR)
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#define L2_EDE_MASK	(L2_EDE_L2CFGERR | L2_EDE_SBECCERR | \
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			L2_EDE_MBECCERR | L2_EDE_TPARERR | L2_EDE_MULL2ERR)
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/*
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 * PCI Err defines
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 */
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#define PCI_EDE_TOE			0x00000001
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#define PCI_EDE_SCM			0x00000002
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#define PCI_EDE_IRMSV			0x00000004
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#define PCI_EDE_ORMSV			0x00000008
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#define PCI_EDE_OWMSV			0x00000010
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#define PCI_EDE_TGT_ABRT		0x00000020
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#define PCI_EDE_MST_ABRT		0x00000040
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#define PCI_EDE_TGT_PERR		0x00000080
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#define PCI_EDE_MST_PERR		0x00000100
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#define PCI_EDE_RCVD_SERR		0x00000200
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#define PCI_EDE_ADDR_PERR		0x00000400
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#define PCI_EDE_MULTI_ERR		0x80000000
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#define PCI_EDE_PERR_MASK	(PCI_EDE_TGT_PERR | PCI_EDE_MST_PERR | \
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				PCI_EDE_ADDR_PERR)
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#define MPC85XX_PCI_ERR_DR		0x0000
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#define MPC85XX_PCI_ERR_CAP_DR		0x0004
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#define MPC85XX_PCI_ERR_EN		0x0008
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#define MPC85XX_PCI_ERR_ATTRIB		0x000c
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#define MPC85XX_PCI_ERR_ADDR		0x0010
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#define MPC85XX_PCI_ERR_EXT_ADDR	0x0014
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#define MPC85XX_PCI_ERR_DL		0x0018
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#define MPC85XX_PCI_ERR_DH		0x001c
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#define MPC85XX_PCI_GAS_TIMR		0x0020
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#define MPC85XX_PCI_PCIX_TIMR		0x0024
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struct mpc85xx_mc_pdata {
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	char *name;
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	int edac_idx;
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	void __iomem *mc_vbase;
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	int irq;
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};
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struct mpc85xx_l2_pdata {
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	char *name;
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	int edac_idx;
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	void __iomem *l2_vbase;
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	int irq;
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};
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struct mpc85xx_pci_pdata {
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	char *name;
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	int edac_idx;
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	void __iomem *pci_vbase;
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	int irq;
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};
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#endif
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