Path: blob/master/drivers/gpu/drm/i2c/ch7006_mode.c
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/*1* Copyright (C) 2009 Francisco Jerez.2* All Rights Reserved.3*4* Permission is hereby granted, free of charge, to any person obtaining5* a copy of this software and associated documentation files (the6* "Software"), to deal in the Software without restriction, including7* without limitation the rights to use, copy, modify, merge, publish,8* distribute, sublicense, and/or sell copies of the Software, and to9* permit persons to whom the Software is furnished to do so, subject to10* the following conditions:11*12* The above copyright notice and this permission notice (including the13* next paragraph) shall be included in all copies or substantial14* portions of the Software.15*16* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,17* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF18* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.19* IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE20* LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION21* OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION22* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.23*24*/2526#include "ch7006_priv.h"2728char *ch7006_tv_norm_names[] = {29[TV_NORM_PAL] = "PAL",30[TV_NORM_PAL_M] = "PAL-M",31[TV_NORM_PAL_N] = "PAL-N",32[TV_NORM_PAL_NC] = "PAL-Nc",33[TV_NORM_PAL_60] = "PAL-60",34[TV_NORM_NTSC_M] = "NTSC-M",35[TV_NORM_NTSC_J] = "NTSC-J",36};3738#define NTSC_LIKE_TIMINGS .vrefresh = 60 * fixed1/1.001, \39.vdisplay = 480, \40.vtotal = 525, \41.hvirtual = 6604243#define PAL_LIKE_TIMINGS .vrefresh = 50 * fixed1, \44.vdisplay = 576, \45.vtotal = 625, \46.hvirtual = 8104748struct ch7006_tv_norm_info ch7006_tv_norms[] = {49[TV_NORM_NTSC_M] = {50NTSC_LIKE_TIMINGS,51.black_level = 0.339 * fixed1,52.subc_freq = 3579545 * fixed1,53.dispmode = bitfs(CH7006_DISPMODE_OUTPUT_STD, NTSC),54.voffset = 0,55},56[TV_NORM_NTSC_J] = {57NTSC_LIKE_TIMINGS,58.black_level = 0.286 * fixed1,59.subc_freq = 3579545 * fixed1,60.dispmode = bitfs(CH7006_DISPMODE_OUTPUT_STD, NTSC_J),61.voffset = 0,62},63[TV_NORM_PAL] = {64PAL_LIKE_TIMINGS,65.black_level = 0.3 * fixed1,66.subc_freq = 4433618.75 * fixed1,67.dispmode = bitfs(CH7006_DISPMODE_OUTPUT_STD, PAL),68.voffset = 0,69},70[TV_NORM_PAL_M] = {71NTSC_LIKE_TIMINGS,72.black_level = 0.339 * fixed1,73.subc_freq = 3575611.433 * fixed1,74.dispmode = bitfs(CH7006_DISPMODE_OUTPUT_STD, PAL_M),75.voffset = 16,76},7778/* The following modes seem to work right but they're79* undocumented */8081[TV_NORM_PAL_N] = {82PAL_LIKE_TIMINGS,83.black_level = 0.339 * fixed1,84.subc_freq = 4433618.75 * fixed1,85.dispmode = bitfs(CH7006_DISPMODE_OUTPUT_STD, PAL),86.voffset = 0,87},88[TV_NORM_PAL_NC] = {89PAL_LIKE_TIMINGS,90.black_level = 0.3 * fixed1,91.subc_freq = 3582056.25 * fixed1,92.dispmode = bitfs(CH7006_DISPMODE_OUTPUT_STD, PAL),93.voffset = 0,94},95[TV_NORM_PAL_60] = {96NTSC_LIKE_TIMINGS,97.black_level = 0.3 * fixed1,98.subc_freq = 4433618.75 * fixed1,99.dispmode = bitfs(CH7006_DISPMODE_OUTPUT_STD, PAL_M),100.voffset = 16,101},102};103104#define __MODE(f, hd, vd, ht, vt, hsynp, vsynp, \105subc, scale, scale_mask, norm_mask, e_hd, e_vd) { \106.mode = { \107.name = #hd "x" #vd, \108.status = 0, \109.type = DRM_MODE_TYPE_DRIVER, \110.clock = f, \111.hdisplay = hd, \112.hsync_start = e_hd + 16, \113.hsync_end = e_hd + 80, \114.htotal = ht, \115.hskew = 0, \116.vdisplay = vd, \117.vsync_start = vd + 10, \118.vsync_end = vd + 26, \119.vtotal = vt, \120.vscan = 0, \121.flags = DRM_MODE_FLAG_##hsynp##HSYNC | \122DRM_MODE_FLAG_##vsynp##VSYNC, \123.vrefresh = 0, \124}, \125.enc_hdisp = e_hd, \126.enc_vdisp = e_vd, \127.subc_coeff = subc * fixed1, \128.dispmode = bitfs(CH7006_DISPMODE_SCALING_RATIO, scale) | \129bitfs(CH7006_DISPMODE_INPUT_RES, e_hd##x##e_vd), \130.valid_scales = scale_mask, \131.valid_norms = norm_mask \132}133134#define MODE(f, hd, vd, ht, vt, hsynp, vsynp, \135subc, scale, scale_mask, norm_mask) \136__MODE(f, hd, vd, ht, vt, hsynp, vsynp, subc, scale, \137scale_mask, norm_mask, hd, vd)138139#define NTSC_LIKE (1 << TV_NORM_NTSC_M | 1 << TV_NORM_NTSC_J | \1401 << TV_NORM_PAL_M | 1 << TV_NORM_PAL_60)141142#define PAL_LIKE (1 << TV_NORM_PAL | 1 << TV_NORM_PAL_N | 1 << TV_NORM_PAL_NC)143144struct ch7006_mode ch7006_modes[] = {145MODE(21000, 512, 384, 840, 500, N, N, 181.797557582, 5_4, 0x6, PAL_LIKE),146MODE(26250, 512, 384, 840, 625, N, N, 145.438046066, 1_1, 0x1, PAL_LIKE),147MODE(20140, 512, 384, 800, 420, N, N, 213.257083791, 5_4, 0x4, NTSC_LIKE),148MODE(24671, 512, 384, 784, 525, N, N, 174.0874153, 1_1, 0x3, NTSC_LIKE),149MODE(28125, 720, 400, 1125, 500, N, N, 135.742176298, 5_4, 0x6, PAL_LIKE),150MODE(34875, 720, 400, 1116, 625, N, N, 109.469496898, 1_1, 0x1, PAL_LIKE),151MODE(23790, 720, 400, 945, 420, N, N, 160.475642016, 5_4, 0x4, NTSC_LIKE),152MODE(29455, 720, 400, 936, 525, N, N, 129.614941843, 1_1, 0x3, NTSC_LIKE),153MODE(25000, 640, 400, 1000, 500, N, N, 152.709948279, 5_4, 0x6, PAL_LIKE),154MODE(31500, 640, 400, 1008, 625, N, N, 121.198371646, 1_1, 0x1, PAL_LIKE),155MODE(21147, 640, 400, 840, 420, N, N, 180.535097338, 5_4, 0x4, NTSC_LIKE),156MODE(26434, 640, 400, 840, 525, N, N, 144.42807787, 1_1, 0x2, NTSC_LIKE),157MODE(30210, 640, 400, 840, 600, N, N, 126.374568276, 7_8, 0x1, NTSC_LIKE),158MODE(21000, 640, 480, 840, 500, N, N, 181.797557582, 5_4, 0x4, PAL_LIKE),159MODE(26250, 640, 480, 840, 625, N, N, 145.438046066, 1_1, 0x2, PAL_LIKE),160MODE(31500, 640, 480, 840, 750, N, N, 121.198371646, 5_6, 0x1, PAL_LIKE),161MODE(24671, 640, 480, 784, 525, N, N, 174.0874153, 1_1, 0x4, NTSC_LIKE),162MODE(28196, 640, 480, 784, 600, N, N, 152.326488422, 7_8, 0x2, NTSC_LIKE),163MODE(30210, 640, 480, 800, 630, N, N, 142.171389101, 5_6, 0x1, NTSC_LIKE),164__MODE(29500, 720, 576, 944, 625, P, P, 145.592111636, 1_1, 0x7, PAL_LIKE, 800, 600),165MODE(36000, 800, 600, 960, 750, P, P, 119.304647022, 5_6, 0x6, PAL_LIKE),166MODE(39000, 800, 600, 936, 836, P, P, 110.127366499, 3_4, 0x1, PAL_LIKE),167MODE(39273, 800, 600, 1040, 630, P, P, 145.816809399, 5_6, 0x4, NTSC_LIKE),168MODE(43636, 800, 600, 1040, 700, P, P, 131.235128487, 3_4, 0x2, NTSC_LIKE),169MODE(47832, 800, 600, 1064, 750, P, P, 119.723275165, 7_10, 0x1, NTSC_LIKE),170{}171};172173struct ch7006_mode *ch7006_lookup_mode(struct drm_encoder *encoder,174struct drm_display_mode *drm_mode)175{176struct ch7006_priv *priv = to_ch7006_priv(encoder);177struct ch7006_mode *mode;178179for (mode = ch7006_modes; mode->mode.clock; mode++) {180181if (~mode->valid_norms & 1<<priv->norm)182continue;183184if (mode->mode.hdisplay != drm_mode->hdisplay ||185mode->mode.vdisplay != drm_mode->vdisplay ||186mode->mode.vtotal != drm_mode->vtotal ||187mode->mode.htotal != drm_mode->htotal ||188mode->mode.clock != drm_mode->clock)189continue;190191return mode;192}193194return NULL;195}196197/* Some common HW state calculation code */198199void ch7006_setup_levels(struct drm_encoder *encoder)200{201struct i2c_client *client = drm_i2c_encoder_get_client(encoder);202struct ch7006_priv *priv = to_ch7006_priv(encoder);203uint8_t *regs = priv->state.regs;204struct ch7006_tv_norm_info *norm = &ch7006_tv_norms[priv->norm];205int gain;206int black_level;207208/* Set DAC_GAIN if the voltage drop between white and black is209* high enough. */210if (norm->black_level < 339*fixed1/1000) {211gain = 76;212213regs[CH7006_INPUT_FORMAT] |= CH7006_INPUT_FORMAT_DAC_GAIN;214} else {215gain = 71;216217regs[CH7006_INPUT_FORMAT] &= ~CH7006_INPUT_FORMAT_DAC_GAIN;218}219220black_level = round_fixed(norm->black_level*26625)/gain;221222/* Correct it with the specified brightness. */223black_level = interpolate(90, black_level, 208, priv->brightness);224225regs[CH7006_BLACK_LEVEL] = bitf(CH7006_BLACK_LEVEL_0, black_level);226227ch7006_dbg(client, "black level: %d\n", black_level);228}229230void ch7006_setup_subcarrier(struct drm_encoder *encoder)231{232struct i2c_client *client = drm_i2c_encoder_get_client(encoder);233struct ch7006_priv *priv = to_ch7006_priv(encoder);234struct ch7006_state *state = &priv->state;235struct ch7006_tv_norm_info *norm = &ch7006_tv_norms[priv->norm];236struct ch7006_mode *mode = priv->mode;237uint32_t subc_inc;238239subc_inc = round_fixed((mode->subc_coeff >> 8)240* (norm->subc_freq >> 24));241242setbitf(state, CH7006_SUBC_INC0, 28, subc_inc);243setbitf(state, CH7006_SUBC_INC1, 24, subc_inc);244setbitf(state, CH7006_SUBC_INC2, 20, subc_inc);245setbitf(state, CH7006_SUBC_INC3, 16, subc_inc);246setbitf(state, CH7006_SUBC_INC4, 12, subc_inc);247setbitf(state, CH7006_SUBC_INC5, 8, subc_inc);248setbitf(state, CH7006_SUBC_INC6, 4, subc_inc);249setbitf(state, CH7006_SUBC_INC7, 0, subc_inc);250251ch7006_dbg(client, "subcarrier inc: %u\n", subc_inc);252}253254void ch7006_setup_pll(struct drm_encoder *encoder)255{256struct i2c_client *client = drm_i2c_encoder_get_client(encoder);257struct ch7006_priv *priv = to_ch7006_priv(encoder);258uint8_t *regs = priv->state.regs;259struct ch7006_mode *mode = priv->mode;260int n, best_n = 0;261int m, best_m = 0;262int freq, best_freq = 0;263264for (n = 0; n < CH7006_MAXN; n++) {265for (m = 0; m < CH7006_MAXM; m++) {266freq = CH7006_FREQ0*(n+2)/(m+2);267268if (abs(freq - mode->mode.clock) <269abs(best_freq - mode->mode.clock)) {270best_freq = freq;271best_n = n;272best_m = m;273}274}275}276277regs[CH7006_PLLOV] = bitf(CH7006_PLLOV_N_8, best_n) |278bitf(CH7006_PLLOV_M_8, best_m);279280regs[CH7006_PLLM] = bitf(CH7006_PLLM_0, best_m);281regs[CH7006_PLLN] = bitf(CH7006_PLLN_0, best_n);282283if (best_n < 108)284regs[CH7006_PLL_CONTROL] |= CH7006_PLL_CONTROL_CAPACITOR;285else286regs[CH7006_PLL_CONTROL] &= ~CH7006_PLL_CONTROL_CAPACITOR;287288ch7006_dbg(client, "n=%d m=%d f=%d c=%d\n",289best_n, best_m, best_freq, best_n < 108);290}291292void ch7006_setup_power_state(struct drm_encoder *encoder)293{294struct ch7006_priv *priv = to_ch7006_priv(encoder);295uint8_t *power = &priv->state.regs[CH7006_POWER];296int subconnector;297298subconnector = priv->select_subconnector ? priv->select_subconnector :299priv->subconnector;300301*power = CH7006_POWER_RESET;302303if (priv->last_dpms == DRM_MODE_DPMS_ON) {304switch (subconnector) {305case DRM_MODE_SUBCONNECTOR_SVIDEO:306*power |= bitfs(CH7006_POWER_LEVEL, CVBS_OFF);307break;308case DRM_MODE_SUBCONNECTOR_Composite:309*power |= bitfs(CH7006_POWER_LEVEL, SVIDEO_OFF);310break;311case DRM_MODE_SUBCONNECTOR_SCART:312*power |= bitfs(CH7006_POWER_LEVEL, NORMAL) |313CH7006_POWER_SCART;314break;315}316317} else {318if (priv->chip_version >= 0x20)319*power |= bitfs(CH7006_POWER_LEVEL, FULL_POWER_OFF);320else321*power |= bitfs(CH7006_POWER_LEVEL, POWER_OFF);322}323}324325void ch7006_setup_properties(struct drm_encoder *encoder)326{327struct i2c_client *client = drm_i2c_encoder_get_client(encoder);328struct ch7006_priv *priv = to_ch7006_priv(encoder);329struct ch7006_state *state = &priv->state;330struct ch7006_tv_norm_info *norm = &ch7006_tv_norms[priv->norm];331struct ch7006_mode *ch_mode = priv->mode;332struct drm_display_mode *mode = &ch_mode->mode;333uint8_t *regs = state->regs;334int flicker, contrast, hpos, vpos;335uint64_t scale, aspect;336337flicker = interpolate(0, 2, 3, priv->flicker);338regs[CH7006_FFILTER] = bitf(CH7006_FFILTER_TEXT, flicker) |339bitf(CH7006_FFILTER_LUMA, flicker) |340bitf(CH7006_FFILTER_CHROMA, 1);341342contrast = interpolate(0, 5, 7, priv->contrast);343regs[CH7006_CONTRAST] = bitf(CH7006_CONTRAST_0, contrast);344345scale = norm->vtotal*fixed1;346do_div(scale, mode->vtotal);347348aspect = ch_mode->enc_hdisp*fixed1;349do_div(aspect, ch_mode->enc_vdisp);350351hpos = round_fixed((norm->hvirtual * aspect - mode->hdisplay * scale)352* priv->hmargin * mode->vtotal) / norm->vtotal / 100 / 4;353354setbitf(state, CH7006_POV, HPOS_8, hpos);355setbitf(state, CH7006_HPOS, 0, hpos);356357vpos = max(0, norm->vdisplay - round_fixed(mode->vdisplay*scale)358+ norm->voffset) * priv->vmargin / 100 / 2;359360setbitf(state, CH7006_POV, VPOS_8, vpos);361setbitf(state, CH7006_VPOS, 0, vpos);362363ch7006_dbg(client, "hpos: %d, vpos: %d\n", hpos, vpos);364}365366/* HW access functions */367368void ch7006_write(struct i2c_client *client, uint8_t addr, uint8_t val)369{370uint8_t buf[] = {addr, val};371int ret;372373ret = i2c_master_send(client, buf, ARRAY_SIZE(buf));374if (ret < 0)375ch7006_err(client, "Error %d writing to subaddress 0x%x\n",376ret, addr);377}378379uint8_t ch7006_read(struct i2c_client *client, uint8_t addr)380{381uint8_t val;382int ret;383384ret = i2c_master_send(client, &addr, sizeof(addr));385if (ret < 0)386goto fail;387388ret = i2c_master_recv(client, &val, sizeof(val));389if (ret < 0)390goto fail;391392return val;393394fail:395ch7006_err(client, "Error %d reading from subaddress 0x%x\n",396ret, addr);397return 0;398}399400void ch7006_state_load(struct i2c_client *client,401struct ch7006_state *state)402{403ch7006_load_reg(client, state, CH7006_POWER);404405ch7006_load_reg(client, state, CH7006_DISPMODE);406ch7006_load_reg(client, state, CH7006_FFILTER);407ch7006_load_reg(client, state, CH7006_BWIDTH);408ch7006_load_reg(client, state, CH7006_INPUT_FORMAT);409ch7006_load_reg(client, state, CH7006_CLKMODE);410ch7006_load_reg(client, state, CH7006_START_ACTIVE);411ch7006_load_reg(client, state, CH7006_POV);412ch7006_load_reg(client, state, CH7006_BLACK_LEVEL);413ch7006_load_reg(client, state, CH7006_HPOS);414ch7006_load_reg(client, state, CH7006_VPOS);415ch7006_load_reg(client, state, CH7006_INPUT_SYNC);416ch7006_load_reg(client, state, CH7006_DETECT);417ch7006_load_reg(client, state, CH7006_CONTRAST);418ch7006_load_reg(client, state, CH7006_PLLOV);419ch7006_load_reg(client, state, CH7006_PLLM);420ch7006_load_reg(client, state, CH7006_PLLN);421ch7006_load_reg(client, state, CH7006_BCLKOUT);422ch7006_load_reg(client, state, CH7006_SUBC_INC0);423ch7006_load_reg(client, state, CH7006_SUBC_INC1);424ch7006_load_reg(client, state, CH7006_SUBC_INC2);425ch7006_load_reg(client, state, CH7006_SUBC_INC3);426ch7006_load_reg(client, state, CH7006_SUBC_INC4);427ch7006_load_reg(client, state, CH7006_SUBC_INC5);428ch7006_load_reg(client, state, CH7006_SUBC_INC6);429ch7006_load_reg(client, state, CH7006_SUBC_INC7);430ch7006_load_reg(client, state, CH7006_PLL_CONTROL);431ch7006_load_reg(client, state, CH7006_CALC_SUBC_INC0);432}433434void ch7006_state_save(struct i2c_client *client,435struct ch7006_state *state)436{437ch7006_save_reg(client, state, CH7006_POWER);438439ch7006_save_reg(client, state, CH7006_DISPMODE);440ch7006_save_reg(client, state, CH7006_FFILTER);441ch7006_save_reg(client, state, CH7006_BWIDTH);442ch7006_save_reg(client, state, CH7006_INPUT_FORMAT);443ch7006_save_reg(client, state, CH7006_CLKMODE);444ch7006_save_reg(client, state, CH7006_START_ACTIVE);445ch7006_save_reg(client, state, CH7006_POV);446ch7006_save_reg(client, state, CH7006_BLACK_LEVEL);447ch7006_save_reg(client, state, CH7006_HPOS);448ch7006_save_reg(client, state, CH7006_VPOS);449ch7006_save_reg(client, state, CH7006_INPUT_SYNC);450ch7006_save_reg(client, state, CH7006_DETECT);451ch7006_save_reg(client, state, CH7006_CONTRAST);452ch7006_save_reg(client, state, CH7006_PLLOV);453ch7006_save_reg(client, state, CH7006_PLLM);454ch7006_save_reg(client, state, CH7006_PLLN);455ch7006_save_reg(client, state, CH7006_BCLKOUT);456ch7006_save_reg(client, state, CH7006_SUBC_INC0);457ch7006_save_reg(client, state, CH7006_SUBC_INC1);458ch7006_save_reg(client, state, CH7006_SUBC_INC2);459ch7006_save_reg(client, state, CH7006_SUBC_INC3);460ch7006_save_reg(client, state, CH7006_SUBC_INC4);461ch7006_save_reg(client, state, CH7006_SUBC_INC5);462ch7006_save_reg(client, state, CH7006_SUBC_INC6);463ch7006_save_reg(client, state, CH7006_SUBC_INC7);464ch7006_save_reg(client, state, CH7006_PLL_CONTROL);465ch7006_save_reg(client, state, CH7006_CALC_SUBC_INC0);466467state->regs[CH7006_FFILTER] = (state->regs[CH7006_FFILTER] & 0xf0) |468(state->regs[CH7006_FFILTER] & 0x0c) >> 2 |469(state->regs[CH7006_FFILTER] & 0x03) << 2;470}471472473