Path: blob/master/drivers/gpu/drm/i915/i915_debugfs.c
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/*1* Copyright © 2008 Intel Corporation2*3* Permission is hereby granted, free of charge, to any person obtaining a4* copy of this software and associated documentation files (the "Software"),5* to deal in the Software without restriction, including without limitation6* the rights to use, copy, modify, merge, publish, distribute, sublicense,7* and/or sell copies of the Software, and to permit persons to whom the8* Software is furnished to do so, subject to the following conditions:9*10* The above copyright notice and this permission notice (including the next11* paragraph) shall be included in all copies or substantial portions of the12* Software.13*14* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR15* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,16* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL17* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER18* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING19* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS20* IN THE SOFTWARE.21*22* Authors:23* Eric Anholt <[email protected]>24* Keith Packard <[email protected]>25*26*/2728#include <linux/seq_file.h>29#include <linux/debugfs.h>30#include <linux/slab.h>31#include "drmP.h"32#include "drm.h"33#include "intel_drv.h"34#include "intel_ringbuffer.h"35#include "i915_drm.h"36#include "i915_drv.h"3738#define DRM_I915_RING_DEBUG 1394041#if defined(CONFIG_DEBUG_FS)4243enum {44ACTIVE_LIST,45FLUSHING_LIST,46INACTIVE_LIST,47PINNED_LIST,48DEFERRED_FREE_LIST,49};5051static const char *yesno(int v)52{53return v ? "yes" : "no";54}5556static int i915_capabilities(struct seq_file *m, void *data)57{58struct drm_info_node *node = (struct drm_info_node *) m->private;59struct drm_device *dev = node->minor->dev;60const struct intel_device_info *info = INTEL_INFO(dev);6162seq_printf(m, "gen: %d\n", info->gen);63#define B(x) seq_printf(m, #x ": %s\n", yesno(info->x))64B(is_mobile);65B(is_i85x);66B(is_i915g);67B(is_i945gm);68B(is_g33);69B(need_gfx_hws);70B(is_g4x);71B(is_pineview);72B(is_broadwater);73B(is_crestline);74B(has_fbc);75B(has_pipe_cxsr);76B(has_hotplug);77B(cursor_needs_physical);78B(has_overlay);79B(overlay_needs_physical);80B(supports_tv);81B(has_bsd_ring);82B(has_blt_ring);83#undef B8485return 0;86}8788static const char *get_pin_flag(struct drm_i915_gem_object *obj)89{90if (obj->user_pin_count > 0)91return "P";92else if (obj->pin_count > 0)93return "p";94else95return " ";96}9798static const char *get_tiling_flag(struct drm_i915_gem_object *obj)99{100switch (obj->tiling_mode) {101default:102case I915_TILING_NONE: return " ";103case I915_TILING_X: return "X";104case I915_TILING_Y: return "Y";105}106}107108static const char *cache_level_str(int type)109{110switch (type) {111case I915_CACHE_NONE: return " uncached";112case I915_CACHE_LLC: return " snooped (LLC)";113case I915_CACHE_LLC_MLC: return " snooped (LLC+MLC)";114default: return "";115}116}117118static void119describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)120{121seq_printf(m, "%p: %s%s %8zd %04x %04x %d %d%s%s%s",122&obj->base,123get_pin_flag(obj),124get_tiling_flag(obj),125obj->base.size,126obj->base.read_domains,127obj->base.write_domain,128obj->last_rendering_seqno,129obj->last_fenced_seqno,130cache_level_str(obj->cache_level),131obj->dirty ? " dirty" : "",132obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");133if (obj->base.name)134seq_printf(m, " (name: %d)", obj->base.name);135if (obj->fence_reg != I915_FENCE_REG_NONE)136seq_printf(m, " (fence: %d)", obj->fence_reg);137if (obj->gtt_space != NULL)138seq_printf(m, " (gtt offset: %08x, size: %08x)",139obj->gtt_offset, (unsigned int)obj->gtt_space->size);140if (obj->pin_mappable || obj->fault_mappable) {141char s[3], *t = s;142if (obj->pin_mappable)143*t++ = 'p';144if (obj->fault_mappable)145*t++ = 'f';146*t = '\0';147seq_printf(m, " (%s mappable)", s);148}149if (obj->ring != NULL)150seq_printf(m, " (%s)", obj->ring->name);151}152153static int i915_gem_object_list_info(struct seq_file *m, void *data)154{155struct drm_info_node *node = (struct drm_info_node *) m->private;156uintptr_t list = (uintptr_t) node->info_ent->data;157struct list_head *head;158struct drm_device *dev = node->minor->dev;159drm_i915_private_t *dev_priv = dev->dev_private;160struct drm_i915_gem_object *obj;161size_t total_obj_size, total_gtt_size;162int count, ret;163164ret = mutex_lock_interruptible(&dev->struct_mutex);165if (ret)166return ret;167168switch (list) {169case ACTIVE_LIST:170seq_printf(m, "Active:\n");171head = &dev_priv->mm.active_list;172break;173case INACTIVE_LIST:174seq_printf(m, "Inactive:\n");175head = &dev_priv->mm.inactive_list;176break;177case PINNED_LIST:178seq_printf(m, "Pinned:\n");179head = &dev_priv->mm.pinned_list;180break;181case FLUSHING_LIST:182seq_printf(m, "Flushing:\n");183head = &dev_priv->mm.flushing_list;184break;185case DEFERRED_FREE_LIST:186seq_printf(m, "Deferred free:\n");187head = &dev_priv->mm.deferred_free_list;188break;189default:190mutex_unlock(&dev->struct_mutex);191return -EINVAL;192}193194total_obj_size = total_gtt_size = count = 0;195list_for_each_entry(obj, head, mm_list) {196seq_printf(m, " ");197describe_obj(m, obj);198seq_printf(m, "\n");199total_obj_size += obj->base.size;200total_gtt_size += obj->gtt_space->size;201count++;202}203mutex_unlock(&dev->struct_mutex);204205seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",206count, total_obj_size, total_gtt_size);207return 0;208}209210#define count_objects(list, member) do { \211list_for_each_entry(obj, list, member) { \212size += obj->gtt_space->size; \213++count; \214if (obj->map_and_fenceable) { \215mappable_size += obj->gtt_space->size; \216++mappable_count; \217} \218} \219} while(0)220221static int i915_gem_object_info(struct seq_file *m, void* data)222{223struct drm_info_node *node = (struct drm_info_node *) m->private;224struct drm_device *dev = node->minor->dev;225struct drm_i915_private *dev_priv = dev->dev_private;226u32 count, mappable_count;227size_t size, mappable_size;228struct drm_i915_gem_object *obj;229int ret;230231ret = mutex_lock_interruptible(&dev->struct_mutex);232if (ret)233return ret;234235seq_printf(m, "%u objects, %zu bytes\n",236dev_priv->mm.object_count,237dev_priv->mm.object_memory);238239size = count = mappable_size = mappable_count = 0;240count_objects(&dev_priv->mm.gtt_list, gtt_list);241seq_printf(m, "%u [%u] objects, %zu [%zu] bytes in gtt\n",242count, mappable_count, size, mappable_size);243244size = count = mappable_size = mappable_count = 0;245count_objects(&dev_priv->mm.active_list, mm_list);246count_objects(&dev_priv->mm.flushing_list, mm_list);247seq_printf(m, " %u [%u] active objects, %zu [%zu] bytes\n",248count, mappable_count, size, mappable_size);249250size = count = mappable_size = mappable_count = 0;251count_objects(&dev_priv->mm.pinned_list, mm_list);252seq_printf(m, " %u [%u] pinned objects, %zu [%zu] bytes\n",253count, mappable_count, size, mappable_size);254255size = count = mappable_size = mappable_count = 0;256count_objects(&dev_priv->mm.inactive_list, mm_list);257seq_printf(m, " %u [%u] inactive objects, %zu [%zu] bytes\n",258count, mappable_count, size, mappable_size);259260size = count = mappable_size = mappable_count = 0;261count_objects(&dev_priv->mm.deferred_free_list, mm_list);262seq_printf(m, " %u [%u] freed objects, %zu [%zu] bytes\n",263count, mappable_count, size, mappable_size);264265size = count = mappable_size = mappable_count = 0;266list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list) {267if (obj->fault_mappable) {268size += obj->gtt_space->size;269++count;270}271if (obj->pin_mappable) {272mappable_size += obj->gtt_space->size;273++mappable_count;274}275}276seq_printf(m, "%u pinned mappable objects, %zu bytes\n",277mappable_count, mappable_size);278seq_printf(m, "%u fault mappable objects, %zu bytes\n",279count, size);280281seq_printf(m, "%zu [%zu] gtt total\n",282dev_priv->mm.gtt_total, dev_priv->mm.mappable_gtt_total);283284mutex_unlock(&dev->struct_mutex);285286return 0;287}288289static int i915_gem_gtt_info(struct seq_file *m, void* data)290{291struct drm_info_node *node = (struct drm_info_node *) m->private;292struct drm_device *dev = node->minor->dev;293struct drm_i915_private *dev_priv = dev->dev_private;294struct drm_i915_gem_object *obj;295size_t total_obj_size, total_gtt_size;296int count, ret;297298ret = mutex_lock_interruptible(&dev->struct_mutex);299if (ret)300return ret;301302total_obj_size = total_gtt_size = count = 0;303list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list) {304seq_printf(m, " ");305describe_obj(m, obj);306seq_printf(m, "\n");307total_obj_size += obj->base.size;308total_gtt_size += obj->gtt_space->size;309count++;310}311312mutex_unlock(&dev->struct_mutex);313314seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",315count, total_obj_size, total_gtt_size);316317return 0;318}319320321static int i915_gem_pageflip_info(struct seq_file *m, void *data)322{323struct drm_info_node *node = (struct drm_info_node *) m->private;324struct drm_device *dev = node->minor->dev;325unsigned long flags;326struct intel_crtc *crtc;327328list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {329const char pipe = pipe_name(crtc->pipe);330const char plane = plane_name(crtc->plane);331struct intel_unpin_work *work;332333spin_lock_irqsave(&dev->event_lock, flags);334work = crtc->unpin_work;335if (work == NULL) {336seq_printf(m, "No flip due on pipe %c (plane %c)\n",337pipe, plane);338} else {339if (!work->pending) {340seq_printf(m, "Flip queued on pipe %c (plane %c)\n",341pipe, plane);342} else {343seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",344pipe, plane);345}346if (work->enable_stall_check)347seq_printf(m, "Stall check enabled, ");348else349seq_printf(m, "Stall check waiting for page flip ioctl, ");350seq_printf(m, "%d prepares\n", work->pending);351352if (work->old_fb_obj) {353struct drm_i915_gem_object *obj = work->old_fb_obj;354if (obj)355seq_printf(m, "Old framebuffer gtt_offset 0x%08x\n", obj->gtt_offset);356}357if (work->pending_flip_obj) {358struct drm_i915_gem_object *obj = work->pending_flip_obj;359if (obj)360seq_printf(m, "New framebuffer gtt_offset 0x%08x\n", obj->gtt_offset);361}362}363spin_unlock_irqrestore(&dev->event_lock, flags);364}365366return 0;367}368369static int i915_gem_request_info(struct seq_file *m, void *data)370{371struct drm_info_node *node = (struct drm_info_node *) m->private;372struct drm_device *dev = node->minor->dev;373drm_i915_private_t *dev_priv = dev->dev_private;374struct drm_i915_gem_request *gem_request;375int ret, count;376377ret = mutex_lock_interruptible(&dev->struct_mutex);378if (ret)379return ret;380381count = 0;382if (!list_empty(&dev_priv->ring[RCS].request_list)) {383seq_printf(m, "Render requests:\n");384list_for_each_entry(gem_request,385&dev_priv->ring[RCS].request_list,386list) {387seq_printf(m, " %d @ %d\n",388gem_request->seqno,389(int) (jiffies - gem_request->emitted_jiffies));390}391count++;392}393if (!list_empty(&dev_priv->ring[VCS].request_list)) {394seq_printf(m, "BSD requests:\n");395list_for_each_entry(gem_request,396&dev_priv->ring[VCS].request_list,397list) {398seq_printf(m, " %d @ %d\n",399gem_request->seqno,400(int) (jiffies - gem_request->emitted_jiffies));401}402count++;403}404if (!list_empty(&dev_priv->ring[BCS].request_list)) {405seq_printf(m, "BLT requests:\n");406list_for_each_entry(gem_request,407&dev_priv->ring[BCS].request_list,408list) {409seq_printf(m, " %d @ %d\n",410gem_request->seqno,411(int) (jiffies - gem_request->emitted_jiffies));412}413count++;414}415mutex_unlock(&dev->struct_mutex);416417if (count == 0)418seq_printf(m, "No requests\n");419420return 0;421}422423static void i915_ring_seqno_info(struct seq_file *m,424struct intel_ring_buffer *ring)425{426if (ring->get_seqno) {427seq_printf(m, "Current sequence (%s): %d\n",428ring->name, ring->get_seqno(ring));429seq_printf(m, "Waiter sequence (%s): %d\n",430ring->name, ring->waiting_seqno);431seq_printf(m, "IRQ sequence (%s): %d\n",432ring->name, ring->irq_seqno);433}434}435436static int i915_gem_seqno_info(struct seq_file *m, void *data)437{438struct drm_info_node *node = (struct drm_info_node *) m->private;439struct drm_device *dev = node->minor->dev;440drm_i915_private_t *dev_priv = dev->dev_private;441int ret, i;442443ret = mutex_lock_interruptible(&dev->struct_mutex);444if (ret)445return ret;446447for (i = 0; i < I915_NUM_RINGS; i++)448i915_ring_seqno_info(m, &dev_priv->ring[i]);449450mutex_unlock(&dev->struct_mutex);451452return 0;453}454455456static int i915_interrupt_info(struct seq_file *m, void *data)457{458struct drm_info_node *node = (struct drm_info_node *) m->private;459struct drm_device *dev = node->minor->dev;460drm_i915_private_t *dev_priv = dev->dev_private;461int ret, i, pipe;462463ret = mutex_lock_interruptible(&dev->struct_mutex);464if (ret)465return ret;466467if (!HAS_PCH_SPLIT(dev)) {468seq_printf(m, "Interrupt enable: %08x\n",469I915_READ(IER));470seq_printf(m, "Interrupt identity: %08x\n",471I915_READ(IIR));472seq_printf(m, "Interrupt mask: %08x\n",473I915_READ(IMR));474for_each_pipe(pipe)475seq_printf(m, "Pipe %c stat: %08x\n",476pipe_name(pipe),477I915_READ(PIPESTAT(pipe)));478} else {479seq_printf(m, "North Display Interrupt enable: %08x\n",480I915_READ(DEIER));481seq_printf(m, "North Display Interrupt identity: %08x\n",482I915_READ(DEIIR));483seq_printf(m, "North Display Interrupt mask: %08x\n",484I915_READ(DEIMR));485seq_printf(m, "South Display Interrupt enable: %08x\n",486I915_READ(SDEIER));487seq_printf(m, "South Display Interrupt identity: %08x\n",488I915_READ(SDEIIR));489seq_printf(m, "South Display Interrupt mask: %08x\n",490I915_READ(SDEIMR));491seq_printf(m, "Graphics Interrupt enable: %08x\n",492I915_READ(GTIER));493seq_printf(m, "Graphics Interrupt identity: %08x\n",494I915_READ(GTIIR));495seq_printf(m, "Graphics Interrupt mask: %08x\n",496I915_READ(GTIMR));497}498seq_printf(m, "Interrupts received: %d\n",499atomic_read(&dev_priv->irq_received));500for (i = 0; i < I915_NUM_RINGS; i++) {501if (IS_GEN6(dev)) {502seq_printf(m, "Graphics Interrupt mask (%s): %08x\n",503dev_priv->ring[i].name,504I915_READ_IMR(&dev_priv->ring[i]));505}506i915_ring_seqno_info(m, &dev_priv->ring[i]);507}508mutex_unlock(&dev->struct_mutex);509510return 0;511}512513static int i915_gem_fence_regs_info(struct seq_file *m, void *data)514{515struct drm_info_node *node = (struct drm_info_node *) m->private;516struct drm_device *dev = node->minor->dev;517drm_i915_private_t *dev_priv = dev->dev_private;518int i, ret;519520ret = mutex_lock_interruptible(&dev->struct_mutex);521if (ret)522return ret;523524seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start);525seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);526for (i = 0; i < dev_priv->num_fence_regs; i++) {527struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;528529seq_printf(m, "Fenced object[%2d] = ", i);530if (obj == NULL)531seq_printf(m, "unused");532else533describe_obj(m, obj);534seq_printf(m, "\n");535}536537mutex_unlock(&dev->struct_mutex);538return 0;539}540541static int i915_hws_info(struct seq_file *m, void *data)542{543struct drm_info_node *node = (struct drm_info_node *) m->private;544struct drm_device *dev = node->minor->dev;545drm_i915_private_t *dev_priv = dev->dev_private;546struct intel_ring_buffer *ring;547const volatile u32 __iomem *hws;548int i;549550ring = &dev_priv->ring[(uintptr_t)node->info_ent->data];551hws = (volatile u32 __iomem *)ring->status_page.page_addr;552if (hws == NULL)553return 0;554555for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {556seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",557i * 4,558hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);559}560return 0;561}562563static void i915_dump_object(struct seq_file *m,564struct io_mapping *mapping,565struct drm_i915_gem_object *obj)566{567int page, page_count, i;568569page_count = obj->base.size / PAGE_SIZE;570for (page = 0; page < page_count; page++) {571u32 *mem = io_mapping_map_wc(mapping,572obj->gtt_offset + page * PAGE_SIZE);573for (i = 0; i < PAGE_SIZE; i += 4)574seq_printf(m, "%08x : %08x\n", i, mem[i / 4]);575io_mapping_unmap(mem);576}577}578579static int i915_batchbuffer_info(struct seq_file *m, void *data)580{581struct drm_info_node *node = (struct drm_info_node *) m->private;582struct drm_device *dev = node->minor->dev;583drm_i915_private_t *dev_priv = dev->dev_private;584struct drm_i915_gem_object *obj;585int ret;586587ret = mutex_lock_interruptible(&dev->struct_mutex);588if (ret)589return ret;590591list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list) {592if (obj->base.read_domains & I915_GEM_DOMAIN_COMMAND) {593seq_printf(m, "--- gtt_offset = 0x%08x\n", obj->gtt_offset);594i915_dump_object(m, dev_priv->mm.gtt_mapping, obj);595}596}597598mutex_unlock(&dev->struct_mutex);599return 0;600}601602static int i915_ringbuffer_data(struct seq_file *m, void *data)603{604struct drm_info_node *node = (struct drm_info_node *) m->private;605struct drm_device *dev = node->minor->dev;606drm_i915_private_t *dev_priv = dev->dev_private;607struct intel_ring_buffer *ring;608int ret;609610ret = mutex_lock_interruptible(&dev->struct_mutex);611if (ret)612return ret;613614ring = &dev_priv->ring[(uintptr_t)node->info_ent->data];615if (!ring->obj) {616seq_printf(m, "No ringbuffer setup\n");617} else {618const u8 __iomem *virt = ring->virtual_start;619uint32_t off;620621for (off = 0; off < ring->size; off += 4) {622uint32_t *ptr = (uint32_t *)(virt + off);623seq_printf(m, "%08x : %08x\n", off, *ptr);624}625}626mutex_unlock(&dev->struct_mutex);627628return 0;629}630631static int i915_ringbuffer_info(struct seq_file *m, void *data)632{633struct drm_info_node *node = (struct drm_info_node *) m->private;634struct drm_device *dev = node->minor->dev;635drm_i915_private_t *dev_priv = dev->dev_private;636struct intel_ring_buffer *ring;637638ring = &dev_priv->ring[(uintptr_t)node->info_ent->data];639if (ring->size == 0)640return 0;641642seq_printf(m, "Ring %s:\n", ring->name);643seq_printf(m, " Head : %08x\n", I915_READ_HEAD(ring) & HEAD_ADDR);644seq_printf(m, " Tail : %08x\n", I915_READ_TAIL(ring) & TAIL_ADDR);645seq_printf(m, " Size : %08x\n", ring->size);646seq_printf(m, " Active : %08x\n", intel_ring_get_active_head(ring));647seq_printf(m, " NOPID : %08x\n", I915_READ_NOPID(ring));648if (IS_GEN6(dev)) {649seq_printf(m, " Sync 0 : %08x\n", I915_READ_SYNC_0(ring));650seq_printf(m, " Sync 1 : %08x\n", I915_READ_SYNC_1(ring));651}652seq_printf(m, " Control : %08x\n", I915_READ_CTL(ring));653seq_printf(m, " Start : %08x\n", I915_READ_START(ring));654655return 0;656}657658static const char *ring_str(int ring)659{660switch (ring) {661case RING_RENDER: return " render";662case RING_BSD: return " bsd";663case RING_BLT: return " blt";664default: return "";665}666}667668static const char *pin_flag(int pinned)669{670if (pinned > 0)671return " P";672else if (pinned < 0)673return " p";674else675return "";676}677678static const char *tiling_flag(int tiling)679{680switch (tiling) {681default:682case I915_TILING_NONE: return "";683case I915_TILING_X: return " X";684case I915_TILING_Y: return " Y";685}686}687688static const char *dirty_flag(int dirty)689{690return dirty ? " dirty" : "";691}692693static const char *purgeable_flag(int purgeable)694{695return purgeable ? " purgeable" : "";696}697698static void print_error_buffers(struct seq_file *m,699const char *name,700struct drm_i915_error_buffer *err,701int count)702{703seq_printf(m, "%s [%d]:\n", name, count);704705while (count--) {706seq_printf(m, " %08x %8u %04x %04x %08x%s%s%s%s%s%s",707err->gtt_offset,708err->size,709err->read_domains,710err->write_domain,711err->seqno,712pin_flag(err->pinned),713tiling_flag(err->tiling),714dirty_flag(err->dirty),715purgeable_flag(err->purgeable),716ring_str(err->ring),717cache_level_str(err->cache_level));718719if (err->name)720seq_printf(m, " (name: %d)", err->name);721if (err->fence_reg != I915_FENCE_REG_NONE)722seq_printf(m, " (fence: %d)", err->fence_reg);723724seq_printf(m, "\n");725err++;726}727}728729static int i915_error_state(struct seq_file *m, void *unused)730{731struct drm_info_node *node = (struct drm_info_node *) m->private;732struct drm_device *dev = node->minor->dev;733drm_i915_private_t *dev_priv = dev->dev_private;734struct drm_i915_error_state *error;735unsigned long flags;736int i, page, offset, elt;737738spin_lock_irqsave(&dev_priv->error_lock, flags);739if (!dev_priv->first_error) {740seq_printf(m, "no error state collected\n");741goto out;742}743744error = dev_priv->first_error;745746seq_printf(m, "Time: %ld s %ld us\n", error->time.tv_sec,747error->time.tv_usec);748seq_printf(m, "PCI ID: 0x%04x\n", dev->pci_device);749seq_printf(m, "EIR: 0x%08x\n", error->eir);750seq_printf(m, "PGTBL_ER: 0x%08x\n", error->pgtbl_er);751if (INTEL_INFO(dev)->gen >= 6) {752seq_printf(m, "ERROR: 0x%08x\n", error->error);753seq_printf(m, "Blitter command stream:\n");754seq_printf(m, " ACTHD: 0x%08x\n", error->bcs_acthd);755seq_printf(m, " IPEIR: 0x%08x\n", error->bcs_ipeir);756seq_printf(m, " IPEHR: 0x%08x\n", error->bcs_ipehr);757seq_printf(m, " INSTDONE: 0x%08x\n", error->bcs_instdone);758seq_printf(m, " seqno: 0x%08x\n", error->bcs_seqno);759seq_printf(m, "Video (BSD) command stream:\n");760seq_printf(m, " ACTHD: 0x%08x\n", error->vcs_acthd);761seq_printf(m, " IPEIR: 0x%08x\n", error->vcs_ipeir);762seq_printf(m, " IPEHR: 0x%08x\n", error->vcs_ipehr);763seq_printf(m, " INSTDONE: 0x%08x\n", error->vcs_instdone);764seq_printf(m, " seqno: 0x%08x\n", error->vcs_seqno);765}766seq_printf(m, "Render command stream:\n");767seq_printf(m, " ACTHD: 0x%08x\n", error->acthd);768seq_printf(m, " IPEIR: 0x%08x\n", error->ipeir);769seq_printf(m, " IPEHR: 0x%08x\n", error->ipehr);770seq_printf(m, " INSTDONE: 0x%08x\n", error->instdone);771if (INTEL_INFO(dev)->gen >= 4) {772seq_printf(m, " INSTDONE1: 0x%08x\n", error->instdone1);773seq_printf(m, " INSTPS: 0x%08x\n", error->instps);774}775seq_printf(m, " INSTPM: 0x%08x\n", error->instpm);776seq_printf(m, " seqno: 0x%08x\n", error->seqno);777778for (i = 0; i < dev_priv->num_fence_regs; i++)779seq_printf(m, " fence[%d] = %08llx\n", i, error->fence[i]);780781if (error->active_bo)782print_error_buffers(m, "Active",783error->active_bo,784error->active_bo_count);785786if (error->pinned_bo)787print_error_buffers(m, "Pinned",788error->pinned_bo,789error->pinned_bo_count);790791for (i = 0; i < ARRAY_SIZE(error->batchbuffer); i++) {792if (error->batchbuffer[i]) {793struct drm_i915_error_object *obj = error->batchbuffer[i];794795seq_printf(m, "%s --- gtt_offset = 0x%08x\n",796dev_priv->ring[i].name,797obj->gtt_offset);798offset = 0;799for (page = 0; page < obj->page_count; page++) {800for (elt = 0; elt < PAGE_SIZE/4; elt++) {801seq_printf(m, "%08x : %08x\n", offset, obj->pages[page][elt]);802offset += 4;803}804}805}806}807808for (i = 0; i < ARRAY_SIZE(error->ringbuffer); i++) {809if (error->ringbuffer[i]) {810struct drm_i915_error_object *obj = error->ringbuffer[i];811seq_printf(m, "%s --- ringbuffer = 0x%08x\n",812dev_priv->ring[i].name,813obj->gtt_offset);814offset = 0;815for (page = 0; page < obj->page_count; page++) {816for (elt = 0; elt < PAGE_SIZE/4; elt++) {817seq_printf(m, "%08x : %08x\n",818offset,819obj->pages[page][elt]);820offset += 4;821}822}823}824}825826if (error->overlay)827intel_overlay_print_error_state(m, error->overlay);828829if (error->display)830intel_display_print_error_state(m, dev, error->display);831832out:833spin_unlock_irqrestore(&dev_priv->error_lock, flags);834835return 0;836}837838static int i915_rstdby_delays(struct seq_file *m, void *unused)839{840struct drm_info_node *node = (struct drm_info_node *) m->private;841struct drm_device *dev = node->minor->dev;842drm_i915_private_t *dev_priv = dev->dev_private;843u16 crstanddelay = I915_READ16(CRSTANDVID);844845seq_printf(m, "w/ctx: %d, w/o ctx: %d\n", (crstanddelay >> 8) & 0x3f, (crstanddelay & 0x3f));846847return 0;848}849850static int i915_cur_delayinfo(struct seq_file *m, void *unused)851{852struct drm_info_node *node = (struct drm_info_node *) m->private;853struct drm_device *dev = node->minor->dev;854drm_i915_private_t *dev_priv = dev->dev_private;855int ret;856857if (IS_GEN5(dev)) {858u16 rgvswctl = I915_READ16(MEMSWCTL);859u16 rgvstat = I915_READ16(MEMSTAT_ILK);860861seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);862seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);863seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>864MEMSTAT_VID_SHIFT);865seq_printf(m, "Current P-state: %d\n",866(rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);867} else if (IS_GEN6(dev)) {868u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);869u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);870u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);871u32 rpstat;872u32 rpupei, rpcurup, rpprevup;873u32 rpdownei, rpcurdown, rpprevdown;874int max_freq;875876/* RPSTAT1 is in the GT power well */877ret = mutex_lock_interruptible(&dev->struct_mutex);878if (ret)879return ret;880881gen6_gt_force_wake_get(dev_priv);882883rpstat = I915_READ(GEN6_RPSTAT1);884rpupei = I915_READ(GEN6_RP_CUR_UP_EI);885rpcurup = I915_READ(GEN6_RP_CUR_UP);886rpprevup = I915_READ(GEN6_RP_PREV_UP);887rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI);888rpcurdown = I915_READ(GEN6_RP_CUR_DOWN);889rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);890891gen6_gt_force_wake_put(dev_priv);892mutex_unlock(&dev->struct_mutex);893894seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);895seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);896seq_printf(m, "Render p-state ratio: %d\n",897(gt_perf_status & 0xff00) >> 8);898seq_printf(m, "Render p-state VID: %d\n",899gt_perf_status & 0xff);900seq_printf(m, "Render p-state limit: %d\n",901rp_state_limits & 0xff);902seq_printf(m, "CAGF: %dMHz\n", ((rpstat & GEN6_CAGF_MASK) >>903GEN6_CAGF_SHIFT) * 50);904seq_printf(m, "RP CUR UP EI: %dus\n", rpupei &905GEN6_CURICONT_MASK);906seq_printf(m, "RP CUR UP: %dus\n", rpcurup &907GEN6_CURBSYTAVG_MASK);908seq_printf(m, "RP PREV UP: %dus\n", rpprevup &909GEN6_CURBSYTAVG_MASK);910seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei &911GEN6_CURIAVG_MASK);912seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown &913GEN6_CURBSYTAVG_MASK);914seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown &915GEN6_CURBSYTAVG_MASK);916917max_freq = (rp_state_cap & 0xff0000) >> 16;918seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",919max_freq * 50);920921max_freq = (rp_state_cap & 0xff00) >> 8;922seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",923max_freq * 50);924925max_freq = rp_state_cap & 0xff;926seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",927max_freq * 50);928} else {929seq_printf(m, "no P-state info available\n");930}931932return 0;933}934935static int i915_delayfreq_table(struct seq_file *m, void *unused)936{937struct drm_info_node *node = (struct drm_info_node *) m->private;938struct drm_device *dev = node->minor->dev;939drm_i915_private_t *dev_priv = dev->dev_private;940u32 delayfreq;941int i;942943for (i = 0; i < 16; i++) {944delayfreq = I915_READ(PXVFREQ_BASE + i * 4);945seq_printf(m, "P%02dVIDFREQ: 0x%08x (VID: %d)\n", i, delayfreq,946(delayfreq & PXVFREQ_PX_MASK) >> PXVFREQ_PX_SHIFT);947}948949return 0;950}951952static inline int MAP_TO_MV(int map)953{954return 1250 - (map * 25);955}956957static int i915_inttoext_table(struct seq_file *m, void *unused)958{959struct drm_info_node *node = (struct drm_info_node *) m->private;960struct drm_device *dev = node->minor->dev;961drm_i915_private_t *dev_priv = dev->dev_private;962u32 inttoext;963int i;964965for (i = 1; i <= 32; i++) {966inttoext = I915_READ(INTTOEXT_BASE_ILK + i * 4);967seq_printf(m, "INTTOEXT%02d: 0x%08x\n", i, inttoext);968}969970return 0;971}972973static int i915_drpc_info(struct seq_file *m, void *unused)974{975struct drm_info_node *node = (struct drm_info_node *) m->private;976struct drm_device *dev = node->minor->dev;977drm_i915_private_t *dev_priv = dev->dev_private;978u32 rgvmodectl = I915_READ(MEMMODECTL);979u32 rstdbyctl = I915_READ(RSTDBYCTL);980u16 crstandvid = I915_READ16(CRSTANDVID);981982seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ?983"yes" : "no");984seq_printf(m, "Boost freq: %d\n",985(rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>986MEMMODE_BOOST_FREQ_SHIFT);987seq_printf(m, "HW control enabled: %s\n",988rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no");989seq_printf(m, "SW control enabled: %s\n",990rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no");991seq_printf(m, "Gated voltage change: %s\n",992rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no");993seq_printf(m, "Starting frequency: P%d\n",994(rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);995seq_printf(m, "Max P-state: P%d\n",996(rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);997seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));998seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));999seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));1000seq_printf(m, "Render standby enabled: %s\n",1001(rstdbyctl & RCX_SW_EXIT) ? "no" : "yes");1002seq_printf(m, "Current RS state: ");1003switch (rstdbyctl & RSX_STATUS_MASK) {1004case RSX_STATUS_ON:1005seq_printf(m, "on\n");1006break;1007case RSX_STATUS_RC1:1008seq_printf(m, "RC1\n");1009break;1010case RSX_STATUS_RC1E:1011seq_printf(m, "RC1E\n");1012break;1013case RSX_STATUS_RS1:1014seq_printf(m, "RS1\n");1015break;1016case RSX_STATUS_RS2:1017seq_printf(m, "RS2 (RC6)\n");1018break;1019case RSX_STATUS_RS3:1020seq_printf(m, "RC3 (RC6+)\n");1021break;1022default:1023seq_printf(m, "unknown\n");1024break;1025}10261027return 0;1028}10291030static int i915_fbc_status(struct seq_file *m, void *unused)1031{1032struct drm_info_node *node = (struct drm_info_node *) m->private;1033struct drm_device *dev = node->minor->dev;1034drm_i915_private_t *dev_priv = dev->dev_private;10351036if (!I915_HAS_FBC(dev)) {1037seq_printf(m, "FBC unsupported on this chipset\n");1038return 0;1039}10401041if (intel_fbc_enabled(dev)) {1042seq_printf(m, "FBC enabled\n");1043} else {1044seq_printf(m, "FBC disabled: ");1045switch (dev_priv->no_fbc_reason) {1046case FBC_NO_OUTPUT:1047seq_printf(m, "no outputs");1048break;1049case FBC_STOLEN_TOO_SMALL:1050seq_printf(m, "not enough stolen memory");1051break;1052case FBC_UNSUPPORTED_MODE:1053seq_printf(m, "mode not supported");1054break;1055case FBC_MODE_TOO_LARGE:1056seq_printf(m, "mode too large");1057break;1058case FBC_BAD_PLANE:1059seq_printf(m, "FBC unsupported on plane");1060break;1061case FBC_NOT_TILED:1062seq_printf(m, "scanout buffer not tiled");1063break;1064case FBC_MULTIPLE_PIPES:1065seq_printf(m, "multiple pipes are enabled");1066break;1067case FBC_MODULE_PARAM:1068seq_printf(m, "disabled per module param (default off)");1069break;1070default:1071seq_printf(m, "unknown reason");1072}1073seq_printf(m, "\n");1074}1075return 0;1076}10771078static int i915_sr_status(struct seq_file *m, void *unused)1079{1080struct drm_info_node *node = (struct drm_info_node *) m->private;1081struct drm_device *dev = node->minor->dev;1082drm_i915_private_t *dev_priv = dev->dev_private;1083bool sr_enabled = false;10841085if (HAS_PCH_SPLIT(dev))1086sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;1087else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev))1088sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;1089else if (IS_I915GM(dev))1090sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;1091else if (IS_PINEVIEW(dev))1092sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;10931094seq_printf(m, "self-refresh: %s\n",1095sr_enabled ? "enabled" : "disabled");10961097return 0;1098}10991100static int i915_emon_status(struct seq_file *m, void *unused)1101{1102struct drm_info_node *node = (struct drm_info_node *) m->private;1103struct drm_device *dev = node->minor->dev;1104drm_i915_private_t *dev_priv = dev->dev_private;1105unsigned long temp, chipset, gfx;1106int ret;11071108ret = mutex_lock_interruptible(&dev->struct_mutex);1109if (ret)1110return ret;11111112temp = i915_mch_val(dev_priv);1113chipset = i915_chipset_val(dev_priv);1114gfx = i915_gfx_val(dev_priv);1115mutex_unlock(&dev->struct_mutex);11161117seq_printf(m, "GMCH temp: %ld\n", temp);1118seq_printf(m, "Chipset power: %ld\n", chipset);1119seq_printf(m, "GFX power: %ld\n", gfx);1120seq_printf(m, "Total power: %ld\n", chipset + gfx);11211122return 0;1123}11241125static int i915_gfxec(struct seq_file *m, void *unused)1126{1127struct drm_info_node *node = (struct drm_info_node *) m->private;1128struct drm_device *dev = node->minor->dev;1129drm_i915_private_t *dev_priv = dev->dev_private;11301131seq_printf(m, "GFXEC: %ld\n", (unsigned long)I915_READ(0x112f4));11321133return 0;1134}11351136static int i915_opregion(struct seq_file *m, void *unused)1137{1138struct drm_info_node *node = (struct drm_info_node *) m->private;1139struct drm_device *dev = node->minor->dev;1140drm_i915_private_t *dev_priv = dev->dev_private;1141struct intel_opregion *opregion = &dev_priv->opregion;1142int ret;11431144ret = mutex_lock_interruptible(&dev->struct_mutex);1145if (ret)1146return ret;11471148if (opregion->header)1149seq_write(m, opregion->header, OPREGION_SIZE);11501151mutex_unlock(&dev->struct_mutex);11521153return 0;1154}11551156static int i915_gem_framebuffer_info(struct seq_file *m, void *data)1157{1158struct drm_info_node *node = (struct drm_info_node *) m->private;1159struct drm_device *dev = node->minor->dev;1160drm_i915_private_t *dev_priv = dev->dev_private;1161struct intel_fbdev *ifbdev;1162struct intel_framebuffer *fb;1163int ret;11641165ret = mutex_lock_interruptible(&dev->mode_config.mutex);1166if (ret)1167return ret;11681169ifbdev = dev_priv->fbdev;1170fb = to_intel_framebuffer(ifbdev->helper.fb);11711172seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, obj ",1173fb->base.width,1174fb->base.height,1175fb->base.depth,1176fb->base.bits_per_pixel);1177describe_obj(m, fb->obj);1178seq_printf(m, "\n");11791180list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) {1181if (&fb->base == ifbdev->helper.fb)1182continue;11831184seq_printf(m, "user size: %d x %d, depth %d, %d bpp, obj ",1185fb->base.width,1186fb->base.height,1187fb->base.depth,1188fb->base.bits_per_pixel);1189describe_obj(m, fb->obj);1190seq_printf(m, "\n");1191}11921193mutex_unlock(&dev->mode_config.mutex);11941195return 0;1196}11971198static int i915_context_status(struct seq_file *m, void *unused)1199{1200struct drm_info_node *node = (struct drm_info_node *) m->private;1201struct drm_device *dev = node->minor->dev;1202drm_i915_private_t *dev_priv = dev->dev_private;1203int ret;12041205ret = mutex_lock_interruptible(&dev->mode_config.mutex);1206if (ret)1207return ret;12081209if (dev_priv->pwrctx) {1210seq_printf(m, "power context ");1211describe_obj(m, dev_priv->pwrctx);1212seq_printf(m, "\n");1213}12141215if (dev_priv->renderctx) {1216seq_printf(m, "render context ");1217describe_obj(m, dev_priv->renderctx);1218seq_printf(m, "\n");1219}12201221mutex_unlock(&dev->mode_config.mutex);12221223return 0;1224}12251226static int i915_gen6_forcewake_count_info(struct seq_file *m, void *data)1227{1228struct drm_info_node *node = (struct drm_info_node *) m->private;1229struct drm_device *dev = node->minor->dev;1230struct drm_i915_private *dev_priv = dev->dev_private;12311232seq_printf(m, "forcewake count = %d\n",1233atomic_read(&dev_priv->forcewake_count));12341235return 0;1236}12371238static int1239i915_wedged_open(struct inode *inode,1240struct file *filp)1241{1242filp->private_data = inode->i_private;1243return 0;1244}12451246static ssize_t1247i915_wedged_read(struct file *filp,1248char __user *ubuf,1249size_t max,1250loff_t *ppos)1251{1252struct drm_device *dev = filp->private_data;1253drm_i915_private_t *dev_priv = dev->dev_private;1254char buf[80];1255int len;12561257len = snprintf(buf, sizeof (buf),1258"wedged : %d\n",1259atomic_read(&dev_priv->mm.wedged));12601261if (len > sizeof (buf))1262len = sizeof (buf);12631264return simple_read_from_buffer(ubuf, max, ppos, buf, len);1265}12661267static ssize_t1268i915_wedged_write(struct file *filp,1269const char __user *ubuf,1270size_t cnt,1271loff_t *ppos)1272{1273struct drm_device *dev = filp->private_data;1274char buf[20];1275int val = 1;12761277if (cnt > 0) {1278if (cnt > sizeof (buf) - 1)1279return -EINVAL;12801281if (copy_from_user(buf, ubuf, cnt))1282return -EFAULT;1283buf[cnt] = 0;12841285val = simple_strtoul(buf, NULL, 0);1286}12871288DRM_INFO("Manually setting wedged to %d\n", val);1289i915_handle_error(dev, val);12901291return cnt;1292}12931294static const struct file_operations i915_wedged_fops = {1295.owner = THIS_MODULE,1296.open = i915_wedged_open,1297.read = i915_wedged_read,1298.write = i915_wedged_write,1299.llseek = default_llseek,1300};13011302/* As the drm_debugfs_init() routines are called before dev->dev_private is1303* allocated we need to hook into the minor for release. */1304static int1305drm_add_fake_info_node(struct drm_minor *minor,1306struct dentry *ent,1307const void *key)1308{1309struct drm_info_node *node;13101311node = kmalloc(sizeof(struct drm_info_node), GFP_KERNEL);1312if (node == NULL) {1313debugfs_remove(ent);1314return -ENOMEM;1315}13161317node->minor = minor;1318node->dent = ent;1319node->info_ent = (void *) key;1320list_add(&node->list, &minor->debugfs_nodes.list);13211322return 0;1323}13241325static int i915_wedged_create(struct dentry *root, struct drm_minor *minor)1326{1327struct drm_device *dev = minor->dev;1328struct dentry *ent;13291330ent = debugfs_create_file("i915_wedged",1331S_IRUGO | S_IWUSR,1332root, dev,1333&i915_wedged_fops);1334if (IS_ERR(ent))1335return PTR_ERR(ent);13361337return drm_add_fake_info_node(minor, ent, &i915_wedged_fops);1338}13391340static int i915_forcewake_open(struct inode *inode, struct file *file)1341{1342struct drm_device *dev = inode->i_private;1343struct drm_i915_private *dev_priv = dev->dev_private;1344int ret;13451346if (!IS_GEN6(dev))1347return 0;13481349ret = mutex_lock_interruptible(&dev->struct_mutex);1350if (ret)1351return ret;1352gen6_gt_force_wake_get(dev_priv);1353mutex_unlock(&dev->struct_mutex);13541355return 0;1356}13571358int i915_forcewake_release(struct inode *inode, struct file *file)1359{1360struct drm_device *dev = inode->i_private;1361struct drm_i915_private *dev_priv = dev->dev_private;13621363if (!IS_GEN6(dev))1364return 0;13651366/*1367* It's bad that we can potentially hang userspace if struct_mutex gets1368* forever stuck. However, if we cannot acquire this lock it means that1369* almost certainly the driver has hung, is not unload-able. Therefore1370* hanging here is probably a minor inconvenience not to be seen my1371* almost every user.1372*/1373mutex_lock(&dev->struct_mutex);1374gen6_gt_force_wake_put(dev_priv);1375mutex_unlock(&dev->struct_mutex);13761377return 0;1378}13791380static const struct file_operations i915_forcewake_fops = {1381.owner = THIS_MODULE,1382.open = i915_forcewake_open,1383.release = i915_forcewake_release,1384};13851386static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)1387{1388struct drm_device *dev = minor->dev;1389struct dentry *ent;13901391ent = debugfs_create_file("i915_forcewake_user",1392S_IRUSR,1393root, dev,1394&i915_forcewake_fops);1395if (IS_ERR(ent))1396return PTR_ERR(ent);13971398return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);1399}14001401static struct drm_info_list i915_debugfs_list[] = {1402{"i915_capabilities", i915_capabilities, 0},1403{"i915_gem_objects", i915_gem_object_info, 0},1404{"i915_gem_gtt", i915_gem_gtt_info, 0},1405{"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},1406{"i915_gem_flushing", i915_gem_object_list_info, 0, (void *) FLUSHING_LIST},1407{"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},1408{"i915_gem_pinned", i915_gem_object_list_info, 0, (void *) PINNED_LIST},1409{"i915_gem_deferred_free", i915_gem_object_list_info, 0, (void *) DEFERRED_FREE_LIST},1410{"i915_gem_pageflip", i915_gem_pageflip_info, 0},1411{"i915_gem_request", i915_gem_request_info, 0},1412{"i915_gem_seqno", i915_gem_seqno_info, 0},1413{"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},1414{"i915_gem_interrupt", i915_interrupt_info, 0},1415{"i915_gem_hws", i915_hws_info, 0, (void *)RCS},1416{"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},1417{"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},1418{"i915_ringbuffer_data", i915_ringbuffer_data, 0, (void *)RCS},1419{"i915_ringbuffer_info", i915_ringbuffer_info, 0, (void *)RCS},1420{"i915_bsd_ringbuffer_data", i915_ringbuffer_data, 0, (void *)VCS},1421{"i915_bsd_ringbuffer_info", i915_ringbuffer_info, 0, (void *)VCS},1422{"i915_blt_ringbuffer_data", i915_ringbuffer_data, 0, (void *)BCS},1423{"i915_blt_ringbuffer_info", i915_ringbuffer_info, 0, (void *)BCS},1424{"i915_batchbuffers", i915_batchbuffer_info, 0},1425{"i915_error_state", i915_error_state, 0},1426{"i915_rstdby_delays", i915_rstdby_delays, 0},1427{"i915_cur_delayinfo", i915_cur_delayinfo, 0},1428{"i915_delayfreq_table", i915_delayfreq_table, 0},1429{"i915_inttoext_table", i915_inttoext_table, 0},1430{"i915_drpc_info", i915_drpc_info, 0},1431{"i915_emon_status", i915_emon_status, 0},1432{"i915_gfxec", i915_gfxec, 0},1433{"i915_fbc_status", i915_fbc_status, 0},1434{"i915_sr_status", i915_sr_status, 0},1435{"i915_opregion", i915_opregion, 0},1436{"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},1437{"i915_context_status", i915_context_status, 0},1438{"i915_gen6_forcewake_count", i915_gen6_forcewake_count_info, 0},1439};1440#define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)14411442int i915_debugfs_init(struct drm_minor *minor)1443{1444int ret;14451446ret = i915_wedged_create(minor->debugfs_root, minor);1447if (ret)1448return ret;14491450ret = i915_forcewake_create(minor->debugfs_root, minor);1451if (ret)1452return ret;14531454return drm_debugfs_create_files(i915_debugfs_list,1455I915_DEBUGFS_ENTRIES,1456minor->debugfs_root, minor);1457}14581459void i915_debugfs_cleanup(struct drm_minor *minor)1460{1461drm_debugfs_remove_files(i915_debugfs_list,1462I915_DEBUGFS_ENTRIES, minor);1463drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops,14641, minor);1465drm_debugfs_remove_files((struct drm_info_list *) &i915_wedged_fops,14661, minor);1467}14681469#endif /* CONFIG_DEBUG_FS */147014711472