Path: blob/master/drivers/gpu/drm/nouveau/nouveau_grctx.h
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#ifndef __NOUVEAU_GRCTX_H__1#define __NOUVEAU_GRCTX_H__23struct nouveau_grctx {4struct drm_device *dev;56enum {7NOUVEAU_GRCTX_PROG,8NOUVEAU_GRCTX_VALS9} mode;10void *data;1112uint32_t ctxprog_max;13uint32_t ctxprog_len;14uint32_t ctxprog_reg;15int ctxprog_label[32];16uint32_t ctxvals_pos;17uint32_t ctxvals_base;18};1920#ifdef CP_CTX21static inline void22cp_out(struct nouveau_grctx *ctx, uint32_t inst)23{24uint32_t *ctxprog = ctx->data;2526if (ctx->mode != NOUVEAU_GRCTX_PROG)27return;2829BUG_ON(ctx->ctxprog_len == ctx->ctxprog_max);30ctxprog[ctx->ctxprog_len++] = inst;31}3233static inline void34cp_lsr(struct nouveau_grctx *ctx, uint32_t val)35{36cp_out(ctx, CP_LOAD_SR | val);37}3839static inline void40cp_ctx(struct nouveau_grctx *ctx, uint32_t reg, uint32_t length)41{42ctx->ctxprog_reg = (reg - 0x00400000) >> 2;4344ctx->ctxvals_base = ctx->ctxvals_pos;45ctx->ctxvals_pos = ctx->ctxvals_base + length;4647if (length > (CP_CTX_COUNT >> CP_CTX_COUNT_SHIFT)) {48cp_lsr(ctx, length);49length = 0;50}5152cp_out(ctx, CP_CTX | (length << CP_CTX_COUNT_SHIFT) | ctx->ctxprog_reg);53}5455static inline void56cp_name(struct nouveau_grctx *ctx, int name)57{58uint32_t *ctxprog = ctx->data;59int i;6061if (ctx->mode != NOUVEAU_GRCTX_PROG)62return;6364ctx->ctxprog_label[name] = ctx->ctxprog_len;65for (i = 0; i < ctx->ctxprog_len; i++) {66if ((ctxprog[i] & 0xfff00000) != 0xff400000)67continue;68if ((ctxprog[i] & CP_BRA_IP) != ((name) << CP_BRA_IP_SHIFT))69continue;70ctxprog[i] = (ctxprog[i] & 0x00ff00ff) |71(ctx->ctxprog_len << CP_BRA_IP_SHIFT);72}73}7475static inline void76_cp_bra(struct nouveau_grctx *ctx, u32 mod, int flag, int state, int name)77{78int ip = 0;7980if (mod != 2) {81ip = ctx->ctxprog_label[name] << CP_BRA_IP_SHIFT;82if (ip == 0)83ip = 0xff000000 | (name << CP_BRA_IP_SHIFT);84}8586cp_out(ctx, CP_BRA | (mod << 18) | ip | flag |87(state ? 0 : CP_BRA_IF_CLEAR));88}89#define cp_bra(c, f, s, n) _cp_bra((c), 0, CP_FLAG_##f, CP_FLAG_##f##_##s, n)90#ifdef CP_BRA_MOD91#define cp_cal(c, f, s, n) _cp_bra((c), 1, CP_FLAG_##f, CP_FLAG_##f##_##s, n)92#define cp_ret(c, f, s) _cp_bra((c), 2, CP_FLAG_##f, CP_FLAG_##f##_##s, 0)93#endif9495static inline void96_cp_wait(struct nouveau_grctx *ctx, int flag, int state)97{98cp_out(ctx, CP_WAIT | flag | (state ? CP_WAIT_SET : 0));99}100#define cp_wait(c, f, s) _cp_wait((c), CP_FLAG_##f, CP_FLAG_##f##_##s)101102static inline void103_cp_set(struct nouveau_grctx *ctx, int flag, int state)104{105cp_out(ctx, CP_SET | flag | (state ? CP_SET_1 : 0));106}107#define cp_set(c, f, s) _cp_set((c), CP_FLAG_##f, CP_FLAG_##f##_##s)108109static inline void110cp_pos(struct nouveau_grctx *ctx, int offset)111{112ctx->ctxvals_pos = offset;113ctx->ctxvals_base = ctx->ctxvals_pos;114115cp_lsr(ctx, ctx->ctxvals_pos);116cp_out(ctx, CP_SET_CONTEXT_POINTER);117}118119static inline void120gr_def(struct nouveau_grctx *ctx, uint32_t reg, uint32_t val)121{122if (ctx->mode != NOUVEAU_GRCTX_VALS)123return;124125reg = (reg - 0x00400000) / 4;126reg = (reg - ctx->ctxprog_reg) + ctx->ctxvals_base;127128nv_wo32(ctx->data, reg * 4, val);129}130#endif131132#endif133134135