CoCalc -- t4fw_ri

GitHub Repository: awilliam/linux-vfio
Path: blob/master/drivers/infiniband/hw/cxgb4/t4fw_ri_api.h
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/*
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 * Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved.
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 *
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 * This software is available to you under a choice of one of two
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 * licenses.  You may choose to be licensed under the terms of the GNU
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 * General Public License (GPL) Version 2, available from the file
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 * COPYING in the main directory of this source tree, or the
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 * OpenIB.org BSD license below:
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 *
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 *     Redistribution and use in source and binary forms, with or
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 *     without modification, are permitted provided that the following
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 *     conditions are met:
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 *
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 *      - Redistributions of source code must retain the above
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 *        copyright notice, this list of conditions and the following
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 *        disclaimer.
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 *      - Redistributions in binary form must reproduce the above
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 *        copyright notice, this list of conditions and the following
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 *        disclaimer in the documentation and/or other materials
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 *        provided with the distribution.
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 *
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 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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 * SOFTWARE.
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 */
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#ifndef _T4FW_RI_API_H_
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#define _T4FW_RI_API_H_
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#include "t4fw_api.h"
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enum fw_ri_wr_opcode {
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	FW_RI_RDMA_WRITE		= 0x0,	/* IETF RDMAP v1.0 ... */
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	FW_RI_READ_REQ			= 0x1,
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	FW_RI_READ_RESP			= 0x2,
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	FW_RI_SEND			= 0x3,
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	FW_RI_SEND_WITH_INV		= 0x4,
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	FW_RI_SEND_WITH_SE		= 0x5,
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	FW_RI_SEND_WITH_SE_INV		= 0x6,
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	FW_RI_TERMINATE			= 0x7,
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	FW_RI_RDMA_INIT			= 0x8,	/* CHELSIO RI specific ... */
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	FW_RI_BIND_MW			= 0x9,
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	FW_RI_FAST_REGISTER		= 0xa,
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	FW_RI_LOCAL_INV			= 0xb,
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	FW_RI_QP_MODIFY			= 0xc,
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	FW_RI_BYPASS			= 0xd,
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	FW_RI_RECEIVE			= 0xe,
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	FW_RI_SGE_EC_CR_RETURN		= 0xf
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};
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enum fw_ri_wr_flags {
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	FW_RI_COMPLETION_FLAG		= 0x01,
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	FW_RI_NOTIFICATION_FLAG		= 0x02,
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	FW_RI_SOLICITED_EVENT_FLAG	= 0x04,
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	FW_RI_READ_FENCE_FLAG		= 0x08,
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	FW_RI_LOCAL_FENCE_FLAG		= 0x10,
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	FW_RI_RDMA_READ_INVALIDATE	= 0x20
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};
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enum fw_ri_mpa_attrs {
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	FW_RI_MPA_RX_MARKER_ENABLE	= 0x01,
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	FW_RI_MPA_TX_MARKER_ENABLE	= 0x02,
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	FW_RI_MPA_CRC_ENABLE		= 0x04,
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	FW_RI_MPA_IETF_ENABLE		= 0x08
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};
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enum fw_ri_qp_caps {
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	FW_RI_QP_RDMA_READ_ENABLE	= 0x01,
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	FW_RI_QP_RDMA_WRITE_ENABLE	= 0x02,
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	FW_RI_QP_BIND_ENABLE		= 0x04,
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	FW_RI_QP_FAST_REGISTER_ENABLE	= 0x08,
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	FW_RI_QP_STAG0_ENABLE		= 0x10
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};
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enum fw_ri_addr_type {
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	FW_RI_ZERO_BASED_TO		= 0x00,
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	FW_RI_VA_BASED_TO		= 0x01
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};
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enum fw_ri_mem_perms {
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	FW_RI_MEM_ACCESS_REM_WRITE	= 0x01,
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	FW_RI_MEM_ACCESS_REM_READ	= 0x02,
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	FW_RI_MEM_ACCESS_REM		= 0x03,
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	FW_RI_MEM_ACCESS_LOCAL_WRITE	= 0x04,
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	FW_RI_MEM_ACCESS_LOCAL_READ	= 0x08,
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	FW_RI_MEM_ACCESS_LOCAL		= 0x0C
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};
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enum fw_ri_stag_type {
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	FW_RI_STAG_NSMR			= 0x00,
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	FW_RI_STAG_SMR			= 0x01,
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	FW_RI_STAG_MW			= 0x02,
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	FW_RI_STAG_MW_RELAXED		= 0x03
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};
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enum fw_ri_data_op {
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	FW_RI_DATA_IMMD			= 0x81,
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	FW_RI_DATA_DSGL			= 0x82,
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	FW_RI_DATA_ISGL			= 0x83
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};
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enum fw_ri_sgl_depth {
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	FW_RI_SGL_DEPTH_MAX_SQ		= 16,
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	FW_RI_SGL_DEPTH_MAX_RQ		= 4
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};
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struct fw_ri_dsge_pair {
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	__be32	len[2];
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	__be64	addr[2];
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};
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struct fw_ri_dsgl {
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	__u8	op;
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	__u8	r1;
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	__be16	nsge;
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	__be32	len0;
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	__be64	addr0;
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#ifndef C99_NOT_SUPPORTED
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	struct fw_ri_dsge_pair sge[0];
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#endif
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};
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struct fw_ri_sge {
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	__be32 stag;
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	__be32 len;
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	__be64 to;
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};
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struct fw_ri_isgl {
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	__u8	op;
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	__u8	r1;
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	__be16	nsge;
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	__be32	r2;
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#ifndef C99_NOT_SUPPORTED
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	struct fw_ri_sge sge[0];
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#endif
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};
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struct fw_ri_immd {
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	__u8	op;
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	__u8	r1;
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	__be16	r2;
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	__be32	immdlen;
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#ifndef C99_NOT_SUPPORTED
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	__u8	data[0];
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#endif
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};
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struct fw_ri_tpte {
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	__be32 valid_to_pdid;
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	__be32 locread_to_qpid;
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	__be32 nosnoop_pbladdr;
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	__be32 len_lo;
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	__be32 va_hi;
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	__be32 va_lo_fbo;
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	__be32 dca_mwbcnt_pstag;
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	__be32 len_hi;
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};
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#define S_FW_RI_TPTE_VALID		31
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#define M_FW_RI_TPTE_VALID		0x1
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#define V_FW_RI_TPTE_VALID(x)		((x) << S_FW_RI_TPTE_VALID)
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#define G_FW_RI_TPTE_VALID(x)		\
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    (((x) >> S_FW_RI_TPTE_VALID) & M_FW_RI_TPTE_VALID)
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#define F_FW_RI_TPTE_VALID		V_FW_RI_TPTE_VALID(1U)
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#define S_FW_RI_TPTE_STAGKEY		23
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#define M_FW_RI_TPTE_STAGKEY		0xff
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#define V_FW_RI_TPTE_STAGKEY(x)		((x) << S_FW_RI_TPTE_STAGKEY)
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#define G_FW_RI_TPTE_STAGKEY(x)		\
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    (((x) >> S_FW_RI_TPTE_STAGKEY) & M_FW_RI_TPTE_STAGKEY)
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#define S_FW_RI_TPTE_STAGSTATE		22
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#define M_FW_RI_TPTE_STAGSTATE		0x1
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#define V_FW_RI_TPTE_STAGSTATE(x)	((x) << S_FW_RI_TPTE_STAGSTATE)
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#define G_FW_RI_TPTE_STAGSTATE(x)	\
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    (((x) >> S_FW_RI_TPTE_STAGSTATE) & M_FW_RI_TPTE_STAGSTATE)
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#define F_FW_RI_TPTE_STAGSTATE		V_FW_RI_TPTE_STAGSTATE(1U)
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#define S_FW_RI_TPTE_STAGTYPE		20
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#define M_FW_RI_TPTE_STAGTYPE		0x3
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#define V_FW_RI_TPTE_STAGTYPE(x)	((x) << S_FW_RI_TPTE_STAGTYPE)
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#define G_FW_RI_TPTE_STAGTYPE(x)	\
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    (((x) >> S_FW_RI_TPTE_STAGTYPE) & M_FW_RI_TPTE_STAGTYPE)
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#define S_FW_RI_TPTE_PDID		0
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#define M_FW_RI_TPTE_PDID		0xfffff
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#define V_FW_RI_TPTE_PDID(x)		((x) << S_FW_RI_TPTE_PDID)
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#define G_FW_RI_TPTE_PDID(x)		\
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    (((x) >> S_FW_RI_TPTE_PDID) & M_FW_RI_TPTE_PDID)
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#define S_FW_RI_TPTE_PERM		28
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#define M_FW_RI_TPTE_PERM		0xf
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#define V_FW_RI_TPTE_PERM(x)		((x) << S_FW_RI_TPTE_PERM)
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#define G_FW_RI_TPTE_PERM(x)		\
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    (((x) >> S_FW_RI_TPTE_PERM) & M_FW_RI_TPTE_PERM)
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#define S_FW_RI_TPTE_REMINVDIS		27
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#define M_FW_RI_TPTE_REMINVDIS		0x1
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#define V_FW_RI_TPTE_REMINVDIS(x)	((x) << S_FW_RI_TPTE_REMINVDIS)
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#define G_FW_RI_TPTE_REMINVDIS(x)	\
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    (((x) >> S_FW_RI_TPTE_REMINVDIS) & M_FW_RI_TPTE_REMINVDIS)
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#define F_FW_RI_TPTE_REMINVDIS		V_FW_RI_TPTE_REMINVDIS(1U)
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#define S_FW_RI_TPTE_ADDRTYPE		26
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#define M_FW_RI_TPTE_ADDRTYPE		1
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#define V_FW_RI_TPTE_ADDRTYPE(x)	((x) << S_FW_RI_TPTE_ADDRTYPE)
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#define G_FW_RI_TPTE_ADDRTYPE(x)	\
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    (((x) >> S_FW_RI_TPTE_ADDRTYPE) & M_FW_RI_TPTE_ADDRTYPE)
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#define F_FW_RI_TPTE_ADDRTYPE		V_FW_RI_TPTE_ADDRTYPE(1U)
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#define S_FW_RI_TPTE_MWBINDEN		25
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#define M_FW_RI_TPTE_MWBINDEN		0x1
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#define V_FW_RI_TPTE_MWBINDEN(x)	((x) << S_FW_RI_TPTE_MWBINDEN)
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#define G_FW_RI_TPTE_MWBINDEN(x)	\
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    (((x) >> S_FW_RI_TPTE_MWBINDEN) & M_FW_RI_TPTE_MWBINDEN)
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#define F_FW_RI_TPTE_MWBINDEN		V_FW_RI_TPTE_MWBINDEN(1U)
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#define S_FW_RI_TPTE_PS			20
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#define M_FW_RI_TPTE_PS			0x1f
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#define V_FW_RI_TPTE_PS(x)		((x) << S_FW_RI_TPTE_PS)
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#define G_FW_RI_TPTE_PS(x)		\
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    (((x) >> S_FW_RI_TPTE_PS) & M_FW_RI_TPTE_PS)
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#define S_FW_RI_TPTE_QPID		0
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#define M_FW_RI_TPTE_QPID		0xfffff
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#define V_FW_RI_TPTE_QPID(x)		((x) << S_FW_RI_TPTE_QPID)
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#define G_FW_RI_TPTE_QPID(x)		\
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    (((x) >> S_FW_RI_TPTE_QPID) & M_FW_RI_TPTE_QPID)
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#define S_FW_RI_TPTE_NOSNOOP		30
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#define M_FW_RI_TPTE_NOSNOOP		0x1
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#define V_FW_RI_TPTE_NOSNOOP(x)		((x) << S_FW_RI_TPTE_NOSNOOP)
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#define G_FW_RI_TPTE_NOSNOOP(x)		\
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    (((x) >> S_FW_RI_TPTE_NOSNOOP) & M_FW_RI_TPTE_NOSNOOP)
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#define F_FW_RI_TPTE_NOSNOOP		V_FW_RI_TPTE_NOSNOOP(1U)
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#define S_FW_RI_TPTE_PBLADDR		0
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#define M_FW_RI_TPTE_PBLADDR		0x1fffffff
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#define V_FW_RI_TPTE_PBLADDR(x)		((x) << S_FW_RI_TPTE_PBLADDR)
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#define G_FW_RI_TPTE_PBLADDR(x)		\
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    (((x) >> S_FW_RI_TPTE_PBLADDR) & M_FW_RI_TPTE_PBLADDR)
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#define S_FW_RI_TPTE_DCA		24
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#define M_FW_RI_TPTE_DCA		0x1f
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#define V_FW_RI_TPTE_DCA(x)		((x) << S_FW_RI_TPTE_DCA)
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#define G_FW_RI_TPTE_DCA(x)		\
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    (((x) >> S_FW_RI_TPTE_DCA) & M_FW_RI_TPTE_DCA)
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#define S_FW_RI_TPTE_MWBCNT_PSTAG	0
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#define M_FW_RI_TPTE_MWBCNT_PSTAG	0xffffff
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#define V_FW_RI_TPTE_MWBCNT_PSTAT(x)	\
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    ((x) << S_FW_RI_TPTE_MWBCNT_PSTAG)
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#define G_FW_RI_TPTE_MWBCNT_PSTAG(x)	\
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    (((x) >> S_FW_RI_TPTE_MWBCNT_PSTAG) & M_FW_RI_TPTE_MWBCNT_PSTAG)
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enum fw_ri_res_type {
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	FW_RI_RES_TYPE_SQ,
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	FW_RI_RES_TYPE_RQ,
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	FW_RI_RES_TYPE_CQ,
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};
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enum fw_ri_res_op {
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	FW_RI_RES_OP_WRITE,
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	FW_RI_RES_OP_RESET,
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};
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struct fw_ri_res {
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	union fw_ri_restype {
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		struct fw_ri_res_sqrq {
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			__u8   restype;
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			__u8   op;
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			__be16 r3;
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			__be32 eqid;
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			__be32 r4[2];
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			__be32 fetchszm_to_iqid;
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			__be32 dcaen_to_eqsize;
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			__be64 eqaddr;
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		} sqrq;
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		struct fw_ri_res_cq {
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			__u8   restype;
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			__u8   op;
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			__be16 r3;
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			__be32 iqid;
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			__be32 r4[2];
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			__be32 iqandst_to_iqandstindex;
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			__be16 iqdroprss_to_iqesize;
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			__be16 iqsize;
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			__be64 iqaddr;
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			__be32 iqns_iqro;
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			__be32 r6_lo;
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			__be64 r7;
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		} cq;
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	} u;
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};
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struct fw_ri_res_wr {
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	__be32 op_nres;
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	__be32 len16_pkd;
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	__u64  cookie;
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#ifndef C99_NOT_SUPPORTED
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	struct fw_ri_res res[0];
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#endif
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};
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#define S_FW_RI_RES_WR_NRES	0
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#define M_FW_RI_RES_WR_NRES	0xff
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#define V_FW_RI_RES_WR_NRES(x)	((x) << S_FW_RI_RES_WR_NRES)
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#define G_FW_RI_RES_WR_NRES(x)	\
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    (((x) >> S_FW_RI_RES_WR_NRES) & M_FW_RI_RES_WR_NRES)
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#define S_FW_RI_RES_WR_FETCHSZM		26
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#define M_FW_RI_RES_WR_FETCHSZM		0x1
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#define V_FW_RI_RES_WR_FETCHSZM(x)	((x) << S_FW_RI_RES_WR_FETCHSZM)
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#define G_FW_RI_RES_WR_FETCHSZM(x)	\
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    (((x) >> S_FW_RI_RES_WR_FETCHSZM) & M_FW_RI_RES_WR_FETCHSZM)
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#define F_FW_RI_RES_WR_FETCHSZM	V_FW_RI_RES_WR_FETCHSZM(1U)
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#define S_FW_RI_RES_WR_STATUSPGNS	25
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#define M_FW_RI_RES_WR_STATUSPGNS	0x1
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#define V_FW_RI_RES_WR_STATUSPGNS(x)	((x) << S_FW_RI_RES_WR_STATUSPGNS)
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#define G_FW_RI_RES_WR_STATUSPGNS(x)	\
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    (((x) >> S_FW_RI_RES_WR_STATUSPGNS) & M_FW_RI_RES_WR_STATUSPGNS)
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#define F_FW_RI_RES_WR_STATUSPGNS	V_FW_RI_RES_WR_STATUSPGNS(1U)
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#define S_FW_RI_RES_WR_STATUSPGRO	24
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#define M_FW_RI_RES_WR_STATUSPGRO	0x1
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#define V_FW_RI_RES_WR_STATUSPGRO(x)	((x) << S_FW_RI_RES_WR_STATUSPGRO)
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#define G_FW_RI_RES_WR_STATUSPGRO(x)	\
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    (((x) >> S_FW_RI_RES_WR_STATUSPGRO) & M_FW_RI_RES_WR_STATUSPGRO)
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#define F_FW_RI_RES_WR_STATUSPGRO	V_FW_RI_RES_WR_STATUSPGRO(1U)
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#define S_FW_RI_RES_WR_FETCHNS		23
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#define M_FW_RI_RES_WR_FETCHNS		0x1
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#define V_FW_RI_RES_WR_FETCHNS(x)	((x) << S_FW_RI_RES_WR_FETCHNS)
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#define G_FW_RI_RES_WR_FETCHNS(x)	\
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    (((x) >> S_FW_RI_RES_WR_FETCHNS) & M_FW_RI_RES_WR_FETCHNS)
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#define F_FW_RI_RES_WR_FETCHNS	V_FW_RI_RES_WR_FETCHNS(1U)
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#define S_FW_RI_RES_WR_FETCHRO		22
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#define M_FW_RI_RES_WR_FETCHRO		0x1
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#define V_FW_RI_RES_WR_FETCHRO(x)	((x) << S_FW_RI_RES_WR_FETCHRO)
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#define G_FW_RI_RES_WR_FETCHRO(x)	\
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    (((x) >> S_FW_RI_RES_WR_FETCHRO) & M_FW_RI_RES_WR_FETCHRO)
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#define F_FW_RI_RES_WR_FETCHRO	V_FW_RI_RES_WR_FETCHRO(1U)
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#define S_FW_RI_RES_WR_HOSTFCMODE	20
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#define M_FW_RI_RES_WR_HOSTFCMODE	0x3
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#define V_FW_RI_RES_WR_HOSTFCMODE(x)	((x) << S_FW_RI_RES_WR_HOSTFCMODE)
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#define G_FW_RI_RES_WR_HOSTFCMODE(x)	\
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    (((x) >> S_FW_RI_RES_WR_HOSTFCMODE) & M_FW_RI_RES_WR_HOSTFCMODE)
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#define S_FW_RI_RES_WR_CPRIO	19
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#define M_FW_RI_RES_WR_CPRIO	0x1
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#define V_FW_RI_RES_WR_CPRIO(x)	((x) << S_FW_RI_RES_WR_CPRIO)
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#define G_FW_RI_RES_WR_CPRIO(x)	\
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    (((x) >> S_FW_RI_RES_WR_CPRIO) & M_FW_RI_RES_WR_CPRIO)
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#define F_FW_RI_RES_WR_CPRIO	V_FW_RI_RES_WR_CPRIO(1U)
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365
#define S_FW_RI_RES_WR_ONCHIP		18
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#define M_FW_RI_RES_WR_ONCHIP		0x1
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#define V_FW_RI_RES_WR_ONCHIP(x)	((x) << S_FW_RI_RES_WR_ONCHIP)
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#define G_FW_RI_RES_WR_ONCHIP(x)	\
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    (((x) >> S_FW_RI_RES_WR_ONCHIP) & M_FW_RI_RES_WR_ONCHIP)
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#define F_FW_RI_RES_WR_ONCHIP	V_FW_RI_RES_WR_ONCHIP(1U)
371

372
#define S_FW_RI_RES_WR_PCIECHN		16
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#define M_FW_RI_RES_WR_PCIECHN		0x3
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#define V_FW_RI_RES_WR_PCIECHN(x)	((x) << S_FW_RI_RES_WR_PCIECHN)
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#define G_FW_RI_RES_WR_PCIECHN(x)	\
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    (((x) >> S_FW_RI_RES_WR_PCIECHN) & M_FW_RI_RES_WR_PCIECHN)
377

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#define S_FW_RI_RES_WR_IQID	0
379
#define M_FW_RI_RES_WR_IQID	0xffff
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#define V_FW_RI_RES_WR_IQID(x)	((x) << S_FW_RI_RES_WR_IQID)
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#define G_FW_RI_RES_WR_IQID(x)	\
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    (((x) >> S_FW_RI_RES_WR_IQID) & M_FW_RI_RES_WR_IQID)
383

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#define S_FW_RI_RES_WR_DCAEN	31
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#define M_FW_RI_RES_WR_DCAEN	0x1
386
#define V_FW_RI_RES_WR_DCAEN(x)	((x) << S_FW_RI_RES_WR_DCAEN)
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#define G_FW_RI_RES_WR_DCAEN(x)	\
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    (((x) >> S_FW_RI_RES_WR_DCAEN) & M_FW_RI_RES_WR_DCAEN)
389
#define F_FW_RI_RES_WR_DCAEN	V_FW_RI_RES_WR_DCAEN(1U)
390

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#define S_FW_RI_RES_WR_DCACPU		26
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#define M_FW_RI_RES_WR_DCACPU		0x1f
393
#define V_FW_RI_RES_WR_DCACPU(x)	((x) << S_FW_RI_RES_WR_DCACPU)
394
#define G_FW_RI_RES_WR_DCACPU(x)	\
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    (((x) >> S_FW_RI_RES_WR_DCACPU) & M_FW_RI_RES_WR_DCACPU)
396

397
#define S_FW_RI_RES_WR_FBMIN	23
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#define M_FW_RI_RES_WR_FBMIN	0x7
399
#define V_FW_RI_RES_WR_FBMIN(x)	((x) << S_FW_RI_RES_WR_FBMIN)
400
#define G_FW_RI_RES_WR_FBMIN(x)	\
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    (((x) >> S_FW_RI_RES_WR_FBMIN) & M_FW_RI_RES_WR_FBMIN)
402

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#define S_FW_RI_RES_WR_FBMAX	20
404
#define M_FW_RI_RES_WR_FBMAX	0x7
405
#define V_FW_RI_RES_WR_FBMAX(x)	((x) << S_FW_RI_RES_WR_FBMAX)
406
#define G_FW_RI_RES_WR_FBMAX(x)	\
407
    (((x) >> S_FW_RI_RES_WR_FBMAX) & M_FW_RI_RES_WR_FBMAX)
408

409
#define S_FW_RI_RES_WR_CIDXFTHRESHO	19
410
#define M_FW_RI_RES_WR_CIDXFTHRESHO	0x1
411
#define V_FW_RI_RES_WR_CIDXFTHRESHO(x)	((x) << S_FW_RI_RES_WR_CIDXFTHRESHO)
412
#define G_FW_RI_RES_WR_CIDXFTHRESHO(x)	\
413
    (((x) >> S_FW_RI_RES_WR_CIDXFTHRESHO) & M_FW_RI_RES_WR_CIDXFTHRESHO)
414
#define F_FW_RI_RES_WR_CIDXFTHRESHO	V_FW_RI_RES_WR_CIDXFTHRESHO(1U)
415

416
#define S_FW_RI_RES_WR_CIDXFTHRESH	16
417
#define M_FW_RI_RES_WR_CIDXFTHRESH	0x7
418
#define V_FW_RI_RES_WR_CIDXFTHRESH(x)	((x) << S_FW_RI_RES_WR_CIDXFTHRESH)
419
#define G_FW_RI_RES_WR_CIDXFTHRESH(x)	\
420
    (((x) >> S_FW_RI_RES_WR_CIDXFTHRESH) & M_FW_RI_RES_WR_CIDXFTHRESH)
421

422
#define S_FW_RI_RES_WR_EQSIZE		0
423
#define M_FW_RI_RES_WR_EQSIZE		0xffff
424
#define V_FW_RI_RES_WR_EQSIZE(x)	((x) << S_FW_RI_RES_WR_EQSIZE)
425
#define G_FW_RI_RES_WR_EQSIZE(x)	\
426
    (((x) >> S_FW_RI_RES_WR_EQSIZE) & M_FW_RI_RES_WR_EQSIZE)
427

428
#define S_FW_RI_RES_WR_IQANDST		15
429
#define M_FW_RI_RES_WR_IQANDST		0x1
430
#define V_FW_RI_RES_WR_IQANDST(x)	((x) << S_FW_RI_RES_WR_IQANDST)
431
#define G_FW_RI_RES_WR_IQANDST(x)	\
432
    (((x) >> S_FW_RI_RES_WR_IQANDST) & M_FW_RI_RES_WR_IQANDST)
433
#define F_FW_RI_RES_WR_IQANDST	V_FW_RI_RES_WR_IQANDST(1U)
434

435
#define S_FW_RI_RES_WR_IQANUS		14
436
#define M_FW_RI_RES_WR_IQANUS		0x1
437
#define V_FW_RI_RES_WR_IQANUS(x)	((x) << S_FW_RI_RES_WR_IQANUS)
438
#define G_FW_RI_RES_WR_IQANUS(x)	\
439
    (((x) >> S_FW_RI_RES_WR_IQANUS) & M_FW_RI_RES_WR_IQANUS)
440
#define F_FW_RI_RES_WR_IQANUS	V_FW_RI_RES_WR_IQANUS(1U)
441

442
#define S_FW_RI_RES_WR_IQANUD		12
443
#define M_FW_RI_RES_WR_IQANUD		0x3
444
#define V_FW_RI_RES_WR_IQANUD(x)	((x) << S_FW_RI_RES_WR_IQANUD)
445
#define G_FW_RI_RES_WR_IQANUD(x)	\
446
    (((x) >> S_FW_RI_RES_WR_IQANUD) & M_FW_RI_RES_WR_IQANUD)
447

448
#define S_FW_RI_RES_WR_IQANDSTINDEX	0
449
#define M_FW_RI_RES_WR_IQANDSTINDEX	0xfff
450
#define V_FW_RI_RES_WR_IQANDSTINDEX(x)	((x) << S_FW_RI_RES_WR_IQANDSTINDEX)
451
#define G_FW_RI_RES_WR_IQANDSTINDEX(x)	\
452
    (((x) >> S_FW_RI_RES_WR_IQANDSTINDEX) & M_FW_RI_RES_WR_IQANDSTINDEX)
453

454
#define S_FW_RI_RES_WR_IQDROPRSS	15
455
#define M_FW_RI_RES_WR_IQDROPRSS	0x1
456
#define V_FW_RI_RES_WR_IQDROPRSS(x)	((x) << S_FW_RI_RES_WR_IQDROPRSS)
457
#define G_FW_RI_RES_WR_IQDROPRSS(x)	\
458
    (((x) >> S_FW_RI_RES_WR_IQDROPRSS) & M_FW_RI_RES_WR_IQDROPRSS)
459
#define F_FW_RI_RES_WR_IQDROPRSS	V_FW_RI_RES_WR_IQDROPRSS(1U)
460

461
#define S_FW_RI_RES_WR_IQGTSMODE	14
462
#define M_FW_RI_RES_WR_IQGTSMODE	0x1
463
#define V_FW_RI_RES_WR_IQGTSMODE(x)	((x) << S_FW_RI_RES_WR_IQGTSMODE)
464
#define G_FW_RI_RES_WR_IQGTSMODE(x)	\
465
    (((x) >> S_FW_RI_RES_WR_IQGTSMODE) & M_FW_RI_RES_WR_IQGTSMODE)
466
#define F_FW_RI_RES_WR_IQGTSMODE	V_FW_RI_RES_WR_IQGTSMODE(1U)
467

468
#define S_FW_RI_RES_WR_IQPCIECH		12
469
#define M_FW_RI_RES_WR_IQPCIECH		0x3
470
#define V_FW_RI_RES_WR_IQPCIECH(x)	((x) << S_FW_RI_RES_WR_IQPCIECH)
471
#define G_FW_RI_RES_WR_IQPCIECH(x)	\
472
    (((x) >> S_FW_RI_RES_WR_IQPCIECH) & M_FW_RI_RES_WR_IQPCIECH)
473

474
#define S_FW_RI_RES_WR_IQDCAEN		11
475
#define M_FW_RI_RES_WR_IQDCAEN		0x1
476
#define V_FW_RI_RES_WR_IQDCAEN(x)	((x) << S_FW_RI_RES_WR_IQDCAEN)
477
#define G_FW_RI_RES_WR_IQDCAEN(x)	\
478
    (((x) >> S_FW_RI_RES_WR_IQDCAEN) & M_FW_RI_RES_WR_IQDCAEN)
479
#define F_FW_RI_RES_WR_IQDCAEN	V_FW_RI_RES_WR_IQDCAEN(1U)
480

481
#define S_FW_RI_RES_WR_IQDCACPU		6
482
#define M_FW_RI_RES_WR_IQDCACPU		0x1f
483
#define V_FW_RI_RES_WR_IQDCACPU(x)	((x) << S_FW_RI_RES_WR_IQDCACPU)
484
#define G_FW_RI_RES_WR_IQDCACPU(x)	\
485
    (((x) >> S_FW_RI_RES_WR_IQDCACPU) & M_FW_RI_RES_WR_IQDCACPU)
486

487
#define S_FW_RI_RES_WR_IQINTCNTTHRESH		4
488
#define M_FW_RI_RES_WR_IQINTCNTTHRESH		0x3
489
#define V_FW_RI_RES_WR_IQINTCNTTHRESH(x)	\
490
    ((x) << S_FW_RI_RES_WR_IQINTCNTTHRESH)
491
#define G_FW_RI_RES_WR_IQINTCNTTHRESH(x)	\
492
    (((x) >> S_FW_RI_RES_WR_IQINTCNTTHRESH) & M_FW_RI_RES_WR_IQINTCNTTHRESH)
493

494
#define S_FW_RI_RES_WR_IQO	3
495
#define M_FW_RI_RES_WR_IQO	0x1
496
#define V_FW_RI_RES_WR_IQO(x)	((x) << S_FW_RI_RES_WR_IQO)
497
#define G_FW_RI_RES_WR_IQO(x)	\
498
    (((x) >> S_FW_RI_RES_WR_IQO) & M_FW_RI_RES_WR_IQO)
499
#define F_FW_RI_RES_WR_IQO	V_FW_RI_RES_WR_IQO(1U)
500

501
#define S_FW_RI_RES_WR_IQCPRIO		2
502
#define M_FW_RI_RES_WR_IQCPRIO		0x1
503
#define V_FW_RI_RES_WR_IQCPRIO(x)	((x) << S_FW_RI_RES_WR_IQCPRIO)
504
#define G_FW_RI_RES_WR_IQCPRIO(x)	\
505
    (((x) >> S_FW_RI_RES_WR_IQCPRIO) & M_FW_RI_RES_WR_IQCPRIO)
506
#define F_FW_RI_RES_WR_IQCPRIO	V_FW_RI_RES_WR_IQCPRIO(1U)
507

508
#define S_FW_RI_RES_WR_IQESIZE		0
509
#define M_FW_RI_RES_WR_IQESIZE		0x3
510
#define V_FW_RI_RES_WR_IQESIZE(x)	((x) << S_FW_RI_RES_WR_IQESIZE)
511
#define G_FW_RI_RES_WR_IQESIZE(x)	\
512
    (((x) >> S_FW_RI_RES_WR_IQESIZE) & M_FW_RI_RES_WR_IQESIZE)
513

514
#define S_FW_RI_RES_WR_IQNS	31
515
#define M_FW_RI_RES_WR_IQNS	0x1
516
#define V_FW_RI_RES_WR_IQNS(x)	((x) << S_FW_RI_RES_WR_IQNS)
517
#define G_FW_RI_RES_WR_IQNS(x)	\
518
    (((x) >> S_FW_RI_RES_WR_IQNS) & M_FW_RI_RES_WR_IQNS)
519
#define F_FW_RI_RES_WR_IQNS	V_FW_RI_RES_WR_IQNS(1U)
520

521
#define S_FW_RI_RES_WR_IQRO	30
522
#define M_FW_RI_RES_WR_IQRO	0x1
523
#define V_FW_RI_RES_WR_IQRO(x)	((x) << S_FW_RI_RES_WR_IQRO)
524
#define G_FW_RI_RES_WR_IQRO(x)	\
525
    (((x) >> S_FW_RI_RES_WR_IQRO) & M_FW_RI_RES_WR_IQRO)
526
#define F_FW_RI_RES_WR_IQRO	V_FW_RI_RES_WR_IQRO(1U)
527

528
struct fw_ri_rdma_write_wr {
529
	__u8   opcode;
530
	__u8   flags;
531
	__u16  wrid;
532
	__u8   r1[3];
533
	__u8   len16;
534
	__be64 r2;
535
	__be32 plen;
536
	__be32 stag_sink;
537
	__be64 to_sink;
538
#ifndef C99_NOT_SUPPORTED
539
	union {
540
		struct fw_ri_immd immd_src[0];
541
		struct fw_ri_isgl isgl_src[0];
542
	} u;
543
#endif
544
};
545

546
struct fw_ri_send_wr {
547
	__u8   opcode;
548
	__u8   flags;
549
	__u16  wrid;
550
	__u8   r1[3];
551
	__u8   len16;
552
	__be32 sendop_pkd;
553
	__be32 stag_inv;
554
	__be32 plen;
555
	__be32 r3;
556
	__be64 r4;
557
#ifndef C99_NOT_SUPPORTED
558
	union {
559
		struct fw_ri_immd immd_src[0];
560
		struct fw_ri_isgl isgl_src[0];
561
	} u;
562
#endif
563
};
564

565
#define S_FW_RI_SEND_WR_SENDOP		0
566
#define M_FW_RI_SEND_WR_SENDOP		0xf
567
#define V_FW_RI_SEND_WR_SENDOP(x)	((x) << S_FW_RI_SEND_WR_SENDOP)
568
#define G_FW_RI_SEND_WR_SENDOP(x)	\
569
    (((x) >> S_FW_RI_SEND_WR_SENDOP) & M_FW_RI_SEND_WR_SENDOP)
570

571
struct fw_ri_rdma_read_wr {
572
	__u8   opcode;
573
	__u8   flags;
574
	__u16  wrid;
575
	__u8   r1[3];
576
	__u8   len16;
577
	__be64 r2;
578
	__be32 stag_sink;
579
	__be32 to_sink_hi;
580
	__be32 to_sink_lo;
581
	__be32 plen;
582
	__be32 stag_src;
583
	__be32 to_src_hi;
584
	__be32 to_src_lo;
585
	__be32 r5;
586
};
587

588
struct fw_ri_recv_wr {
589
	__u8   opcode;
590
	__u8   r1;
591
	__u16  wrid;
592
	__u8   r2[3];
593
	__u8   len16;
594
	struct fw_ri_isgl isgl;
595
};
596

597
struct fw_ri_bind_mw_wr {
598
	__u8   opcode;
599
	__u8   flags;
600
	__u16  wrid;
601
	__u8   r1[3];
602
	__u8   len16;
603
	__u8   qpbinde_to_dcacpu;
604
	__u8   pgsz_shift;
605
	__u8   addr_type;
606
	__u8   mem_perms;
607
	__be32 stag_mr;
608
	__be32 stag_mw;
609
	__be32 r3;
610
	__be64 len_mw;
611
	__be64 va_fbo;
612
	__be64 r4;
613
};
614

615
#define S_FW_RI_BIND_MW_WR_QPBINDE	6
616
#define M_FW_RI_BIND_MW_WR_QPBINDE	0x1
617
#define V_FW_RI_BIND_MW_WR_QPBINDE(x)	((x) << S_FW_RI_BIND_MW_WR_QPBINDE)
618
#define G_FW_RI_BIND_MW_WR_QPBINDE(x)	\
619
    (((x) >> S_FW_RI_BIND_MW_WR_QPBINDE) & M_FW_RI_BIND_MW_WR_QPBINDE)
620
#define F_FW_RI_BIND_MW_WR_QPBINDE	V_FW_RI_BIND_MW_WR_QPBINDE(1U)
621

622
#define S_FW_RI_BIND_MW_WR_NS		5
623
#define M_FW_RI_BIND_MW_WR_NS		0x1
624
#define V_FW_RI_BIND_MW_WR_NS(x)	((x) << S_FW_RI_BIND_MW_WR_NS)
625
#define G_FW_RI_BIND_MW_WR_NS(x)	\
626
    (((x) >> S_FW_RI_BIND_MW_WR_NS) & M_FW_RI_BIND_MW_WR_NS)
627
#define F_FW_RI_BIND_MW_WR_NS	V_FW_RI_BIND_MW_WR_NS(1U)
628

629
#define S_FW_RI_BIND_MW_WR_DCACPU	0
630
#define M_FW_RI_BIND_MW_WR_DCACPU	0x1f
631
#define V_FW_RI_BIND_MW_WR_DCACPU(x)	((x) << S_FW_RI_BIND_MW_WR_DCACPU)
632
#define G_FW_RI_BIND_MW_WR_DCACPU(x)	\
633
    (((x) >> S_FW_RI_BIND_MW_WR_DCACPU) & M_FW_RI_BIND_MW_WR_DCACPU)
634

635
struct fw_ri_fr_nsmr_wr {
636
	__u8   opcode;
637
	__u8   flags;
638
	__u16  wrid;
639
	__u8   r1[3];
640
	__u8   len16;
641
	__u8   qpbinde_to_dcacpu;
642
	__u8   pgsz_shift;
643
	__u8   addr_type;
644
	__u8   mem_perms;
645
	__be32 stag;
646
	__be32 len_hi;
647
	__be32 len_lo;
648
	__be32 va_hi;
649
	__be32 va_lo_fbo;
650
};
651

652
#define S_FW_RI_FR_NSMR_WR_QPBINDE	6
653
#define M_FW_RI_FR_NSMR_WR_QPBINDE	0x1
654
#define V_FW_RI_FR_NSMR_WR_QPBINDE(x)	((x) << S_FW_RI_FR_NSMR_WR_QPBINDE)
655
#define G_FW_RI_FR_NSMR_WR_QPBINDE(x)	\
656
    (((x) >> S_FW_RI_FR_NSMR_WR_QPBINDE) & M_FW_RI_FR_NSMR_WR_QPBINDE)
657
#define F_FW_RI_FR_NSMR_WR_QPBINDE	V_FW_RI_FR_NSMR_WR_QPBINDE(1U)
658

659
#define S_FW_RI_FR_NSMR_WR_NS		5
660
#define M_FW_RI_FR_NSMR_WR_NS		0x1
661
#define V_FW_RI_FR_NSMR_WR_NS(x)	((x) << S_FW_RI_FR_NSMR_WR_NS)
662
#define G_FW_RI_FR_NSMR_WR_NS(x)	\
663
    (((x) >> S_FW_RI_FR_NSMR_WR_NS) & M_FW_RI_FR_NSMR_WR_NS)
664
#define F_FW_RI_FR_NSMR_WR_NS	V_FW_RI_FR_NSMR_WR_NS(1U)
665

666
#define S_FW_RI_FR_NSMR_WR_DCACPU	0
667
#define M_FW_RI_FR_NSMR_WR_DCACPU	0x1f
668
#define V_FW_RI_FR_NSMR_WR_DCACPU(x)	((x) << S_FW_RI_FR_NSMR_WR_DCACPU)
669
#define G_FW_RI_FR_NSMR_WR_DCACPU(x)	\
670
    (((x) >> S_FW_RI_FR_NSMR_WR_DCACPU) & M_FW_RI_FR_NSMR_WR_DCACPU)
671

672
struct fw_ri_inv_lstag_wr {
673
	__u8   opcode;
674
	__u8   flags;
675
	__u16  wrid;
676
	__u8   r1[3];
677
	__u8   len16;
678
	__be32 r2;
679
	__be32 stag_inv;
680
};
681

682
enum fw_ri_type {
683
	FW_RI_TYPE_INIT,
684
	FW_RI_TYPE_FINI,
685
	FW_RI_TYPE_TERMINATE
686
};
687

688
enum fw_ri_init_p2ptype {
689
	FW_RI_INIT_P2PTYPE_RDMA_WRITE		= FW_RI_RDMA_WRITE,
690
	FW_RI_INIT_P2PTYPE_READ_REQ		= FW_RI_READ_REQ,
691
	FW_RI_INIT_P2PTYPE_SEND			= FW_RI_SEND,
692
	FW_RI_INIT_P2PTYPE_SEND_WITH_INV	= FW_RI_SEND_WITH_INV,
693
	FW_RI_INIT_P2PTYPE_SEND_WITH_SE		= FW_RI_SEND_WITH_SE,
694
	FW_RI_INIT_P2PTYPE_SEND_WITH_SE_INV	= FW_RI_SEND_WITH_SE_INV,
695
	FW_RI_INIT_P2PTYPE_DISABLED		= 0xf,
696
};
697

698
struct fw_ri_wr {
699
	__be32 op_compl;
700
	__be32 flowid_len16;
701
	__u64  cookie;
702
	union fw_ri {
703
		struct fw_ri_init {
704
			__u8   type;
705
			__u8   mpareqbit_p2ptype;
706
			__u8   r4[2];
707
			__u8   mpa_attrs;
708
			__u8   qp_caps;
709
			__be16 nrqe;
710
			__be32 pdid;
711
			__be32 qpid;
712
			__be32 sq_eqid;
713
			__be32 rq_eqid;
714
			__be32 scqid;
715
			__be32 rcqid;
716
			__be32 ord_max;
717
			__be32 ird_max;
718
			__be32 iss;
719
			__be32 irs;
720
			__be32 hwrqsize;
721
			__be32 hwrqaddr;
722
			__be64 r5;
723
			union fw_ri_init_p2p {
724
				struct fw_ri_rdma_write_wr write;
725
				struct fw_ri_rdma_read_wr read;
726
				struct fw_ri_send_wr send;
727
			} u;
728
		} init;
729
		struct fw_ri_fini {
730
			__u8   type;
731
			__u8   r3[7];
732
			__be64 r4;
733
		} fini;
734
		struct fw_ri_terminate {
735
			__u8   type;
736
			__u8   r3[3];
737
			__be32 immdlen;
738
			__u8   termmsg[40];
739
		} terminate;
740
	} u;
741
};
742

743
#define S_FW_RI_WR_MPAREQBIT	7
744
#define M_FW_RI_WR_MPAREQBIT	0x1
745
#define V_FW_RI_WR_MPAREQBIT(x)	((x) << S_FW_RI_WR_MPAREQBIT)
746
#define G_FW_RI_WR_MPAREQBIT(x)	\
747
    (((x) >> S_FW_RI_WR_MPAREQBIT) & M_FW_RI_WR_MPAREQBIT)
748
#define F_FW_RI_WR_MPAREQBIT	V_FW_RI_WR_MPAREQBIT(1U)
749

750
#define S_FW_RI_WR_P2PTYPE	0
751
#define M_FW_RI_WR_P2PTYPE	0xf
752
#define V_FW_RI_WR_P2PTYPE(x)	((x) << S_FW_RI_WR_P2PTYPE)
753
#define G_FW_RI_WR_P2PTYPE(x)	\
754
    (((x) >> S_FW_RI_WR_P2PTYPE) & M_FW_RI_WR_P2PTYPE)
755

756
struct tcp_options {
757
	__be16 mss;
758
	__u8 wsf;
759
#if defined(__LITTLE_ENDIAN_BITFIELD)
760
	__u8:4;
761
	__u8 unknown:1;
762
	__u8:1;
763
	__u8 sack:1;
764
	__u8 tstamp:1;
765
#else
766
	__u8 tstamp:1;
767
	__u8 sack:1;
768
	__u8:1;
769
	__u8 unknown:1;
770
	__u8:4;
771
#endif
772
};
773

774
struct cpl_pass_accept_req {
775
	union opcode_tid ot;
776
	__be16 rsvd;
777
	__be16 len;
778
	__be32 hdr_len;
779
	__be16 vlan;
780
	__be16 l2info;
781
	__be32 tos_stid;
782
	struct tcp_options tcpopt;
783
};
784

785
/* cpl_pass_accept_req.hdr_len fields */
786
#define S_SYN_RX_CHAN    0
787
#define M_SYN_RX_CHAN    0xF
788
#define V_SYN_RX_CHAN(x) ((x) << S_SYN_RX_CHAN)
789
#define G_SYN_RX_CHAN(x) (((x) >> S_SYN_RX_CHAN) & M_SYN_RX_CHAN)
790

791
#define S_TCP_HDR_LEN    10
792
#define M_TCP_HDR_LEN    0x3F
793
#define V_TCP_HDR_LEN(x) ((x) << S_TCP_HDR_LEN)
794
#define G_TCP_HDR_LEN(x) (((x) >> S_TCP_HDR_LEN) & M_TCP_HDR_LEN)
795

796
#define S_IP_HDR_LEN    16
797
#define M_IP_HDR_LEN    0x3FF
798
#define V_IP_HDR_LEN(x) ((x) << S_IP_HDR_LEN)
799
#define G_IP_HDR_LEN(x) (((x) >> S_IP_HDR_LEN) & M_IP_HDR_LEN)
800

801
#define S_ETH_HDR_LEN    26
802
#define M_ETH_HDR_LEN    0x1F
803
#define V_ETH_HDR_LEN(x) ((x) << S_ETH_HDR_LEN)
804
#define G_ETH_HDR_LEN(x) (((x) >> S_ETH_HDR_LEN) & M_ETH_HDR_LEN)
805

806
/* cpl_pass_accept_req.l2info fields */
807
#define S_SYN_MAC_IDX    0
808
#define M_SYN_MAC_IDX    0x1FF
809
#define V_SYN_MAC_IDX(x) ((x) << S_SYN_MAC_IDX)
810
#define G_SYN_MAC_IDX(x) (((x) >> S_SYN_MAC_IDX) & M_SYN_MAC_IDX)
811

812
#define S_SYN_XACT_MATCH    9
813
#define V_SYN_XACT_MATCH(x) ((x) << S_SYN_XACT_MATCH)
814
#define F_SYN_XACT_MATCH    V_SYN_XACT_MATCH(1U)
815

816
#define S_SYN_INTF    12
817
#define M_SYN_INTF    0xF
818
#define V_SYN_INTF(x) ((x) << S_SYN_INTF)
819
#define G_SYN_INTF(x) (((x) >> S_SYN_INTF) & M_SYN_INTF)
820

821
struct ulptx_idata {
822
	__be32 cmd_more;
823
	__be32 len;
824
};
825

826
#define S_ULPTX_NSGE    0
827
#define M_ULPTX_NSGE    0xFFFF
828
#define V_ULPTX_NSGE(x) ((x) << S_ULPTX_NSGE)
829

830
#define S_RX_DACK_MODE    29
831
#define M_RX_DACK_MODE    0x3
832
#define V_RX_DACK_MODE(x) ((x) << S_RX_DACK_MODE)
833
#define G_RX_DACK_MODE(x) (((x) >> S_RX_DACK_MODE) & M_RX_DACK_MODE)
834

835
#define S_RX_DACK_CHANGE    31
836
#define V_RX_DACK_CHANGE(x) ((x) << S_RX_DACK_CHANGE)
837
#define F_RX_DACK_CHANGE    V_RX_DACK_CHANGE(1U)
838

839
#endif /* _T4FW_RI_API_H_ */
840

841
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