CoCalc -- ehca_classes

GitHub Repository: awilliam/linux-vfio
Path: blob/master/drivers/infiniband/hw/ehca/ehca_classes_pSeries.h
¹⁵¹¹² views
1
/*
2
 *  IBM eServer eHCA Infiniband device driver for Linux on POWER
3
 *
4
 *  pSeries interface definitions
5
 *
6
 *  Authors: Waleri Fomin <[email protected]>
7
 *           Christoph Raisch <[email protected]>
8
 *
9
 *  Copyright (c) 2005 IBM Corporation
10
 *
11
 *  All rights reserved.
12
 *
13
 *  This source code is distributed under a dual license of GPL v2.0 and OpenIB
14
 *  BSD.
15
 *
16
 * OpenIB BSD License
17
 *
18
 * Redistribution and use in source and binary forms, with or without
19
 * modification, are permitted provided that the following conditions are met:
20
 *
21
 * Redistributions of source code must retain the above copyright notice, this
22
 * list of conditions and the following disclaimer.
23
 *
24
 * Redistributions in binary form must reproduce the above copyright notice,
25
 * this list of conditions and the following disclaimer in the documentation
26
 * and/or other materials
27
 * provided with the distribution.
28
 *
29
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
30
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
31
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
32
 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
33
 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
34
 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
35
 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
36
 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
37
 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
38
 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
39
 * POSSIBILITY OF SUCH DAMAGE.
40
 */
41

42
#ifndef __EHCA_CLASSES_PSERIES_H__
43
#define __EHCA_CLASSES_PSERIES_H__
44

45
#include "hcp_phyp.h"
46
#include "ipz_pt_fn.h"
47

48

49
struct ehca_pfqp {
50
	struct ipz_qpt sqpt;
51
	struct ipz_qpt rqpt;
52
};
53

54
struct ehca_pfcq {
55
	struct ipz_qpt qpt;
56
	u32 cqnr;
57
};
58

59
struct ehca_pfeq {
60
	struct ipz_qpt qpt;
61
	struct h_galpa galpa;
62
	u32 eqnr;
63
};
64

65
struct ipz_adapter_handle {
66
	u64 handle;
67
};
68

69
struct ipz_cq_handle {
70
	u64 handle;
71
};
72

73
struct ipz_eq_handle {
74
	u64 handle;
75
};
76

77
struct ipz_qp_handle {
78
	u64 handle;
79
};
80
struct ipz_mrmw_handle {
81
	u64 handle;
82
};
83

84
struct ipz_pd {
85
	u32 value;
86
};
87

88
struct hcp_modify_qp_control_block {
89
	u32 qkey;                      /* 00 */
90
	u32 rdd;                       /* reliable datagram domain */
91
	u32 send_psn;                  /* 02 */
92
	u32 receive_psn;               /* 03 */
93
	u32 prim_phys_port;            /* 04 */
94
	u32 alt_phys_port;             /* 05 */
95
	u32 prim_p_key_idx;            /* 06 */
96
	u32 alt_p_key_idx;             /* 07 */
97
	u32 rdma_atomic_ctrl;          /* 08 */
98
	u32 qp_state;                  /* 09 */
99
	u32 reserved_10;               /* 10 */
100
	u32 rdma_nr_atomic_resp_res;   /* 11 */
101
	u32 path_migration_state;      /* 12 */
102
	u32 rdma_atomic_outst_dest_qp; /* 13 */
103
	u32 dest_qp_nr;                /* 14 */
104
	u32 min_rnr_nak_timer_field;   /* 15 */
105
	u32 service_level;             /* 16 */
106
	u32 send_grh_flag;             /* 17 */
107
	u32 retry_count;               /* 18 */
108
	u32 timeout;                   /* 19 */
109
	u32 path_mtu;                  /* 20 */
110
	u32 max_static_rate;           /* 21 */
111
	u32 dlid;                      /* 22 */
112
	u32 rnr_retry_count;           /* 23 */
113
	u32 source_path_bits;          /* 24 */
114
	u32 traffic_class;             /* 25 */
115
	u32 hop_limit;                 /* 26 */
116
	u32 source_gid_idx;            /* 27 */
117
	u32 flow_label;                /* 28 */
118
	u32 reserved_29;               /* 29 */
119
	union {                        /* 30 */
120
		u64 dw[2];
121
		u8 byte[16];
122
	} dest_gid;
123
	u32 service_level_al;          /* 34 */
124
	u32 send_grh_flag_al;          /* 35 */
125
	u32 retry_count_al;            /* 36 */
126
	u32 timeout_al;                /* 37 */
127
	u32 max_static_rate_al;        /* 38 */
128
	u32 dlid_al;                   /* 39 */
129
	u32 rnr_retry_count_al;        /* 40 */
130
	u32 source_path_bits_al;       /* 41 */
131
	u32 traffic_class_al;          /* 42 */
132
	u32 hop_limit_al;              /* 43 */
133
	u32 source_gid_idx_al;         /* 44 */
134
	u32 flow_label_al;             /* 45 */
135
	u32 reserved_46;               /* 46 */
136
	u32 reserved_47;               /* 47 */
137
	union {                        /* 48 */
138
		u64 dw[2];
139
		u8 byte[16];
140
	} dest_gid_al;
141
	u32 max_nr_outst_send_wr;      /* 52 */
142
	u32 max_nr_outst_recv_wr;      /* 53 */
143
	u32 disable_ete_credit_check;  /* 54 */
144
	u32 qp_number;                 /* 55 */
145
	u64 send_queue_handle;         /* 56 */
146
	u64 recv_queue_handle;         /* 58 */
147
	u32 actual_nr_sges_in_sq_wqe;  /* 60 */
148
	u32 actual_nr_sges_in_rq_wqe;  /* 61 */
149
	u32 qp_enable;                 /* 62 */
150
	u32 curr_srq_limit;            /* 63 */
151
	u64 qp_aff_asyn_ev_log_reg;    /* 64 */
152
	u64 shared_rq_hndl;            /* 66 */
153
	u64 trigg_doorbell_qp_hndl;    /* 68 */
154
	u32 reserved_70_127[58];       /* 70 */
155
};
156

157
#define MQPCB_MASK_QKEY                         EHCA_BMASK_IBM( 0,  0)
158
#define MQPCB_MASK_SEND_PSN                     EHCA_BMASK_IBM( 2,  2)
159
#define MQPCB_MASK_RECEIVE_PSN                  EHCA_BMASK_IBM( 3,  3)
160
#define MQPCB_MASK_PRIM_PHYS_PORT               EHCA_BMASK_IBM( 4,  4)
161
#define MQPCB_PRIM_PHYS_PORT                    EHCA_BMASK_IBM(24, 31)
162
#define MQPCB_MASK_ALT_PHYS_PORT                EHCA_BMASK_IBM( 5,  5)
163
#define MQPCB_MASK_PRIM_P_KEY_IDX               EHCA_BMASK_IBM( 6,  6)
164
#define MQPCB_PRIM_P_KEY_IDX                    EHCA_BMASK_IBM(24, 31)
165
#define MQPCB_MASK_ALT_P_KEY_IDX                EHCA_BMASK_IBM( 7,  7)
166
#define MQPCB_MASK_RDMA_ATOMIC_CTRL             EHCA_BMASK_IBM( 8,  8)
167
#define MQPCB_MASK_QP_STATE                     EHCA_BMASK_IBM( 9,  9)
168
#define MQPCB_MASK_RDMA_NR_ATOMIC_RESP_RES      EHCA_BMASK_IBM(11, 11)
169
#define MQPCB_MASK_PATH_MIGRATION_STATE         EHCA_BMASK_IBM(12, 12)
170
#define MQPCB_MASK_RDMA_ATOMIC_OUTST_DEST_QP    EHCA_BMASK_IBM(13, 13)
171
#define MQPCB_MASK_DEST_QP_NR                   EHCA_BMASK_IBM(14, 14)
172
#define MQPCB_MASK_MIN_RNR_NAK_TIMER_FIELD      EHCA_BMASK_IBM(15, 15)
173
#define MQPCB_MASK_SERVICE_LEVEL                EHCA_BMASK_IBM(16, 16)
174
#define MQPCB_MASK_SEND_GRH_FLAG                EHCA_BMASK_IBM(17, 17)
175
#define MQPCB_MASK_RETRY_COUNT                  EHCA_BMASK_IBM(18, 18)
176
#define MQPCB_MASK_TIMEOUT                      EHCA_BMASK_IBM(19, 19)
177
#define MQPCB_MASK_PATH_MTU                     EHCA_BMASK_IBM(20, 20)
178
#define MQPCB_MASK_MAX_STATIC_RATE              EHCA_BMASK_IBM(21, 21)
179
#define MQPCB_MASK_DLID                         EHCA_BMASK_IBM(22, 22)
180
#define MQPCB_MASK_RNR_RETRY_COUNT              EHCA_BMASK_IBM(23, 23)
181
#define MQPCB_MASK_SOURCE_PATH_BITS             EHCA_BMASK_IBM(24, 24)
182
#define MQPCB_MASK_TRAFFIC_CLASS                EHCA_BMASK_IBM(25, 25)
183
#define MQPCB_MASK_HOP_LIMIT                    EHCA_BMASK_IBM(26, 26)
184
#define MQPCB_MASK_SOURCE_GID_IDX               EHCA_BMASK_IBM(27, 27)
185
#define MQPCB_MASK_FLOW_LABEL                   EHCA_BMASK_IBM(28, 28)
186
#define MQPCB_MASK_DEST_GID                     EHCA_BMASK_IBM(30, 30)
187
#define MQPCB_MASK_SERVICE_LEVEL_AL             EHCA_BMASK_IBM(31, 31)
188
#define MQPCB_MASK_SEND_GRH_FLAG_AL             EHCA_BMASK_IBM(32, 32)
189
#define MQPCB_MASK_RETRY_COUNT_AL               EHCA_BMASK_IBM(33, 33)
190
#define MQPCB_MASK_TIMEOUT_AL                   EHCA_BMASK_IBM(34, 34)
191
#define MQPCB_MASK_MAX_STATIC_RATE_AL           EHCA_BMASK_IBM(35, 35)
192
#define MQPCB_MASK_DLID_AL                      EHCA_BMASK_IBM(36, 36)
193
#define MQPCB_MASK_RNR_RETRY_COUNT_AL           EHCA_BMASK_IBM(37, 37)
194
#define MQPCB_MASK_SOURCE_PATH_BITS_AL          EHCA_BMASK_IBM(38, 38)
195
#define MQPCB_MASK_TRAFFIC_CLASS_AL             EHCA_BMASK_IBM(39, 39)
196
#define MQPCB_MASK_HOP_LIMIT_AL                 EHCA_BMASK_IBM(40, 40)
197
#define MQPCB_MASK_SOURCE_GID_IDX_AL            EHCA_BMASK_IBM(41, 41)
198
#define MQPCB_MASK_FLOW_LABEL_AL                EHCA_BMASK_IBM(42, 42)
199
#define MQPCB_MASK_DEST_GID_AL                  EHCA_BMASK_IBM(44, 44)
200
#define MQPCB_MASK_MAX_NR_OUTST_SEND_WR         EHCA_BMASK_IBM(45, 45)
201
#define MQPCB_MASK_MAX_NR_OUTST_RECV_WR         EHCA_BMASK_IBM(46, 46)
202
#define MQPCB_MASK_DISABLE_ETE_CREDIT_CHECK     EHCA_BMASK_IBM(47, 47)
203
#define MQPCB_MASK_QP_ENABLE                    EHCA_BMASK_IBM(48, 48)
204
#define MQPCB_MASK_CURR_SRQ_LIMIT               EHCA_BMASK_IBM(49, 49)
205
#define MQPCB_MASK_QP_AFF_ASYN_EV_LOG_REG       EHCA_BMASK_IBM(50, 50)
206
#define MQPCB_MASK_SHARED_RQ_HNDL               EHCA_BMASK_IBM(51, 51)
207

208
#endif /* __EHCA_CLASSES_PSERIES_H__ */
209

210
Product

Resources

Company
