Path: blob/master/drivers/infiniband/hw/mthca/mthca_catas.c
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/*1* Copyright (c) 2005 Cisco Systems. All rights reserved.2*3* This software is available to you under a choice of one of two4* licenses. You may choose to be licensed under the terms of the GNU5* General Public License (GPL) Version 2, available from the file6* COPYING in the main directory of this source tree, or the7* OpenIB.org BSD license below:8*9* Redistribution and use in source and binary forms, with or10* without modification, are permitted provided that the following11* conditions are met:12*13* - Redistributions of source code must retain the above14* copyright notice, this list of conditions and the following15* disclaimer.16*17* - Redistributions in binary form must reproduce the above18* copyright notice, this list of conditions and the following19* disclaimer in the documentation and/or other materials20* provided with the distribution.21*22* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,23* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF24* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND25* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS26* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN27* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN28* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE29* SOFTWARE.30*/3132#include <linux/jiffies.h>33#include <linux/timer.h>34#include <linux/workqueue.h>3536#include "mthca_dev.h"3738enum {39MTHCA_CATAS_POLL_INTERVAL = 5 * HZ,4041MTHCA_CATAS_TYPE_INTERNAL = 0,42MTHCA_CATAS_TYPE_UPLINK = 3,43MTHCA_CATAS_TYPE_DDR = 4,44MTHCA_CATAS_TYPE_PARITY = 5,45};4647static DEFINE_SPINLOCK(catas_lock);4849static LIST_HEAD(catas_list);50static struct workqueue_struct *catas_wq;51static struct work_struct catas_work;5253static int catas_reset_disable;54module_param_named(catas_reset_disable, catas_reset_disable, int, 0644);55MODULE_PARM_DESC(catas_reset_disable, "disable reset on catastrophic event if nonzero");5657static void catas_reset(struct work_struct *work)58{59struct mthca_dev *dev, *tmpdev;60LIST_HEAD(tlist);61int ret;6263mutex_lock(&mthca_device_mutex);6465spin_lock_irq(&catas_lock);66list_splice_init(&catas_list, &tlist);67spin_unlock_irq(&catas_lock);6869list_for_each_entry_safe(dev, tmpdev, &tlist, catas_err.list) {70struct pci_dev *pdev = dev->pdev;71ret = __mthca_restart_one(dev->pdev);72/* 'dev' now is not valid */73if (ret)74printk(KERN_ERR "mthca %s: Reset failed (%d)\n",75pci_name(pdev), ret);76else {77struct mthca_dev *d = pci_get_drvdata(pdev);78mthca_dbg(d, "Reset succeeded\n");79}80}8182mutex_unlock(&mthca_device_mutex);83}8485static void handle_catas(struct mthca_dev *dev)86{87struct ib_event event;88unsigned long flags;89const char *type;90int i;9192event.device = &dev->ib_dev;93event.event = IB_EVENT_DEVICE_FATAL;94event.element.port_num = 0;95dev->active = false;9697ib_dispatch_event(&event);9899switch (swab32(readl(dev->catas_err.map)) >> 24) {100case MTHCA_CATAS_TYPE_INTERNAL:101type = "internal error";102break;103case MTHCA_CATAS_TYPE_UPLINK:104type = "uplink bus error";105break;106case MTHCA_CATAS_TYPE_DDR:107type = "DDR data error";108break;109case MTHCA_CATAS_TYPE_PARITY:110type = "internal parity error";111break;112default:113type = "unknown error";114break;115}116117mthca_err(dev, "Catastrophic error detected: %s\n", type);118for (i = 0; i < dev->catas_err.size; ++i)119mthca_err(dev, " buf[%02x]: %08x\n",120i, swab32(readl(dev->catas_err.map + i)));121122if (catas_reset_disable)123return;124125spin_lock_irqsave(&catas_lock, flags);126list_add(&dev->catas_err.list, &catas_list);127queue_work(catas_wq, &catas_work);128spin_unlock_irqrestore(&catas_lock, flags);129}130131static void poll_catas(unsigned long dev_ptr)132{133struct mthca_dev *dev = (struct mthca_dev *) dev_ptr;134int i;135136for (i = 0; i < dev->catas_err.size; ++i)137if (readl(dev->catas_err.map + i)) {138handle_catas(dev);139return;140}141142mod_timer(&dev->catas_err.timer,143round_jiffies(jiffies + MTHCA_CATAS_POLL_INTERVAL));144}145146void mthca_start_catas_poll(struct mthca_dev *dev)147{148phys_addr_t addr;149150init_timer(&dev->catas_err.timer);151dev->catas_err.map = NULL;152153addr = pci_resource_start(dev->pdev, 0) +154((pci_resource_len(dev->pdev, 0) - 1) &155dev->catas_err.addr);156157dev->catas_err.map = ioremap(addr, dev->catas_err.size * 4);158if (!dev->catas_err.map) {159mthca_warn(dev, "couldn't map catastrophic error region "160"at 0x%llx/0x%x\n", (unsigned long long) addr,161dev->catas_err.size * 4);162return;163}164165dev->catas_err.timer.data = (unsigned long) dev;166dev->catas_err.timer.function = poll_catas;167dev->catas_err.timer.expires = jiffies + MTHCA_CATAS_POLL_INTERVAL;168INIT_LIST_HEAD(&dev->catas_err.list);169add_timer(&dev->catas_err.timer);170}171172void mthca_stop_catas_poll(struct mthca_dev *dev)173{174del_timer_sync(&dev->catas_err.timer);175176if (dev->catas_err.map)177iounmap(dev->catas_err.map);178179spin_lock_irq(&catas_lock);180list_del(&dev->catas_err.list);181spin_unlock_irq(&catas_lock);182}183184int __init mthca_catas_init(void)185{186INIT_WORK(&catas_work, catas_reset);187188catas_wq = create_singlethread_workqueue("mthca_catas");189if (!catas_wq)190return -ENOMEM;191192return 0;193}194195void mthca_catas_cleanup(void)196{197destroy_workqueue(catas_wq);198}199200201