Path: blob/master/drivers/infiniband/hw/mthca/mthca_user.h
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/*1* Copyright (c) 2005 Topspin Communications. All rights reserved.2* Copyright (c) 2005, 2006 Cisco Systems. All rights reserved.3*4* This software is available to you under a choice of one of two5* licenses. You may choose to be licensed under the terms of the GNU6* General Public License (GPL) Version 2, available from the file7* COPYING in the main directory of this source tree, or the8* OpenIB.org BSD license below:9*10* Redistribution and use in source and binary forms, with or11* without modification, are permitted provided that the following12* conditions are met:13*14* - Redistributions of source code must retain the above15* copyright notice, this list of conditions and the following16* disclaimer.17*18* - Redistributions in binary form must reproduce the above19* copyright notice, this list of conditions and the following20* disclaimer in the documentation and/or other materials21* provided with the distribution.22*23* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,24* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF25* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND26* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS27* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN28* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN29* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE30* SOFTWARE.31*/3233#ifndef MTHCA_USER_H34#define MTHCA_USER_H3536#include <linux/types.h>3738/*39* Increment this value if any changes that break userspace ABI40* compatibility are made.41*/42#define MTHCA_UVERBS_ABI_VERSION 14344/*45* Make sure that all structs defined in this file remain laid out so46* that they pack the same way on 32-bit and 64-bit architectures (to47* avoid incompatibility between 32-bit userspace and 64-bit kernels).48* In particular do not use pointer types -- pass pointers in __u6449* instead.50*/5152struct mthca_alloc_ucontext_resp {53__u32 qp_tab_size;54__u32 uarc_size;55};5657struct mthca_alloc_pd_resp {58__u32 pdn;59__u32 reserved;60};6162struct mthca_reg_mr {63/*64* Mark the memory region with a DMA attribute that causes65* in-flight DMA to be flushed when the region is written to:66*/67#define MTHCA_MR_DMASYNC 0x168__u32 mr_attrs;69__u32 reserved;70};7172struct mthca_create_cq {73__u32 lkey;74__u32 pdn;75__u64 arm_db_page;76__u64 set_db_page;77__u32 arm_db_index;78__u32 set_db_index;79};8081struct mthca_create_cq_resp {82__u32 cqn;83__u32 reserved;84};8586struct mthca_resize_cq {87__u32 lkey;88__u32 reserved;89};9091struct mthca_create_srq {92__u32 lkey;93__u32 db_index;94__u64 db_page;95};9697struct mthca_create_srq_resp {98__u32 srqn;99__u32 reserved;100};101102struct mthca_create_qp {103__u32 lkey;104__u32 reserved;105__u64 sq_db_page;106__u64 rq_db_page;107__u32 sq_db_index;108__u32 rq_db_index;109};110111#endif /* MTHCA_USER_H */112113114